Enhanced Performance of Gadolinia-Doped Ceria Diffusion Barrier

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Enhanced Performance of Gadolinia-doped Ceria Diffusion Barrier Layers Fabricated by Pulsed Laser Deposition for Large-Area Solid Oxide Fuel Cells Miguel Morales, Arianna Pesce, Aneta Slodczyk, Marc Torrell, Paolo Piccardo, Dario Montinaro, Albert Tarancón, and Alex Morata ACS Appl. Energy Mater., Just Accepted Manuscript • DOI: 10.1021/acsaem.8b00039 • Publication Date (Web): 23 Apr 2018 Downloaded from http://pubs.acs.org on April 28, 2018

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ACS Applied Energy Materials

Enhanced Performance of Gadolinia-doped Ceria Diffusion Barrier Layers Fabricated by Pulsed Laser Deposition for Large-Area Solid Oxide Fuel Cells Miguel Moralesa, Arianna Pescea, Aneta Slodczyka, Marc Torrella, d

c

a,b

,a

Paolo Piccardo , Dario Montinaro , Albert Tarancón , Alex Morata*

a

IREC, Catalonia Institute for Energy Research, Dept of Advanced Materials for Energy

Applications, Jardins de les Dones de Negre 1, Planta 2, 08930, Sant Adrià del Besòs, Barcelona, Spain. b

ICREA, Passeig Lluís Companys 23, 08010 Barcelona, Catalonia, Spain c

d

SOLIDpower SpA, Viale Trento 117, 38017 Mezzolombardo, Italy.

Università degli Studi di Genova, Department of Chemistry and Industrial Chemistry, Via Dodecaneso, 31 - 16146 Genova Corresponding author: [email protected]

Abstract Diffusion barrier layers are typically introduced in Solid Oxide Fuel Cells (SOFCs) to avoid reaction between state-of-the-art cathode and electrolyte materials, La1-xSrxCo1-yFeyO3-δ and yttria-stabilized zirconia (YSZ), respectively. However, commonly used layers of gadolinia-doped ceria (CGO) introduce overpotentials that significantly reduce the cell performance. This performance decrease is mainly due to the low density achievable with traditional deposition techniques, such as screen printing, at acceptable fabrication temperatures. In this work, perfectly dense and reproducible barrier layers for state-of-the-art cells (ca. 80 cm2) were implemented, for the first time, using Large-Area Pulsed Laser Deposition (LA-PLD). In order to minimize cation interdiffusion, the lowtemperature deposited barrier layers were thermally stabilized in the range between 1100-1400ºC. Significant enhanced performance is reported for cells stabilized at 1150ºC showing excellent power densities of 1.25 Wcm-2 at 0.7 V and at a operation temperature of 750ºC. Improved cells were finally included in a stack and operated in realistic conditions for 4500h revealing low degradation rates (0.5%/1000h) comparable to reference cells. This approach opens new perspectives in manufacturing highly reproducible and stable barrier layers for a new generation of SOFCs. Keywords: Pulsed Laser Deposition (PLD), Solid Oxide Fuel Cells (SOFCs), diffusion barrier layer, Gadolinia doped Ceria (CGO), cation diffusion at CGO/YSZ interface, SrZrO3.

ACS Paragon Plus Environment

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1.

Introduction

Solid oxide fuels cells (SOFCs) are efficient energy conversion devices that directly transform chemical energy into electricity.1 The future of SOFCs depends on the development of efficient and robust materials capable to withstand long times at high temperature and typical harsh ambient during operation. Currently, the developments in SOFCs are focused on increasing the power density and minimizing degradation during the cell operation. An important contribution to the overall cell resistance comes from the reaction of the commonly used mixed ionic–electronic La1xSrxCo1-yFeyO3

(LSCF) cathode2 with the state-of-the-art yttria-stabilized zirconia (YSZ) electrolyte

during the SOFC manufacturing at high temperatures.3,4,5 Insulating phases such as Strontium Zirconate (SrZrO3) and Lanthanum Zirconate (La2Zr2O7) are generated, which potentially form ion blocking layers in regions of the system as critical as the cathode-electrolyte interface. An effect of this element diffusion is the formation of secondary phases with low electrical conductivity like Co3O4, Co2Fe2O4, or La0.6Sr0.4-xFeO3 at regions where Sr can be expelled from the LSCF structure.6,7,8,9,10 A solution to avoid the Sr and Zr diffusion is the use of a barrier layer based on Gd, Sm or Y-doped CeO2 (CGO, SDC, YDC, respectively) between the cathode and the electrolyte.11,12 Commonly employed wet deposition techniques (e.g., screen printing, spray deposition and dip coating) require high sintering temperatures (≥ 1200°C) to achieve effective dense diffusion barrier layers. These high temperatures typically activate parallel inter-diffusion processes between: i) ceria and zirconia layers, which eventually lead to the formation of CGOx:YSZ(1−x) solid solutions, the well-known Kirkendall voids or even dopant migration13,14,15,16,17,18 or ii) between the cathode and the electrolyte ultimately resulting in the decomposition of the electrode material.9,19,20,21,22,23 In both cases, an increase of the overall resistances is expected resulting in a diminished performance of the cell. This deleterious effect represents an upper bound of the densification temperature of the barrier layer. In addition, strong limitations of wet techniques to deposit homogeneous thin layers considerably limit the potential reduction of the contribution of the barrier layer to the overall resistance by reducing the thickness. Although some works like Van Berkel et al.24 have presented screen-printed ceria barrier layers as thin as 1.4 µm, the inter-diffusion barrier layers fabricated by traditional wet deposition techniques generally present a thickness range of 210 µm.25 In addition, the porosity of these screen-printed and sequentially sintered barrier layers may be in the range 20-30%, even after sintering around 1300ºC.26 Consequently, in order to improve the densification of this type of layers some researchers have proposed the use of sintering aids, such as cobalt or iron oxides.17,26,27 For instance, Suresh et al.28 and Dasari et al.29 reported a positive influence of Sr and Li on CGO densification at temperatures as low as 400ºC and 600ºC, respectively. In any case, ionic conductivities of so-fabricated CGO barrier layers are lower than expected.


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A promising alternative to wet techniques is the use of vacuum deposition methods able to fabricate dense and thin (even at sub-micrometric scale) barrier layers at low temperatures, currently in the range between room temperature and 1000ºC. Commonly available techniques are Pulsed Laser Deposition (PLD),30 Magnetron Sputtering (MS),31 Electron Beam Physical Vapour Deposition (EB-PVD)32,33 and (4) Chemical Vapor Deposition (CVD).34 Although not traditionally implemented in the SOFC industry, some of these techniques are mature and considered mainstream technologies in several industrial sectors. For example, inline sputter systems are important in today’s solar cell fabrication for the deposition of a broad range of materials, fulfilling large scale production requirements in such a competitive industry as photovoltaics. More generally, magnetron sputtering is a well-established technology used for coating of all kind of glasses, with large production rates ranging from some hundred thousand to more than one million square meters per year.35 As an example of application in SOFC, sputter deposition of YSZ electrolytes on porous NiO/YSZ SOFC anodes (13x13 cm2) has been shown as a very promising technique for the fabrication of SOFC stacks.36 Complementary, PLD has also been explored in industrial scenarios requiring complex oxides deposition using multi-plume and cassette-tocassette or roll-to-roll loading strategies.37,38 In this sense, systems specially designed for the deposition of CeO2 or YBaCuO capable to produce layers between 1 and 2 µm in 10 m2 substrates for 10 h per day process have been reported.39 Despite the fabrication at low temperatures, previous works on dense CGO barrier layers deposited by physical methods have reported the formation of SrZrO3. For instance, Knibbe et al.40 observed fast Sr diffusion to the YSZ electrolyte along grain boundaries of dense epitaxial CGO layers (thickness of 600 nm) deposited by PLD, which formed SrZrO3 grains discontinuously at the YSZ/CGO interface. They concluded that better solutions are barrier layers with a phase/lattice mismatch unfavourable to epitaxy or alternatively elongate/extend the grain boundaries to eliminate the fast diffusion paths. In the same way, Wang et al.6 evaluated pellet-type cells with dense CGO interlayers of 1 µm thickness processed by PLD. Although CGO/YSZ systems were annealed at 1200ºC for 5 h to modify the CGO microstructure, the results clearly showed that the SrZrO3 formation at the LSFC/CGO interface is accelerated under polarization at extreme operation temperatures (900-1000ºC). Other researchers have also tried to block the Sr diffusion along the column/grain boundaries by tuning the CGO barrier layers prepared by magnetron sputtering. Both Sønderby et al.41 and Uhlenbruck et al.42 observed that the Sr diffusion in magnetron sputtered CGO barrier layers is strongly reduced by tuning the deposition temperature and substrate bias voltage/power. The increase of substrate bias and deposition temperature can inhibit the columnar film growth. By modifying of CGO film thickness and microstructure, the reaction temperature of Sr with CGO barrier layer can decrease, and the formation of SrZrO3 may



be suppressed. In another work, Sønderby et al.43 reported that 600 nm of MS CGO layers effectively blocked Sr diffusion, when depositions were carried out at 400ºC and applying a substrate bias of -50 V. Complementary, Nurk et al.44 systematically investigated the influence of the deposition method (PLD, MS, spray-pyrolisis and screen-printing) and barrier layer sintering temperature on Sr, Zr and Ce mass transfer, using LSC cathode sintered at two fixed sintering temperatures of 950 and 1100ºC. According to this work and overall, the best performances of SOFCs, with CGO barriers processed by different techniques, required specifically optimized layer thicknesses and specific thermal treatment programs for sintering of barrier layer as well as for cathode.

In this work, the main objective is the fabrication of thermally stable effective CGO barrier layers by Large Area PLD. For this purpose, homogeneous and dense PLD CGO barrier layers deposited at low temperature (T=600 ºC) have been thermally stabilized between 1100 and 1400ºC. The effect of the thermal treatment of the PLD barrier layers on the cation diffusion inhibition (Sr, Zr, Ce, GdU) at the LSCF/CGO/YSZ interfaces has been comparatively investigated by combining different analytical techniques such as X-Ray Diffraction (XRD), micro-Raman spectroscopy and Secondary Electron Microscopy and Energy Dispersive X-ray spectroscopy (SEM-EDX). Additionally, the functionality of these stabilized barrier layers in full cells have been electrochemically tested in short- and mid-term experiments to determine the optimum fabrication conditions. Using these conditions, large-area cells have been fabricated to show the scalability of the process. Finally, short stacks made of these cells have been fabricated and tested for 4500 h under close to real operation conditions.

2. Experimental In order to simplify the description of the experimental procedure, this section is separated in four parts. In the first one, the details of cell manufacturing, mainly focussing on the barrier layer fabrication, are presented. Afterwards, details on the characetrization of samples with different annealing temperatures are exposed. In the third part, the conditions for the electrochemical characterization experiments in button cells are detailed, including long-term tests. Finally, the scalling-up process of the LA-PLD deposition to large-area cells is defined, along with the longterm tests in a short stack. 2.1 Cell fabrication 250 µm porous nickel-yttria-stabilized zirconia (Ni-YSZ) cermet anode-supported cells are composed of a dense YSZ electrolyte, a PLD CGO (Ce0.80Gd0.20O1.95) barrier layer, and a lanthanum strontium cobalt ferrite oxide (La0.6Sr0.4Co0.2Fe0.8O3-δ) cathode. The fabrication of the


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cell has been optimized for the maximization of the performance and stability, using commercially viable manufacturing techniques, except for the CGO barrier. Anode and electrolyte were manufactured by tape-casting using water suspensions and co-sintered at ca. 1400ºC. Additionally, button cells with state-of-the-art screen-printed barrier were also fabricated to be compared to the cells with the PLD-deposited barriers. Further experimental details can be found in previous works.17,45,46,47

The barrier layer (thickness = 2 µm) between cathode and electrolyte was fabricated by PLD technique, using a PVD5000 system from PVD Products. A KrF excimer laser (λ = 248 nm) was used for the ablation of CGO material, applying a pulse energy density of 3.0 Jcm-2 on the CGO target and a frequency of 10 Hz. During the deposition process, the distance between the NiOYSZ/YSZ half-cell substrate and the target was 90 mm, and the half-cell substrates were kept at 600ºC and under an oxygen partial pressure of 2.7 Pa. Afterwards, an annealing thermal treatment, in the range between 1100 and 1400ºC, was applied to enhance the chemical and microstructural stability of the barrier layer. Finally, the cathode was screen-printed on top of this supporting structure and sintered.5

2.2 Analysis of annealed PLD barriers in button cells The effect of the annealing temperature of the PLD CGO barrier layer on the diffusion of Zr, Ce, Gd and Sr was systematically studied with button cells of 2 cm2 cathode active area. For this purpose, a first set of NiO-YSZ/YSZ/CGO half-cells with as-deposited (600°C) and annealed barrier layers at different temperatures: 1100, 1150, 1200, 1300, 1400ºC for 2 h and 1400ºC for 10 h, was analysed to compare the cation diffusion (Zr, Ce and Gd) at the CGO barrier region during the annealing. A second set of NiO-YSZ/YSZ/CGO/LSCF cells with as-deposited and annealed barrier layers (11001400ºC for 2h), and cathode sintered at 1150ºC, which is above the current sintering temperature of state-of-the-art cells23,33,45 for further accelerating the mass transports, was characterized for studying the Sr diffusion and other elements (Zr, Ce and Gd) at the barrier layer, during the cathode sintering. For each experimental parameter set at least two identically prepared cells were analysed.

The cross-section analysis of the cation diffusion at the cathode/interlayer/electrolyte region was complementarily performed by X-ray Diffraction (XRD), Raman Spectroscopy and Scanning Electron Microscopy equipped with Energy Dispersive X-ray Analyser (SEM-EDX). The XRD patterns on the surface top of CGO/YSZ/NiO-YSZ half-cells were recorded using an diffractometer (Bruker D8 Advance) equipped with Cu Kα radiation (λ = 1.5418 Ǻ). The identification of the



crystalline phases formed during PLD and annealing processes was carried out by the FULLPROF Rietveld refinement program48,49,50 and the Powder Diffraction File (PDF) database.51 The Raman spectra were recorded using a high resolution, confocal Spectrometer HR800 (LabRAM Series, Horiba Jobin Yvon). The 532 nm excitation line and a 100x objective were employed. Parallel to the manual measurements performed on the LSCF/CGO/YSZ cross section (the numerous spectra were recorded along Y direction each 1µm or 0.5 µm depending on the analysed layer), 2D XY Raman maps were also recorded in order to assess the possible formation of (Zr,Ce)O2-based solid solutions and the formation of secondary insulating phases. The microstructure of samples were examined by Scanning Electron Microscopy (SEM, Zeiss Auriga) equipped with an Oxford Inca Pentafet X3 Energy Dispersive X-ray Analyser (EDX). The spatial distributions of Ce, Gd, Zr, Y and Sr elements were determined by SEM-EDX mapping over CGO/YSZ interface and LSCF/CGO/YSZ interfaces in order to evaluate the chemical reaction after annealing and cathode sintering, respectively.

2.3 Electrochemical tests on button cells Two button cells with annealed barrier layer and with as-deposited one as a reference, and cathode sintered below 1100ºC, were selected to be electrochemically tested from the results of preliminary elemental analyses. In the case of the annealed cell, it should present the best balance between low cation mobility (Sr, Zr, Gd...) and microstructural stabilization of the barrier layer in order to minimize the possible effects of the formation of SrZrO3 and the loss of Gd dopant, during manufacturing and/or in operation. The electrochemical fuel cell tests were carried out in a commercial ProboStatTM (NorECs AS) sample holder placed inside a tubular furnace and employing a potentiostat/galvanostat PARSTAT 2273. Current collectors at the electrodes were made of platinum meshes, which were painted with Ni and Pt slurries at the anode and cathode, respectively. Ceramabond™ ring covering the sample edge was used to ensure gas tightness between the fuel and oxygen chambers. The long-term tests were performed at 750ºC for more than 1000 h in galvanostatic conditions, using dry H2 (16 Nmlmin-1cm-2) as a fuel and synthetic air (40 Nmlmin-1cm-2) as an oxidant. A chronopotentiometry at 0.5 A.cm² with a time step of 20 s was performed. In addition, current-voltage (j-V) and electrochemical impedance spectroscopy (EIS) curves of cells were periodically recorded during the tests. EIS data acquisition was done with ZView software to extract serial resistance and polarization resistance degradation values. For each experimental parameter set at least two identically prepared cells were tested.

2.4 Characterization of large-area cells with annealed barriers Three large-area cells were fabricated in identical conditions of button cells with the optimally annealed PLD CGO barrier layer, following the preliminary results of button cells, and the LSCF


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cathode was sintered below 1100ºC. The cells were electrochemically tested at long-term in a stack under operation conditions close to real ones. Simultaneously, in the same stack, three large-area cells with state-of-the-art screen-printed barrier were also tested.

The LA-PLD deposition process was carried out in a PVD5000 system from PVD Products, designed for holding round samples of 10 cm in diameter and capable to host four targets of up-to 10 cm. The relative distance from the target to the sample was 90 mm. The layer was deposited with an energy reaching the target of 200 mJ and an oxygen pressure in the chamber of 20 mTorr and 600 ºC has been imposed during the deposition by means of infrared lamps included in the system. The thickness map of the layers deposited in large-area cells was performed by means of spectroscopic ellipsometry, which is a non-destructive optical technique. The frequency range used for these measurements was from 1.5 to 3.0 eV, imposing an incident angle of 70º. A Tauc Lorenz dispersion model was employed for simulating the CGO optical behavior.52

Figure 1. Single repeating element consisting of a planar SOFC mounted on a stainless steel cassette.

The performances of the LA-PLD cells with 80 cm2 active area were tested on a stack consisted of 33 Repeating Elements (REs) grouped in 11 clusters made by 3 cells, including cells with identical design and composition. Three of these clusters include cells with a reference barrier layer made by screen printing, while one cluster is composed by cells including the barrier layer made by PLD. Two of the reference clusters were mounted on the top and on the bottom of the stack tower to exclude the variability due to thermal gradients. All other clusters were randomly mounted in the tower. The structure of a single repeating element (RE) is shown in Figure 1. Stack interconnects are based on a ferritic stainless steel cassette design and are coated by a ceramic protective coating to prevent



chromium evaporation. A glass ceramic seal is deposited at the cell-edge and at the gas manifold to separate the fuel from the air atmosphere. Degradation tests were carried out in the stack working under realistic operation conditions, partial (50%) Natural Gas (desulfurized upstream the reformer) Steam Reforming at a current density of 0.4 Acm-2, corresponding to 80% Fuel Utilization, and at a nominal operation temperature of 750 ºC (that corresponds to the temperature of air-out). For more details, see previous works.45,46,47

3. Results and discussion 3.1 Effect of annealing temperature on the CGO barrier layer The introduction of an optimized annealing process is proposed as a strategy to improve microstructural stability and reduce cation diffusion during the cell fabrication. This section will be focused on the influence of different annealing temperatures in the LA-PLD deposited CGO layers. 3.1.1 Microstructural and structural effects Figure 2a shows top-surface XRD diffractograms in a short range of angles, including the major diffraction peaks for CGO and YSZ, for samples treated at different temperatures as well as for the as-deposited sample. Extended range diffractograms are included in Figure S1 (see the Supporting Information). The results reveal a clear broadening of the peaks for barriers annealed at 1400ºC. The widening is accompanied by a shift of the CGO and YSZ peaks toward higher and lower angles, respectively. This is a characteristic evidence of the formation of the (Zr,Ce)O2based solid solution. Both effects are more pronounced when the sample is submitted to a 10h annealing process, indicating an increase of the extent of this phenomena with time. Opposite, the XRD data do not evidence the formation of (Zr,Ce)O2-based solid solution on layers annealed at temperatures equal or below 1300ºC, suggesting composite-like CGO-YSZ in case of interdiffusion.

Figure 2b-e show cross-section SEM images of the barrier layers for the whole set of annealing conditions. The thickness of the layers remains unchanged (ca. 2 µm) after annealing, as expected for fully dense structures. An absence of cracks or pores is found along the layers and a good adhesion with the YSZ electrolyte is presented. However, remarkable microstructural differences are visible after high temperature processing. As shown in Figure 2b, the cross-section microstructures of the as-deposited layer (non-annealed) present columnar grains perpendicularly oriented to the substrate, which is typical from low pressure PLD deposition. Grain size lower than 100 nm are observed in this case. This columnar shape disappears with annealing processes (Figure 2 c-e). Some indications of the initial structure are still visible in samples annealed at 1150ºC, which seems to be a transition temperature to a coarse grain polycrystalline structure well visible starting from 1200ºC (Figure 2d-e). This evolution of the microstructure can have a


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significant influence in the diffusion of species, the formation of undesired secondary phases and the loss of dopants, as grain boundaries have been described as fast diffusion paths.16,17,40

(a)

(e)

•

• CGO ♦ YSZ

♦

1400°°C (10h)

Intensity (a.u.)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


1400°°C (2h)

1 µm

(d)

1300°°C (2h) 1 µm

1200°°C (2h) (c) 1150°°C (2h)

28

29

1100°°C (2h)

1 µm

As-deposited

(b)

30

2θ (°)

31 1 µm

Figure 2. (a) Detail of the main peaks of CGO and YSZ from top-surface XRD diffractograms of samples after applying different thermal annealing processes. Cross-section SEM of PLD CGO barrier layers corresponding to: (b) as deposited samples and samples annealed at several temperatures for 2 h: (c) 1150 ºC, (d) 1200 ºC, and (e) 1300 ºC. 3.1.2 Zr, Ce and Gd diffusion after barrier annealing Figure 3 shows Raman spectra recorded in cross section for the upper part of the barrier layer, i.e. at a distance of 1.5 µm from the barrier-layer/electrolyte interface, for as-deposited and annealed samples. The most intense peak detected at ca. 460 cm-1 can be assigned to the main F2g peak of cubic CGO.53 The presence of weaker bands observed at 142, 256 and 617 cm-1 reveals the existence of tetragonal bis YSZ. This Raman signature entails the coexistence of both phases (i.e. YSZ and CGO) in a composite-like state, as previously reported by Tompsett et al.54 As it can be clearly seen the peaks corresponding to YSZ become progressively more prominent at higher temperatures, from 1100 to 1300ºC, qualitatively indicating a higher diffusion of YSZ into CGO. In particular, the YSZ accumulations at 1200 and 1300ºC should be taken into account because the Zr presence deep inside the barrier layer may promote the fast nucleation and growth of SrZrO3 during the cathode sintering.


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Normalized Raman intensity (a.u.)


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F2g --- CGO --- 8YSZ Eg

A1g

Eg

1300°°C (2h) 1200°°C (2h) 1150°°C (2h) 1100°°C (2h) As-deposited

200

400

600

800

1000

-1

Raman shift (cm ) Figure 3. Raman microprobe spectra, in the cross section of the layers at the position of 1.5 µm from interface with electrolyte, into the barrier layers annealed at different temperatures. Further information is provided by Raman spectroscopy about the nature of the ceria-based compounds along the barrier layer region (Figure 4). As shown in Fig. 4a, the main CGO peak positions recorded at the top of the barrier layer are consistent with doped ceria (middle CGO position ca. 460 cm-1; pure CeO2 is detected at 465 cm-1). The presence of the (Zr,Ce)O2-based solid solution, which presents a significant peak broadening and a shift to higher wavenumbers (ca. 470 cm-1), is only observed for the samples annealed at 1400ºC. A moderated peak shift to higher energies (ca. 464 cm-1), without the changes in the FWHM, is observed at 1300ºC. This is an indication of a reduction of the Gd concentration in the CGO compound. These Raman measurements are in good agreement with the XRD studies presented in the previous section. Interestingly, the behaviour of the CGO peak shifts recorded at the CGO/YSZ interface (Fig. 4b) evidences the occurrence of the same phenomena (i.e. dopant loss and solid solution generation) at lower temperatures. For instance, at 1200ºC, the position of CGO peak is indeed very close to the one corresponding to undoped ceria (CeO2).17,53 Moreover, the results are in concordance with SEM-EDX line scans showed in Figure S2, in which the relative amount of Gd and Zr as a function of the position into barrier for different annealing temperatures are represented.


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(b)

Top-surface F2g (CeO2) F2g (Ce0,95Zr0,05O2)

1400°C (10h) 1400°C

1300°C 1200°C 1150°C 1100°C As-deposited

440

460

480

500 -1

Raman shift (cm )


(a)


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


CGO/YSZ interface F2g (CeO2) F2g (Ce0,95Zr0,05O2)

1300°C 1200°C 1150°C 1100°C As-deposited 440

460

480

500 -1

Raman shift (cm )

Figure 4. Raman spectra at CGO peak region recorded: (a) at the top-surface, and (b) at cross-

sectional CGO/YSZ interface of barrier layers annealed at different temperatures for 2 h.

3.2 Sr diffusion and SrZrO3 formation after cathode sintering

With the aim of precisely determine the ionic spatial distribution and generated phases into the CGO barrier layer and at LSCF/CGO and CGO/YSZ interfaces, compositional and microstructural analyses of the barriers after cathode sintering were carried out by SEM-EDX and Raman analyses. Figure 5 shows representative Raman spectra and SEM-EDX mapping of these interfaces. It can be clearly observed that the annealing temperature of CGO barrier layer has a strong influence on the zirconium diffusion that leads to the formation of SrZrO3 during the cathode sintering. As shown in Fig. 5a, Raman spectra of barriers annealed at 1300 and 1400ºC clearly indicate the significant presence of SrZrO3 (a few characteristic peaks, for example, the most intense at ca. 160, 413, 555 and around 700 cm-1 are well observed). In contrast, the analyses of as-deposited and annealed at 1100-1200ºC barrier layers do not show the presence of this zirconate. The SEM-EDX mappings confirm the formation of Sr and Zr containing clusters in asdeposited and annealed at 1300ºC barrier layers (Fig. 5b), which are not present in 1150ºC annealed samples. The significant amount of zirconium close to the top-surface CGO layer, after annealing at 1300ºC (Figure 3), is expected to promote both the formation of SrZrO3 at the cathode/barrier-layer interface and the growth of strontium zirconate at the barrier-layer/electrolyte interface, as previously reported by Wang et al.6 Regarding the as-deposited layers, significant accumulations of Sr and SrZrO3 at both cathode- and electrolyte- interfaces are observed by SEMEDX (Figure 5b). The enhanced presence of SrZrO3 clusters in as-deposited samples could be



related to the columnar grain morphology, which involves highly diffusive grain boundaries, as previously shown by Knibbe et al.40 According to the results discussed above, 1150ºC seems to be an optimal temperature for the layer stabilization, representing a balance between the elimination of fast diffusion paths of Sr after annealing, and the presence of low amounts of Zr near the cathode/barrier interface before cathode sintering (Figures 3 and 5b). Next section presents electrochemical tests showing the consequences of the implementation of this thermally optimized barrier layer.

(a)

(b) F2g

Intensity (a.u.)

B1g

1400°°C(10h) 1400°°C 1300°°C

2 µm

2 µm

2 µm

As-dep.

Ag

--- CGO --- SrZrO3

1200ºC 1150°°C 1100ºC As-dep. 200

300

400

500

600

Zr

1150°°C

Ag

Sr

1300°°C

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

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700

Raman shift (cm-1)

Figure 5. (a) Raman spectra, and (b) cross-section SEM-EDX of as-deposited and annealed CGO

barriers, after sintering of LSCF cathode at 1150ºC. 3.4 Electrochemical properties of button cells

For first electrochemical tests, button cells prepared with LA-PLD deposited CGO barrier layers are characterized. According to the previous study, an annealed cell at 1150ºC and a second asdeposited cell are selected for comparison. In addition, a cell with standard screen-printed barrier layer is also used for comparison. Figure 6a presents j-V curves for these samples. The cell with annealed barrier achieves a high power density (1.25 Wcm-2 at 0.7 V and 750ºC), which is around 70% larger than those obtained for both the cell with as-deposited layer (0.73 Wcm-2) and state-ofthe-art screen-printed one (0.72 Wcm-2). These values are very close to the performances reached by cells presented in works based in PLD technology from Hjelm et al.55 and Han et al.56, which are c.a. 1.3 Wcm -2 at 0.7 V at 750 ºC, using LSC and LSCF as cathodes. On the other side, the electrochemical impedance spectra of the cells, at OCV and operating at 0.5 Acm-2 (Fig. 6b and c), reveals both lower ohmic and polarization resistances of the cells with annealed PLD barrier layer compared to those of as-deposited PLD barrier. Taking into account the good adhesion of the barrier layer with the cathode and the electrolyte for both cells (see Fig. S3a-b),


Page 13 of 23

the reduction can be attributed to the punctual SrZrO3 presence at both cathode/barrier and barrier/electrolyte interfaces for the cell with as-deposited barrier layers. The cell with screenprinted barrier layer (0.5 Acm-2) also presents higher ohmic resistance than the cell with annealed PLD barrier, but both cells possess a similar polarization resistances. In this case, the difference in ohmic resistance can be related with several factors like porosity, the presence of SrZrO3 and the loss of Gd dopant close to the electrolyte/barrier interface (Fig. S3c).17,23 Finally, the stability of the PLD barrier layers is studied by long-term tests, in which a constant current density of 0.5 Acm-2 is applied and the voltage evolution is monitored at 750ºC under humidified hydrogen and synthetic air (Fig. S4a). In order to discard possible degradation from other cell components (i.e. cathode, anode or seal elements), impedance spectra have been periodically acquired during the experiment. Ohmic resistances are obtained from these measurements by fitting of the equivalent circuit: LR1(R2Q1)(R3Q2) (Figures 6 and S4b), which are assigned as R1 and can be associated to the sum of the contributions of the electrolyte, barrier layer and contact resistances. These tests demonstrate an important reduction in the ohmic resistance for the sample submitted to the stabilization process of barrier at 1150ºC (with a similar electrolyte and the same set-up). They also confirm a beneficial effect in terms of long-term stability (Figure S4b). In order to assess the behaviour of samples with the improved barrier layer in realistic operation conditions, the fabrication procedure has been scaled to large area cells. Results are shown in the following section. (b)

3,0

1,2

Voltage (V)

1,0

Temperature = 750ºC H2 = 16 mlmin-1cm-2 -1

1,4

-2

Air = 40 mlmin cm

0,8

1,2 1,0 0,8

0,6

0,6

0,4 0,2

1,6

Annealed PLD As-deposited PLD Screen-printed

0,4 0,2

0,0 0,0 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 -2

Current density (Acm )


2,0 1,5 1

1,0

0.1 1

1

0,5

0.1

0.1

103 3 0,0 103 10

0,0

(c)

0,5

1,0

1,5

2,0

2,5

3,0

Z'' (Ωcm2) 0,4 0,3

Z'' (Ωcm2)

(a)

Z'' (Ωcm2)

2,5

Power density (Wcm-2)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60



0,2 0,1 103

0,0 0,0

1 0.1 103

0,1

103

0,2

1 0.1 1

0,3

0.1

0,4

Z' (Ωcm2)

Figure 6. (a) j-V curves, and EIS at: (b) OCV, and (c) 0.5 Acm-2, for cells with CGO barrier layers

fabricated by PLD (as-deposited and annealed at 1150°C) and screen printing.



3.6 Scale-up and degradation tests of large-area cells

After electrochemical analyses of button cells with annealed barrier layers, which demonstrate an excellent cell performance and improved stability at long-term, the layer deposition was extended to large-area SOFCs (80 cm2). Figure 7 shows the thickness profile of the deposited layers. A good homogeneity is evidenced since more than 90% of total deposited area is within the thickness range between 1.75 and 1.97 µm. Radial symmetry is intrinsically ensured by the fabrication method, in which the sample is rotating in an axis perpendicular to the surface while depositing.

Figure 7. Profile of the thickness of the annealed PLD CGO barrier layer, corresponding to a large

area cell, determined by ellipsometry technique. Figure 8 shows the voltage evolution with time for this and a reference stack. A significant

improvement of the performance (ca. 4%) is observed for the enhanced barrier layers. This difference in performance is lower than the one observed in button cells (~8%) at a current density of 0.4 Acm-2. It is important to remark that, although imposing the same current density, the measurement in the stack is at 80% fuel utilization, far from the one reached by the button cell. In addition, the different fuel composition (i.e. reformed Natural Gas versus pure hydrogen) can also be behind the different behaviors. It is worth mentioning, however, that an enhancement of 4% in such a mature well optimized technology is an important step ahead. The cost reduction arisen from this improvement could become significangly more important if an development of stack components that now limit the overall performance is achieved in the future. On the other hand, the stack is currently running for ca. 4500 h and it was subjected to 4 thermal cycles, due to maintenance of the testing bench. After an initial voltage drop, which is normally associated to particle coarsening and to the stabilization of the microstructure in the first 500 h, the performaces of the stack were quite stable. The slight increase of performance after restarting the test at ca.


Page 14 of 23

Page 15 of 23

2650 h is related to the introduction of auxiliary heating elements, which improve the thermal insulation of the stack. After this point, the performance of the stack is even more stable and the degradation is calculated in the range 2650-6560 h, corresponding to 2550 h net operation time. The observed degradation of the reference and enhanced cells, in this range of time, is pratically identical (0.35 and 0.34%/1000h, for reference and enhanced cells, respectively). The main cause of degradation in this period is clearly associated to the thermal cycles. It is also worth pointing out that the operating temperature is self-sustained by the exothermic reactions occurring in the stack while the testing bench is not equipped with resistances to maintain a constant temperature.

Accumulated operation time (h) 0,92

0

1000 1950 2170 2980 3730 4200 4750 Current density = 0.4 Acm-2 Temperature = 750ºC Fuel utilization = 80%

0,88

Voltage (V)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Annealed PLD barrier layer

0,84

*

0,80

*

*

*

*

Screen-printed barrier layer (state-of-the-art)

0,76

Improved thermal insulation * Interruption of operation for maintenance

0,72 0

1000 2000 3000 4000 5000 6000 7000

Progress time (h) Figure 8. Comparison of average degradation curves of a stack with a cluster of three cells with

annealed PLD CGO barrier layers and an identical cluster composed by state-of-the-art cells with screen-printed barrier layer. Up to the best knowledge of the authors, this is the first work presenting degradation rates of largearea cells with PLD barrier layers operated in a stack under real conditions. Despite this consideration, for comparison purposes, Table 1 also lists the degradation tests of a button cell with annealed PLD barrier from this present work, and other two cells from previous studies, in which single large-area cells of 25 cm2 and 16 cm2 with CGO barrier layers fabricated by Magnetron Sputtering33 and PLD,40 respectively, were also operated at long-term. Comparatively, this work is unique since keeps the degradation rates in the order of magnitude expected for commercializable products. Therefore, the present work demonstrates the feasibility of the



Page 16 of 23

implementation of thermally stable barrier layers of CGO fabricated by physical vapor deposition techniques for large area SOFCs.

Materials and fabrication conditions

Study

Deposition technique of barrier layer Temperature (°C)

Cathode material Sintering temperature (°C)

Degradation testing conditions

Cathode area (cm2)

Scale

Time (h)

Temperature (°C)

Current density for Resistance Degradation rate degradation degradation rate (%/1000h) tests (mΩ·cm-2/1000h) -2 (A·cm )

Thickness (µm)

[33]

As-deposited MS LSCF 800 1080 0.5

25

Button-cell

1400

700

0.8

63

5.7

[40]

As-deposited PLD 0.6

16

Button-cell

1500

650

0.75

56

3.3

2

Button-cell

1000

750

0.5

54

3.0

80

3 LargeArea cells in a 33cells-Stack

4500

750

0.4

15 (0-1950h) 7 (1950-4500h) 10 (overall)

0.73 (0-1950h) 0.34 (1950-4500h) 0.53 (overall)

80

3 LargeArea cells in a 33cells-Stack

4500

750

0.4

13 (0-1950h) 7 (1950-4500h) 9 (overall)

0.63 (0-1950h) 0.35 (1950-4500h) 0.49 (overall)

LSC

Enhanced Performance of Gadolinia-Doped Ceria Diffusion Barrier

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