pubs.acs.org/NanoLett
Flexible Organic Transistor Memory Devices Soo-Jin Kim and Jang-Sik Lee* School of Advanced Materials Engineering, Kookmin University, Seoul 136-702, Republic of Korea ABSTRACT The flexible nonvolatile organic memory devices were developed on the plastic substrates based on the organic thinfilm transistors embedding self-assembled gold nanoparticles (AuNP). The organic memory devices exhibited good programmable memory characteristics with respect to the program/erase operations, resulting in controllable and reliable threshold voltage shifts. Additionally, the endurance, data retention, and bending cyclic measurements confirmed that the flexible memory devices exhibited good electrical reliability as well as mechanical stability. The memory devices were composed of the solution-processed organic dielectric layers/metallic nanoparticles and the low-temperature processed organic transistors. Therefore, this approach could potentially be applied to advanced flexible/plastic electronic devices as well as integrated organic device circuits. KEYWORDS Flexible memory, organic electronics, metallic nanoparticles, charge trapping
R
efforts.14-16 Thus, the existing organic electronic components (transistors, logic circuits, etc.) can feasibly be integrated with organic transistor-based memory devices for system-on-chip applications.17 Therefore, organic transistorbased nanofloating gate memory devices are one of the best candidates for future system-on-chip flexible/printable electronic devices. Normally, nanocrystals are synthesized at very high temperatures, making their use in organic device applications virtually impossible. However, low temperaturesynthesized controlled metallic nanocrystal arrays can be used in the charge storage layers of nonvolatile memory devices.9,10 In this work, organic nanofloating gate memory devices were developed based on solution-processed dielectric layers and organic pentacene thin-film transistors (TFTs) on flexible substrates. The solution-processed (spin-coated) cross-linked poly(vinylphenol) (PVP) layers acted as the blocking and tunneling dielectric layers. The controlled gold nanoparticles (AuNP) were synthesized and used as the charge trapping elements. In this study, the organic memory devices were fully flexible and easily fabricated through the adsorption of the Au nanoparticles using the solution process. The programming/erasing operations showed that the organic memory devices exhibited good programmable memory characteristics, resulting in a gate-voltage controlled reliable threshold voltage (Vth) shift in the programmed/erased states. The data retention and endurance measurements also confirmed the reliable nonvolatile memory properties. Additionally, the flexibility of the organic memory devices was verified using the bending cyclic tests. Simple solution processes were used to synthesize the charge-trapping elements/dielectric layers, and the pentacene TFTs were formed at low temperatures with flexible substrates. Therefore, these processes could readily be adopted in the fabrication of integrated flexible electronic devices. Figure 1a shows a schematic illustration of the device structure for the bottom gate and top contact organic transistor-based nonvolatile memory devices on the flexible
ecently, a great demand for high-performance nonvolatile memory devices has arisen for use in portable electronic devices. Therefore, active research has been performed to study the fabrication of highperformance nonvolatile memory devices with reliable data storage, low-power consumption, and low-manufacturing cost.1-5 Among the many types of memory devices, floatinggate type flash memory is the most widely used form of memory devices because of its simple device structure, which is typically a single transistor structure.1 In these devices, the charge carriers can be stored in the floatinggate that is composed of highly doped polysilicon. However, the stored charge carriers are very easily lost through the thin tunneling oxides because the conducting nature of the floating gates leads to continuous charge storage.1 Thus, nitride- or nanocrystal-based flash memory devices (nanofloating gate memory devices) with discrete charge storage media have gained a great deal attention these days.6-10 Many studies have focused on controlling the synthesis of the nanocrystal layer in nanofloating gate memory devices because the programmable memory properties are dependent on the geometry and/or species of the nanocrystals.9,10 On the other hand, many studies have examined semiconductor devices that are based on organic materials for flexible/printed electronic device applications. These organic devices can be processed at low temperatures and low costs and, therefore, are regarded as one of the most important types of semiconductor devices for future flexible/stretchable electronic device applications.11-16 Most of these studies have focused on the transistors and the logic circuits in the organic-material-based semiconductor devices, and currently, transistor devices and logic circuits with excellent electrical performance can be fabricated because of these
* To whom correspondence should be addressed. E-mail:
[email protected]. Tel: +82-2-910-4288. Fax: +82-2-910-4320. Received for review: 3/18/2010 Published on Web: 06/25/2010 © 2010 American Chemical Society
2884
DOI: 10.1021/nl1009662 | Nano Lett. 2010, 10, 2884–2890
FIGURE 1. (a) Three-dimensional schematic diagram of the memory device architecture. Patterned Ti/Au on the PES plastic substrate was used as the gate electrode and the cross-linked PVP layers were used as the blocking and tunneling organic dielectric layers. The self-assembled AuNP charge storage layers were formed on the APTES-coated PVP blocking dielectric layer. The pentacene active layer and the gold source/ drain contacts were formed to make the organic transistor-based memory devices. The chemical structures of the organic layers are shown in the figure. (b) Photograph of the fabricated flexible organic memory devices. (The device size is 3 × 3 cm2.)
substrates. The memory devices were fabricated on polyether sulfone (PES) substrates. The blocking and tunneling dielectric layers (cross-linked PVP) were spin-coated with thicknesses of 400 and 10 nm, respectively. Au that was deposited through evaporation was used as the gate and source-drain electrodes. The charge trapping layer was composed of an adhesion layer of 3-aminopropyltriethoxysilane (APTES) and gold nanoparticles (AuNP) that were synthesized using the citrate reduction method.10,17c,d,18 The maximum processing temperature in this study was 180 °C that was used for the PVP cross-linking. Otherwise, all of the processes were carried out under 100 °C. Therefore, the processing temperature could be much further reduced by reducing the annealing temperature of the solution-processed dielectric layers or adopting low-temperature processable organic dielectric layers. The uniform adsorption of the AuNP was confirmed using the scanning-electron microscopy (SEM) image in Figure 1a. The average diameter of the synthesized AuNP was 10.4 ( 3.4 nm, and the density was 1.26 × 1011 cm-2. The uniform adsorption of the AuNP in the whole area of the device sample (sample size of 3 × 3 cm2) was also examined. In Supporting Information Figure © 2010 American Chemical Society
S1, almost no difference was observed between the adsorbed AuNP distribution (average nanoparticle size and density) in the SEM images that were taken from each region of the memory devices. The facile control of the nanoparticle size was an advantage of using the solution-processed colloidal gold nanoparticles. Additionally, the gold nanoparticles that were synthesized using the citrate reduction method had a negative surface charge, which made them well-dispersed without agglomeration because of the repulsive force of each nanoparticle. The proper synthesis of the AuNP was confirmed using an aqueous solution of the dispersed AuNP at a pH of 5.6, and these nanoparticles exhibited a Plasmon absorption peak at around 525 nm.10 Figure 1b shows a photograph of the fabricated flexible organic memory devices. Notably, most of the device areas were almost transparent except for the gate and sourcedrain regions. Thus, these memory devices could also be applied to transparent electronic devices by adopting transparent conducting electrodes. Figure 2 shows the electrical properties of the fabricated organic TFTs. The organic TFTs were fabricated without the AuNP (device structure: PES/Ti/Au/PVP/APTES/PVP/penta2885
DOI: 10.1021/nl1009662 | Nano Lett. 2010, 10, 2884-–2890
Vth of -8.27 ( 0.21 V, a subthreshold swing of ∼1.18 V/decade, and an Ion/Ioff of ∼106. These electrical properties were comparable to the organic transistor devices that have been reported elsewhere (detailed comparison of organic TFT performances can be found in the Supporting Information, Table S1). The uniformity of the electrical properties was examined by randomly selecting 10 transistor devices that were fabricated on the same plastic substrate (substrate size of 3 × 3 cm2) in Supporting Information Figure S3. The Vth and the saturation mobility were slightly fluctuated, but overall, the electrical properties were found to be very uniform. The programmable memory characteristics were investigated using the memory devices with a structure of PES/ Ti/Au/PVP/APTES/AuNP/PVP/pentacene/Au source-drain. Figure 3a shows the output curves of the memory device in its initial state. The device exhibited good linear behavior at a low drain voltage (VD) and a good saturation region at a high VD as well. The memory device also exhibited the typical p-channel TFT output characteristics. The programmable memory behavior of the organic transistor memory devices that were based on the p-type pentacene semiconductors was related to the charging/discharging states of the holes in the metallic nanoparticles during the program/erase operations. In this study, the blocking organic dielectric layer was used to prevent charge transfer from the gate to the metallic nanoparticles or vice versa during the program/ erase operations. The typical program/erase operation is shown in Figure 3b. The transfer curves were obtained by measuring the drain current (ID) with respect to the applied gate voltage (VG) before (initial curve) and after the programming/erasing operations. Memory devices that are based on organic TFT typically have a lower drift velocity because of their lower carrier mobility compared to the existing memory devices on the Si substrates. As a result, Fowler-Nordheim (F-N) tunneling is a favorable way to program/erase the devices rather than the channel-hot electron/hole injection. In this study, F-N tunneling was used for both the programming and erasing operations, and bias pulses of -90 and 90 V were applied to the gate for 1 s. The F-N tunneling was confirmed by the measurement of tunneling current using the metal-insulator-semiconductor capacitor devices (device structure: p-type Si substrate/cross-linked PVP insulator (10 nm)/Au gate). Ten nanometer thick PVP was used as the gate dielectric since the thickness of tunneling dielectric layer used in the memory devices was 10 nm. F-N tunneling can be described using the equation J ) AE2 exp(-B/E) where J is current density, E is the electric field, and A and B are constants related to the effective mass and barrier height.19 The plot of ln(J/E2) versus 1/E is shown in Supporting Information Figure S4. The linear behavior shows that the tunneling current is followed by the F-N tunneling mechanism. The device was scanned with respect to the gate bias at a drain bias of -30 V to determine the programmed/ erased states. A significant shift in the transfer curves was
FIGURE 2. (a) Output curves of the organic transistor devices. The device had the following structure: PES/Ti/Au/PVP/APTES/PVP/pentacene/Au source-drain. (b) Transfer characteristics of the organic transistors. The AuNP that were used for charge storage elements in the memory devices were not included in this structure to confirm the charging effects in the dielectric layers of the transistors.
cene/Au source-drain) to determine the charging effects in the transistor devices. The only difference compared to the memory devices was the absence of the gold nanoparticlecharge trapping layer in the gate dielectric layer. Otherwise, all of the device structures and the processing conditions were the same. Figure 2a shows the typical output characteristics of the p-channel TFT devices with respect to the gate bias. The transfer characteristics of the organic transistor without the AuNP are shown in Figure 2b. In the gate sweep voltage ranges (10 V to -40 V to 10 V), the TFT device exhibited almost no hysteresis in the transfer curves. We further investigated the charging effect by the application of bias pulses to the gate. The applied bias pulses were the same as used for memory device operations. The program/ erase bias pulses were from (50 to (90 V for 1 s. There was a small Vth shift of around 1 V even after the application of (90 V for 1 s as shown in Supporting Information Figure S2. Therefore, almost negligible charging and/or discharging of the charge carriers occurred in the bulk and/or interfaces of the gate dielectric layer (PVP/APTES/PVP). The transistor exhibited a saturation mobility of 0.25 ( 0.01 cm2/V·s, a © 2010 American Chemical Society
2886
DOI: 10.1021/nl1009662 | Nano Lett. 2010, 10, 2884-–2890
respect to the applied program/erase bias pulses. In this study, the memory window was around 10 V with program/ erase bias pulses of (90 V for 1 s (Figure 3b). The Vth was determined from the intercept of the plot of (ID)1/2 versus VG. After applying a negative voltage to the bottom-gate electrode, holes could be injected to the AuNP from the pentacene layer through the thin 10 nm thick cross-linked PVP tunneling layer. The transfer curve shift (negative bias direction in comparison to the initial curve) confirmed that AuNP acted as the charge trapping elements of the holes. After applying a positive voltage to the bottom-gate electrodes, the stored holes in the AuNP were ejected from the nanoparticles layer to the pentacene layer, resulting in a positive Vth shift. We roughly calculated the trapped charge carrier density using the equation Q ) C∆Vth (where C is the capacitance per unit area and ∆Vth is the memory window, defined as Vth (erased) - Vth (programmed));9b,10,17b it was found that around 4-5 charge carriers were trapped in each gold nanoparticle. The programmed/erased states were defined as the states with the holes that were trapped/detrapped after the application of the negative/positive gate biases, respectively. Thus, the programmed/erased states can be verified by measuring the drain currents upon application of reading bias, resulting in off- and on-states. The hysteresis behavior of the transfer curves was also investigated as a function of the static bias sweep (Supporting Information Figure S5). A static gate bias range from (50 to (90 V was applied with increments of (10 V. Not much hysteresis was observed up to (70 V, but after (80 V the typical counterclockwise hysteresis was observed, indicating the hole charging/discharging of the memory devices. The program/erase speeds were measured using separate memory device cells with programmed/ erased states (Figure 3c). Initially, the separate memory devices were programmed and erased at bias pulses of (90 V for 1 s. Then the program/erase operations were carried out with respect to the applied gate bias pulse widths. The initial Vth was -8.3 V for the erased cell and -18 V for the programmed cell. According to the increase in the program/ erase bias pulse widths, the memory devices exhibited larger Vth shifts. The Vth shift increased with increasing program/ erase operation times. Overall, the flexible organic memory devices were relatively well programmed/erased, but typically, longer bias pulses (>100 ms) must be applied in order to obtain larger Vth shifts. Notably, the on-current level of memory devices was around 1 order of magnitude lower than that of the TFT devices without the AuNP. Additionally, the subthreshold swing properties were degraded in the memory devices. The subthreshold swing was related to the oxide and the depletion capacitances as well as the interfacetrap associated capacitance. Charge carriers were trapped in the metallic nanoparticles of the memory devices, and these charge carriers increased the trapped carrier density, resulting in the degradation of the subthreshold swing properties. Additionally, the channel mobility was also degraded by the presence of the trapped charge carriers in
FIGURE 3. Programmable memory characteristics of the organic memory devices. The device was composed of a layered structure of PES/Ti/Au/PVP/(APTES/AuNP)/PVP/Pentacene/Au source-drain. (a) Output curves of the organic memory devices in the initial state. (b) Transfer curves of the organic memory devices according to the programming/ erasing operations. Programming/erasing bias pulses of (90 V were applied to the gate for 1s. The drain current (ID) vs gate voltage (VG) curves were obtained at a drain bias (VD) of -30 V. The VG was swept from 5 to -40 V. The change in the threshold voltage (memory window) was around 10 V. (c) Program/erase speeds of the organic memory devices. Programming/erasing bias pulses of (90 V were applied to the gate at different pulse widths.
observed in the memory devices with the AuNP. The memory window, ∆Vth, was defined as the change in the Vth with © 2010 American Chemical Society
2887
DOI: 10.1021/nl1009662 | Nano Lett. 2010, 10, 2884-–2890
FIGURE 4. (a) Test pulse sequence for the endurance measurements. Program/erase bias pulses of (90 V were repeatedly applied to the bottom-gate electrode for 1s, and then after a certain number of program/erase cycles (P/E cycles) the reading process was carried out to confirm the change in the drain current. A reading bias of -8 V was applied to measure the drain current. (b) Endurance characteristics of the flexible organic memory devices with respect to the number of program/erase operations. (c) Test pulse sequence for the data retention measurements. The separate devices were programmed and erased at (90 V for 1s, and the reading process was carried out with respect to time to verify the change in the drain current. A reading bias of -8 V was applied to measure the drain current. (d) Data retention capability as a function of the retention time for the flexible organic memory devices in the programmed/erased states under ambient conditions at room temperature. The dotted line is an extrapolation of the measured data for the retention capability to determine the long-term reliability of the memory devices.
the AuNP charge trapping layers. Therefore, the presence of the AuNP as well as the trapped charge carriers close to the pentacene surface affected the channel conductance. However, overall, the memory device exhibited good transfer characteristics with a high on-off ratio, low subthreshold swing, and so forth. We calculated the charging energy of our system. The charging energy can be calculated using the equation, q2/2C, where q is the fundamental unit of charge and C is the capacitance of the particle. The capacitance is particle-size dependent and C(r) ) 4πε0εrr, where ε0 is the permittivity of a vacuum, εr is the dielectric constant of the material surrounding the particle, and r is the radius of the nanoparticle.9b,17b,20 In this work, we used cross-linked PVP as dielectric media (εr of ∼4.14) and the radius of the nanoparticles is around 5.2 nm. Thus, the charging energy of our system is calculated to be about 33.4 meV. The charging energy is similar to the thermal energy at room temperature (kBT, where kB is Boltzmann constant and T is absolute temperature.), so almost continuous charging is expected at room temperature without Coulomb blockade effect. Reliable operation is very important in nonvolatile memory devices, and the endurance and data retention © 2010 American Chemical Society
capability are the most important device performance measurement parameters. Figure 4a,b shows the test pulse sequence for endurance measurements along with measured endurance properties. The programming/erasing operations were repeated with the continuous application of bias pulses of (90 V for 1 s to measure the endurance properties. The drain current was measured as a function of the number of program/erase cycles to confirm the on/ off states in Figure 4b. For reliable device operation, the onand off-states should be distinguishable because the programmed/erased states can be verified by reading the current at some reading bias, which lies in between the programmed and erased Vth. In each programming/erasing operation, a reading voltage of -8 V was applied to measure the drain current. Almost no degradation was observed for the drain currents with respect to the number of program/ erase cycles, and the memory devices did not break down until more than 700 cycles (Figure 4b). For practical applications, the number of endurance cycles should be at least 104 in conventional Si-based nonvolatile memory devices. However, a number of endurance cycles over several hundreds were believed to be promising for future applications of organic transistor memory devices for low-cost flexible 2888
DOI: 10.1021/nl1009662 | Nano Lett. 2010, 10, 2884-–2890
through the thin tunneling dielectric layer. Therefore, scaling the tunneling dielectric layer should be accompanied with the blocking dielectric layer scaling. Then, there should be degradation of data retention property, which is as important as the operating voltage reduction. Therefore, detailed and thorough band structure engineering must be done, and the process must be optimized to obtain the best device performances. Additionally, the transparent organic memory devices on the flexible substrates were believed to be based on the device architecture that was presented in this study because most of the device areas were already transparent except for the gate and source/drain electrode regions. Therefore, fully flexible and transparent organic nonvolatile memory devices are viable in the near future by adopting transparent electrodes. In conclusion, the flexible organic TFT-based nonvolatile nanofloating gate memory devices were developed. The solution-processed organic dielectric layers were used as the blocking and tunneling barrier layers, and pentacene was used as the active layer. Large memory windows (∆Vth > 10 V) as well as reliable memory operations were obtained by optimizing the tunneling and blocking barrier layers for the fabrication of flexible memory devices. Data retention properties were expected from the extrapolation of the measured data retention characteristics, which showed that the stored information was reliably maintained for more than a year. This study also confirmed that the organic memory device was very reliable after more than hundreds of repeated programming/erasing operation cycles. Additionally, the mechanical flexibility was confirmed using the bending cyclic test over 1000 times. The nonvolatile memory devices were based on the solution-processed metallic nanoparticles and dielectric layers. Additionally, all of the processes were carried out at low temperatures. Therefore, these methods could potentially be integrated with plastic electronic components/circuits.
FIGURE 5. Mechanical stability test of the flexible organic memory devices that was carried out by repeatedly bending the memory devices with a bending radius of 20 mm. The programmed/erased Vth was measured after a certain number of bending cycles.
memory devices. The data retention properties were measured as a function of time using the memory devices in the programmed/erased states at room temperature. The bias pulses that were used are shown in Figure 4c. The data retention properties were measured as a function of the retention time using the memory devices in the programmed/ erased states (Figure 4d). The programmed/erased states were obtained at an applied bias of (90 V for 1s. A reading voltage of -8 V was applied to measure the drain current. The on-current (Ion) and off-current (Ioff) were well separated with respect to the elapsed time. Notably, both the programmed and erased states degraded with time, but the degradation was not severe compared to other organic memory devices. Overall, the stored data were well maintained, and moreover distinguishable on/off ratio was expected after a retention time of one year from the extrapolation. In addition to the reliable device operation, the bending stability is also one of the most important factors for determining the suitability of this device structure for applications in flexible electronic devices. The bending tests were carried out by repeatedly bending the samples with a radius of curvature of 20 mm. The cyclic bending tests were performed up to 1000 times to confirm the flexibility of the organic memory devices. In the bending tests, the memory devices exhibited almost no change in the programmed/erased Vth even after 1000 cycles (Figure 5). These results confirmed that the fabricated organic memory devices exhibited a good mechanical flexibility as well as good programmable memory properties, and therefore, these devices were suitable for flexible electronic device applications. On the basis of this work, additional studies are currently being conducted to further enhance the programmable memory characteristics. Actually, the current organic memory devices typically require high-operation voltages. The operating voltages could possibly be further reduced by adopting high-k dielectrics for the blocking dielectric layers. However, this memory device was based on the charge carrier transfer from the semiconductor layer to the metallic nanoparticles © 2010 American Chemical Society
Acknowledgment. This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (MEST) (Grants 2008-0059952, 2009-0077593, 2010-0014925, 2010-0015014); by the CMPS/ERC program of NRF/MEST (Grant R11-2005-04800000-0); by the IT R&D program of MKE/KEIT (Grant 10030559); and by the G.R.O.W. project of World Gold Council (Grant RP05-08). Note Added after ASAP Publication. This paper published ASAP June 25, 2010. Minor text corrections were made in the seventh paragraph and reference 13, in addition to improved rendering of Figure S1. The correct version published on June 30, 2010. Supporting Information Available. Experimental details, uniform adsorption of gold nanoparticle-charge trapping elements, charging effects in organic TFTs and memory devices, comparison of electrical properties of 2889
DOI: 10.1021/nl1009662 | Nano Lett. 2010, 10, 2884-–2890
organic TFTs, the uniform electrical properties of the flexible organic TFTs, measurement of tunneling current through the cross-linked PVP tunneling dielectric layer, and the hysteresis behavior of flexible organic memory devices. This material is available free of charge via the Internet at http://pubs.acs.org.
(11) (a) Garnier, F.; Horowitz, G.; Peng, X. H.; Fichou, D. Adv. Mater. 1990, 2 (12), 592–594. (b) Katz, H. E.; Lovinger, A. J.; Johnson, J.; Kloc, C.; Siegrist, T.; Li, W.; Lin, Y. Y.; Dodabalapur, A. Nature 2000, 404 (6777), 478–481. (c) Eder, F.; Klauk, H.; Halik, M.; Zschieschang, U.; Schmid, G.; Dehm, C. Appl. Phys. Lett. 2004, 84 (14), 2673–2675. (d) Forrest, S. R. Nature 2004, 428 (6986), 911–918. (e) Ouyang, J. Y.; Chu, C. W.; Szmanda, C. R.; Ma, L. P.; Yang, Y. Nat. Mater. 2004, 3 (12), 918–922. (f) Someya, T.; Sekitani, T.; Iba, S.; Kato, Y.; Kawaguchi, H.; Sakurai, T. Proc. Natl. Acad. Sci. U.S.A. 2004, 101 (27), 9966–9970. (g) Majewski, L. A.; Schroeder, R.; Grell, M. Adv. Mater. 2005, 17 (2), 192–196. (h) Bozano, L. D.; Kean, B. W.; Beinhoff, M.; Carter, K. R.; Rice, P. M.; Scott, J. C. Adv. Funct. Mater. 2005, 15 (12), 1933–1939. (i) Ling, Q. D.; Song, Y.; Ding, S. J.; Zhu, C. X.; Chan, D. S. H.; Kwong, D. L.; Kang, E. T.; Neoh, K. G. Adv. Mater. 2005, 17 (4), 455–459. (j) Briseno, A. L.; Mannsfeld, S. C. B.; Ling, M. M.; Liu, S. H.; Tseng, R. J.; Reese, C.; Roberts, M. E.; Yang, Y.; Wudl, F.; Bao, Z. N. Nature 2006, 444 (7121), 913–917. (k) Lee, S. W.; Lee, H. J.; Choi, J. H.; Koh, W. G.; Myoung, J. M.; Hur, J. H.; Park, J. J.; Cho, J. H.; Jeong, U. Nano Lett. 2010, 10 (1), 347–351. (12) Lee, W. H.; Kim, D. H.; Jang, Y.; Cho, J. H.; Hwang, M.; Park, Y. D.; Kim, Y. H.; Han, J. I.; Cho, K. Appl. Phys. Lett. 2007, 90 (13), 132106. (13) Park, S. K.; Jackson, T. N.; Anthony, J. E.; Mourey, D. A. Appl. Phys. Lett. 2007, 91 (6), 063514. (14) (a) Sirringhaus, H.; Ando, M. MRS Bull. 2008, 33 (7), 676–682. (b) Sirringhaus, H. Proc. IEEE 2009, 97 (9), 1570–1579. (15) Lodha, A.; Singh, R. IEEE Trans. Semicond. Manuf. 2001, 14 (3), 281–296. (16) (a) Klauk, H.; Halik, M.; Zschieschang, U.; Eder, F.; Schmid, G.; Dehm, C. Appl. Phys. Lett. 2003, 82 (23), 4175–4177. (b) Klauk, H.; Halik, M.; Zschieschang, U.; Eder, F.; Rohde, D.; Schmid, G.; Dehm, C. IEEE Trans. Electron Devices 2005, 52 (4), 618–622. (c) Klauk, H.; Zschieschang, U.; Pflaum, J.; Halik, M. Nature 2007, 445 (7129), 745–748. (d) Sirringhaus, H.; Kawase, T.; Friend, R. H.; Shimoda, T.; Inbasekaran, M.; Wu, W.; Woo, E. P. Science 2000, 290 (5499), 2123–2126. (17) (a) Sekitani, T.; Yokota, T.; Zschieschang, U.; Klauk, H.; Bauer, S.; Takeuchi, K.; Takamiya, M.; Sakurai, T.; Someya, T. Science 2009, 326 (5959), 1516–1519. (b) Baeg, K. J.; Noh, Y. Y.; Sirringhaus, H.; Kim, D. Y. Adv. Funct. Mater. 2010, 20 (2), 224– 230. (c) Kim, S. J.; Park, Y. S.; Lyu, S. H.; Lee, J. S. Appl. Phys. Lett. 2010, 96 (3), 033302. (d) Kim, Y. M.; Park, Y. S.; O’Reilly, A.; Lee, J. S. Electrochem. Solid-State Lett. 2010, 13 (4), H134– H136. (18) Grabar, K. C.; Freeman, R. G.; Hommer, M. B.; Natan, M. J. Anal. Chem. 1995, 67, 735–743. (19) Sze, S. M.; Ng, K. K. Physics of Semiconductor Devices, 3rd ed; John Wiley & Sons: Hoboken, NJ 2007; p 227. (20) (a) Collier, C. P.; Vossmeyer, T.; Heath, J. R. Annu. Rev. Phys. Chem. 1998, 49, 371–404. (b) Likharev, K. K. Proc. IEEE 1999, 87, 606–632. (c) Thomas, P. J.; Kulkami, G. U.; Rao, C. N. R. Chem. Phys. Lett. 2000, 321, 163–168.
REFERENCES AND NOTES (1)
(a) Pavan, P.; Bez, R.; Olivo, P.; Zanoni, E. Proc. IEEE 1997, 85 (8), 1248–1271. (b) Bez, R.; Camerlenghi, E.; Modelli, A.; Visconti, A. Proc. IEEE 2003, 91 (4), 489–502. (c) Lu, C. Y.; Hsieh, K. Y.; Liu, R. Microelectron. Eng. 2009, 86 (3), 283–286. (2) Kozicki, M. N.; Park, M.; Mitkova, M. IEEE Trans. Nanotechnol. 2005, 4 (3), 331–338. (3) Naber, R. C. G.; Tanase, C.; Blom, P. W. M.; Gelinck, G. H.; Marsman, A. W.; Touwslager, F. J.; Setayesh, S.; De Leeuw, D. M. Nat. Mater. 2005, 4 (3), 243–248. (4) Wuttig, M.; Yamada, N. Nat. Mater. 2007, 6 (11), 824–832. (5) Ling, Q. D.; Liaw, D. J.; Zhu, C. X.; Chan, D. S. H.; Kang, E. T.; Neoh, K. G. Prog. Polym. Sci. 2008, 33 (10), 917–978. (6) (a) Yang, Y. L.; White, M. H. Solid-State Electron. 2000, 44 (6), 949–958. (b) Lee, J. S.; Kang, C. S.; Shin, Y. C.; Lee, C. H.; Park, K. T.; Sel, J. S.; Kim, V.; Choe, B. I.; Sim, J. S.; Choi, J.; Kim, K. Jpn. J. Appl. Phys., Part 1 2006, 45 (4B), 3213–3216. (7) (a) De Salvo, B.; Ghibaudo, G.; Pananakakis, G.; Masson, P.; Baron, T.; Buffet, N.; Fernandes, A.; Guillaumot, B. IEEE Trans. Electron Devices 2001, 48 (8), 1789–1799. (b) De Blauwe, J. IEEE Trans. Nanotechnol. 2002, 1 (1), 72–77. (c) Kim, D. W.; Kim, T.; Banerjee, S. K. IEEE Trans. Electron Devices 2003, 50 (9), 1823–1829. (d) De Salvo, B.; Gerardi, C.; van Schaijk, R.; Lombardo, S. A.; Corso, D.; Plantamura, C.; Serafino, S.; Ammendola, G.; van Duuren, M.; Goarin, P.; Mei, W. Y.; van der Jeugd, K.; Baron, T.; Gely, M.; Mur, P.; Deleonibus, S. IEEE Trans. Device Mater. Reliab. 2004, 4 (3), 377–389. (e) Kim, E. K.; Kim, J. H.; Lee, D. U.; Kim, G. H.; Kim, Y. H. Jpn. J. Appl. Phys., Part 1 2006, 45 (9A), 7209–7212. (f) Koliopoulou, S.; Dimitrakis, P.; Goustouridis, D.; Normand, P.; Pearson, C.; Petty, M. C.; Radamson, H.; Tsoukalas, D. Microelectron. Eng. 2006, 83 (4-9), 1563–1566. (g) Yamada, K.; Yoshii, S.; Kumagai, S.; Miura, A.; Uraoka, Y.; Fuyuki, T.; Yamashita, I. Jpn. J. Appl. Phys., Part 1 2006, 45 (11), 8946–8951. (h) Yeom, D.; Kang, J.; Lee, M.; Jang, J.; Yun, J.; Jeong, D. Y.; Yoon, C.; Koo, J.; Kim, S. Nanotechnology 2008, 19 (39), 395204. (i) Hong, A. J.; Liu, C. C.; Wang, Y.; Kim, J.; Xiu, F. X.; Ji, S. X.; Zou, J.; Nealey, P. F.; Wang, K. L. Nano Lett. 2010, 10 (1), 224–229. (8) Liu, Z. C.; Xue, F. L.; Su, Y.; Lvov, Y. M.; Varahramyan, K. IEEE Trans. Nanotechnol. 2006, 5 (4), 379–384. (9) (a) Lee, C.; Kwon, J. H.; Lee, J. S.; Kim, Y. M.; Choi, Y.; Shin, H.; Lee, J.; Sohn, B. H. Appl. Phys. Lett. 2007, 91 (15), 153506. (b) Lee, J. S.; Kim, Y. M.; Kwon, J. H.; Shin, H.; Sohn, B. H.; Lee, J. Adv. Mater. 2009, 21 (2), 178–183. (10) Lee, J. S.; Cho, J.; Lee, C.; Kim, I.; Park, J.; Kim, Y. M.; Shin, H.; Lee, J.; Caruso, F. Nat. Nanotechnol. 2007, 2 (12), 790–795.
© 2010 American Chemical Society
2890
DOI: 10.1021/nl1009662 | Nano Lett. 2010, 10, 2884-–2890
