Fully Solution-Processed Transparent Artificial Neural Network Using

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Functional Inorganic Materials and Devices

Fully solution processed transparent artificial neural network using drop-on-demand electro-hydrodynamic printing Jason Yong, You Liang, Yang Yu, Basem Hassan, Sharafat Hossain, Kumaravelu Ganesan, Ranjith Rajasekharan Unnithan, Robin Evans, Gary Egan, Gursharan Chana, Babak Nasr, and Efstratios Skafidas ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.9b02465 • Publication Date (Web): 22 Apr 2019 Downloaded from http://pubs.acs.org on April 22, 2019

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ACS Applied Materials & Interfaces

Fully solution processed transparent artificial neural network using drop-on-demand electro-hydrodynamic printing Jason Yong*†,§,⊥,††, You Liang†,§,⊥, Yang Yu†,§,⊥, Basem Hassan†,§,⊥, Md Sharafat Hossain§,††,‡‡, Kumaravelu Ganesan∥, Ranjith Rajasekharan Unnithan§, Robin Evans§, Gary Egan⊥,‡, Gursharan Chana†,#,@,¶, Babak Nasr†,§,⊥, Efstratios Skafidas*†,§,⊥,††

† Centre

for Neural Engineering, The University of Melbourne, Carlton, VIC 3053, Australia.

§

Department of Electrical and Electronic Engineering, University of Melbourne, VIC 3010, Australia. ∥

School of Physics, University of Melbourne, Melbourne, VIC 3010, Australia.

Australian Research Council Centre of Excellence for Integrative Brain Function, The University of Melbourne, Victoria, 3010, Australia. ⊥

‡

Monash Biomedical Imaging, Monash University, Clayton, VIC, Australia.

# Department

of Medicine (RMH), The University of Melbourne, VIC, 3010, Australia.

@ Department ¶

of Psychiatry, The University of Melbourne, VIC, 3010, Australia.

Florey Institute of Neuroscience and Mental Health, Parkville, VIC 3010.

†† Advanced

Micro Devices (AMD), 32, Lincoln Square North, Victoria 3053, Australia.

‡‡

ARC Research Hub for Graphene Enabled Industry Transformation, The University of Melbourne, Parkville, Australia

Keywords: electrohydrodynamic printing, synaptic plasticity, synaptic transistors, neuromorphic device, sol-gel In2O3, sol-gel ITO, thin film transistor

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Abstract Artificial neural networks (ANN), deep learning and neuromorphic systems are exciting new processing architectures being used to implement a wide variety of intelligent and adaptive systems. To date, these architectures have been primarily realised using traditional CMOS processes or otherwise conventional semiconductor fabrication processes. Thus, the high cost associated with the design and fabrication of these circuits has limited the broader scientific community from applying new ideas, and arguably, has slowed research progress in this exciting new area. Solution processed electronics offer an attractive option for providing low-cost rapid prototyping of neuromorphic devices. This paper proposes a novel, wholly solution-based process used to produce low cost transparent synaptic transistors capable of emulating biological synaptic functioning and thus used to construct ANN. We have demonstrated the fabrication process by constructing an ANN that encodes and decodes a 100×100-pixel image. Here the synaptic weights were configured to achieve the desired image processing functions.


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Introduction Stochastic based neural networks are an exciting new computing paradigm being applied to image recognition, pattern classification and optimisation problems. In contrast to the conventional Von Neumann computing architectures, these artificial neural networks (ANN), deep learning architectures and neuromorphic computing rely on massive parallel networks for both computing and memory storage based on altering the synaptic strength connecting compute elements within the neural network. These complex ensembles of interconnected networks of neurons have the desirable benefits of being: adaptive; robust to single node failure; have the ability to learn based on previously observed inputs. Critically, they have higher energy efficiency when compared to traditionally Von Neumann architectures.1 Though the idea of building a neuron-like solid-state device has been conceptualised since the 1990s, synaptic transistors have been primarily fabricated using physical and chemical vapour deposition (PVD / CVD) techniques, or by means of CMOS based processes. Shibata et. al. proposed a neuron MOSFET or neuMOS device with multiple input gates that were capacitively coupled with an additional floating gate to emulate the integration of multiple pre-synaptic inputs.2 Notwithstanding some significant advantages over their contemporary counterparts, large neural network implementations on CMOS technologies are not without their limitations. Advanced implementations of large-scale networks comprise of 30,000 custom high-performance CMOS compute processors but only emulate a fraction of the brain in non-real-time at an energy budget of 1W per chip. In contrast, the typical human brain consumes approximately 20 W.3,4 New devices and modelling approaches are required that are both cheaper and more power efficient. The realisation of neuromorphic circuits using two terminal devices such as memristors and photonic PCM (phase change material) devices, which imitates neural function via the formation of conductive filaments or alteration of optical properties, are well known.5–7 Three terminal transistors devices emulates biological synapses via the modulation of the channel conductance are an alternative approach. Electrolytic-gated thin film transistors are recipients of significant attention due to their potential in low-cost electronics and neuromorphic computing.8 In recent years, a broad spectrum of electrolyte-gated transistors scheme has been proposed such as sodium alginate gated IZO transistors, graphene oxide based IZO transistors and methyl celullose gated IZO transistors.9– 11 More recently, Zhu et. al. proposed an in-plane synaptic transistor by lateral coupling of the indium zinc oxide (IZO) layer sputtered on a phosphorus-doped nano-granular SiO2 proton conductive film.12 These biologically inspired artificial synapses are capable of performing basic neuromorphic functions ranging from short-term plasticity, long-term plasticity, pulse-pair facilitation and spike-timing-dependent plasticity.13–15 Unfortunately, these devices are difficult to build and require the usage of vacuum-based physical deposition techniques, specifically, magnetron sputtering, atomic layer deposition and e-beam evaporation. These methods, whilst having advanced the field, are expensive, with modifications to architectures and network layouts requiring many months between design modifications and availability of the ANN for testing. Furthermore, these fabrication approaches are available to a select few, and therefore restrict accessibility by the scientific community to be able to quickly execute and test new architectures and systems. Printing techniques offer a great potential as an exciting candidate for ANN fabrication for its compatibility with various large area substrate and its prospective towards low cost rapid prototyping capabilities.16 The advent of these techniques for fabricating semiconductor technologies can complement conventional fabrication methods in the research and development of new circuit architectures in which costly design iteration is expected. Unlike conventional methods, printing techniques does not require lithographical mask which can be expensive.17 Table 1 summarises the deposition resolution of various non-contact printing techniques. Non-contact ACS Paragon Plus Environment


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printing techniques have a unique advantage over other deposition technique as it does not require physical mask for patterning. Conventional printing techniques, such as inkjet and aerosol jetting techniques do not provide adequate patterning resolution.18 Electrohydrodynamic (EHD) deposition methods could potentially alleviate these issues due to the simplicity of the technology and with the benefit of significantly higher deposition resolution. Over the past several years, tremendous progress in printing technologies has been made through various schemes. Rim et. al. demonstrated the method for producing solution processed all oxide transistor circuit in conjunction with a deep ultraviolet processing for achieving large fabrication throughput.19 Unlike conventional technologies, they are fully additive fabrication processes, able to undertake large area batch electronic fabrication with the added benefit of significant flexibility in the choice of substrate.16,20,21 Furthermore, three-dimensional device architecture can be easily envisaged through vertically integrated solution process based field effect transistors (FETs) which promises higher circuit density without the need for enhancement of the patterning resolution.22,23 In this present study, we explore and develop a new solution process methodology for low-cost and effective rapid prototyping of neural networks that is equally applicable to general electronic circuit fabrication. The proposed process is well suited to ANN applications where the transistor switching speed and the reliability of fabrication of any single transistor in a network are not a critical issue. To the best of our knowledge, this is the first report of fully solution processed, transparent, synaptic transistors in an artificial neural network. Here, we discuss the fabrication of a synaptic transistor and networks based on a co-planar sodium alginate gated indium oxide channel. Furthermore, by exploiting the hydrogenation and hydroxylation of the indium oxide channel, we were able to realise synaptic dynamics, such as spike-timing-dependent plasticity, paired-pulse facilitation, and dynamic filtering, using a single transistor. Moreover, we have successfully fabricated an artificial neural network which emulated synaptic functions for encoding and decoding of visual information. By tuning the device dimensions of the fabricated synaptic transistor, we were able to modulate the synaptic efficacy, thus realising different image processing capabilities. Due to the transparent characteristics of our fabricated devices, they have potential application in display technologies found in virtual reality (VR) and augmented reality (AR) systems in which highly efficient, portable, image processing modules can be integrated onto the viewing lenses thus maximising available substrate real estate.

Results and Discussion Fully solution processed electrolytic gated transistors. Figure 1a-d illustrates the temporal fabrication sequence of the co-planar transistors. Initially, the ITO precursors were spin-coated on a glass slide and subsequently thermally annealed to form the transparent conductive oxide layer. This ITO layer was wet-etched using techniques discussed by Su Shui Hsiang et. al. in conjunction with a direct laser lithographical method which defines the source, the drain and gate electrodes of the transistor.24 For this study, we utilised an EHD deposition technique, to pattern the In2O3 semiconducting channel. Our in-house EHD printer is illustrated schematically in Figure S1 with further details of the physical apparatus available in the methods section. The EHD deposition technique involves the application of electrostatic forces between the print-head and the substrate/counter electrode. When a sufficiently high electrostatic force is applied, the tangential stress deforms the liquid meniscus, on the print-head, into a Taylor cone.21 The ejection of droplets of the liquid precursor droplets from the cone apex occurs when the applied stress overcomes the surface tension of the droplet.25 This electric field based deposition method allows for high resolution patterning in comparison to other conventional direct printing technologies.25 In general, this process can be described as a four-component cycle; (1) the liquid accumulation phase, (2) Taylor cone formation, (3) droplet deposition and (4) liquid relaxation phase.26,27 Figure S2a, b ACS Paragon Plus Environment

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illustrate the droplet deposition and meniscus relaxation phase. We observed that pulsation and oscillatory motion of the Taylor cone negatively impacts both the resolution and the repeatability of the printing process. Uncontrollable ejection of droplets has been reported earlier by J.U. Park et. al.21 Excessive charging of the liquid droplets or the substrate, a phenomenon inherent to EHD systems, can result in erratic behaviour throughout the deposition process which reduces the resolution and quality of the deposited pattern.21,28 To address this shortcoming, our EHD printhead utilises a high voltage push-pull amplifier architecture in which the initiation and termination of the applied voltage can be precisely tuned to negate the aforementioned oscillatory motion as well as providing the drop-on-demand (DOD) capabilities. We have demonstrated 300 nm patterning resolution as shown by Helium ion microscope (HIM) images in Figure S3. Following the deposition of the ITO electrodes, a glass pipette mounted within the print-head was filled with the In2O3 precursor. With the aid of an integrated microscope, the print-head was aligned over the channel as shown in Figure 1e. As the electric field was applied between the nozzle and the aluminium counter electrode, the In2O3 precursor was ejected from the print-head at a controlled temperature of 28○C. The deposited precursor was then thermal annealed at 350○C to form the semiconductor channel. The EHD deposition conditions and configurations are discussed in the Methods section. Finally, the sodium alginate (Na Alg.) electrolyte solution was deposited onto the channel using a pipette and air dried for 30 minutes at room temperature to form the electrolyte gated field effect transistor (EGFET) as seen in Figure 1f. Figure S4a, b, c illustrate the fabricated transistors with various combinations of channel width and length, namely: 420 μm / 115 μm, 200 μm / 90 μm and 100 μm / 90 μm. The detailed fabrication process with the preparation of the precursors is also described in the method sections. EGFET Characteristics. Figure 2a show the transfer characteristics (ID-VG) of the electrolytic gated transistor (EGFET). We observed a hysteresis loop when a cyclic gate voltage was swept from -0.4V to 1V and vice versa. This hysteresis is likely caused by the surface hydrogenation and hydroxylation of the In2O3 surface.29 The thermodynamically stable hydroxyl bonds on the channel surface require a larger negative gate voltage to initiate the proton desorption.30 This phenomenon manifests as a change in the threshold voltage and can be observed as an anti-clockwise hysteresis loop on the transfer characteristic.31 For this application, the observed hysteresis is a crucial property in realising synaptic functions which will be discussed in later sections. The precursor In2O3 channel with 25nm thickness was modulated by a co-planar gate and exhibited the desirable n-type characteristics with an on/off ratio (Ion / Ioff) of 103 with a gate leakage of less than 5 nA. The mean effective mobility and threshold voltage for the fabricated transistors were 0.14 cm2V-1s-1 and -0.39 V respectively. The effective field effect mobility, μFE, is calculated using: ∂ I DS L μ FE = (1) CW V DS ∂ V GS max

[

]

where C is the capacitance, whereas the sub-threshold swing, SS, is calculated as: −1 ∂ log10 I DS SS= ∂ V DS min

[

]

(2)

Figure 2b illustrates the output characteristics of the EGFET which indicate the transistors can be effectively gated at a low voltage of 0.5V and operates as a depletion type device. The transfer and output characteristics of the fabricated transistor with different channel widths and lengths (W/L = 420 μm / 115 μm and 100 μm / 90 μm as seen in Figure 2c, d) are shown in Figure S5. The curves presented in Figure S5 shows the characteristics of a typical field effect transistor with a linear region for VDS < 0.5V and a saturation region for VDS > 0.5V. In the saturation and linear region, all transistors exhibited low leakage current of < 10 nA. In the saturation region for different transistor dimensions, the threshold voltage was determined to be within the ranges of -0.5 V < Vth < -0.1 V in where wider device exhibits more negative threshold voltage as compared to those with narrower channel. The behaviour has been seen in various thin film semiconductor and is attributed ACS Paragon Plus Environment


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to the hole trapping in the back-interface region.32 All the output characteristics curve exhibited an Ion/Ioff ratio of 103. The transparent precursor ITO electrodes were found to have a sheet resistivity of 610 Ω/□. It was also observed that ohmic contact was formed between the probe-electrode and the electrodesemiconductor junctions. Despite the large 100 μm separation between the coplanar gate electrode and the channel, an electric double layer (EDL) can be induced with an application of gate voltage that modulates the channel due to the large accumulation of charge near the In2O3 surface. It has been extensively reported that the EDL thickness, analogous to that of a gate dielectric thickness, is approximately 1 nm.33 The accumulation of charge in the sodium alginate electrolyte can describe by the proton transport mechanism in which protons hop between hydroxyl groups and water molecules, thereby polarising the electrolyte layer and generating large capacitance.34 The FTIR (Fourier transform infrared spectroscopy) spectra of a desiccated sodium alginate film, is shown in Figure 3a, exhibited strong wide spectral bands at 3200-3600 cm-1 range that corresponds to the stretching vibrations of the hydroxyl groups. The operational voltage of these transistors was limited to a maximum of 1V drain voltage and 0.5V gate voltage to prevent excessive electrochemical reaction on the interfaces. Consequently, it was observed that the output current versus drain to source voltage characteristic curves lacked a definitive saturation region. The absence of a redox reaction on the electrode surfaces can be inferred by the measured constant gate leakage current which agrees with previously reported results.35 Figure 3b shows the UV-Visible spectrophotometry measurement which indicate that the fabricated transistors are optically transparent, with an optical transmittance of > 80%, between the wavelengths of 390nm and 1500nm. X-ray photo-electron spectroscopy (XPS) analysis was performed to characterise the chemical composition and chemical states of deposited metal films. Figure 3c, d shows the XPS wide-scan spectra which indicates the conversion of the sol-gel precursor to the appropriate metal oxides compound for the In2O3 and ITO films respectively. The integration of the XPS peaks indicates that the atomic ratio of In:O was 1:1.3 which differs from the composition stoichiometric of In2O3. This deviation suggests a higher number of oxygen vacancies within the semiconductor film. The conductive ITO film has an atomic ratio In:Sn:O of 0.11:1:1.52 which corresponds to the composition of high conductivity sol-gel ITO described previously by M.G. Kim et.al.36 The in-situ tin doping along with the oxygen-deficient defects sites introduce higher carrier density in the ITO film and thus enhanced the electrical conductivity.37 It can be observed from the wide-scan spectra for both sol-gel deposited metal oxides shows carbon (C1s) contamination peaks. These C1s peaks can be attributed to the incomplete decomposition of the organic solvent and ligands.38 Figure S6a and c show the deconvolution of the oxygen (O1s) peaks for In2O3 and ITO respectively. The peak at 530.2 eV (M-O) originates from the oxygen bond of the metal-oxygenmetal bonds whereas the peak at 531.1 eV (Ovac) is associated with the oxygen vacancy in the metal-oxygen networks.36 The peak at 532.4 eV is associated with the hydroxyl species. Strong oxygen lattice bond in conjunction with the weak hydroxyl related bond (M-OH) within the metal oxide film suggests an effective decomposition of the metal oxide precursors.39 Figure S6b, d and e show the Gaussian fitted curve for the deconvolution of the In3d and Sn3d peaks of these metal oxide films. The XPS spectra exhibited the characteristic spin-orbit split 3d5/2 and 3d3/2 signals for both In2O3 and ITO films which suggest the indium and tin valency is primarily +3 in the metal oxide film.40 Comparison studies of In2O3 transistor performance with gating strategy. We evaluated the indium oxide transistor characteristics using different dielectric materials and gating configuration. Figure S7a, b shows the transfer characteristics of the 0.1 μm thick silicon oxide and the 0.12 μm sol-gel based Al2O3 back gated transistors on a p++ silicon wafer respectively. The width and ACS Paragon Plus Environment

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length of these transistors are designed to be 500 μm and 100 μm respectively. The thickness of the sol-gel alumina layer and the sol-gel indium oxide layer were approximately 120nm and 18nm in thickness respectively as determined by optical profilometry (see Figure S8 and S9). Figure S7c shows the capacitance-frequency curve for fabricated transistors with different dielectric materials. The measured capacitance was approximately 11-8 μFcm-2, 1-0.3 μFcm-2 and 0.05-0.004 μFcm-2 up to 10 kHz for the sodium alginate electrolyte, sol-gel alumina dielectric and silicon oxide dielectric respectively. Due to the higher capacitance of the electrolytic dielectric, the fabricated EGFET can perform at low operational voltage (< 1 V) which is crucial for low power and portable applications. Figure S10a, b and c present the distribution of effective mobility, sub-threshold swing and threshold voltage of the transistors with different gating material. For the sol gel alumina gated transistor, the effective mobility was estimated as 28.3 cm2V-1s-1 with an average threshold voltage of -1.05 V and a sub-threshold swing of 0.10 V/decade whereas in the case of silicon oxide gated transistor, the effective mobility was calculated to be 1.50 cm2V-1s-1 with a threshold voltage of 1.77 V and a sub-threshold swing of 1.23 V/decade. As for the sodium alginate electrolytic transistor, the effective mobility was 0.14 cm2V-1s-1 with an average threshold voltage of -0.39 V and a sub-threshold swing of 0.87 V/decade. We also observed that the fabricated transistors gated with an oxide-based dielectric exhibited negligible hysteresis behaviour which further emphasises the surface hydrogenation and hydroxylation at In2O3-electrolyte interface is due to the proton conduction within the electrolyte plays a key role in introducing hysteresis that is needed in this application. Emulation of synaptic functions on electrolytic gated transistors. The proton conductor and trapping mechanism within the sodium alginate electrolytic transistor, described in the previous section, offers short-term synaptic plasticity capabilities which can be used for information processing and synaptic based computations.12 Figure 4a, b shows the Poisson distributed input spike train and their corresponding excitatory post-synaptic current (EPSC) triggered for a transistor with a width and length of 400 μm and 100 μm respectively. The Poisson distribution methodology provides a reliable and deterministic technique for generating spike trains and has been demonstrated by various in-vitro studies.41 This form of input stimulus was chosen as a primary means of stimulating the transistor as it closely mimics its biological counterpart. Figure 4c illustrates a simplified biological model of the pre-synaptic and postsynaptic terminal. As an action potential reaches the pre-synaptic terminals, ionic binding on the presynaptic membrane trigger the release of synaptic vesicles containing neurotransmitters into the synaptic cleft. These neurotransmitters diffuse across the synaptic cleft and attach themselves onto binding sites on the post-synaptic terminal which initiates the opening of ion channels. The opening of these ion channels results in the production of excitatory or inhibitory postsynaptic currents. Here, the movement of sodium ions into the postsynaptic terminals leads to the production of an EPSC.13 In comparison to the biological analog, the EPSC were triggered as mobile protons migrated within the sodium alginate electrolyte towards the In2O3 channel. Here, the co-planar gate is analogous to the pre-synaptic input and the In2O3 channel is analogous to the postsynaptic terminal. As an electric field is applied through the co-planar gate, the mobile protons/ions in the electrolyte form an EDL on the surface of the semiconducting channel.33,42 The accumulation of electrons in the oxide induces the formation of a conductive channel which leads to the production of the EPSC. Upon removal of the stimulus, these mobile protons/ions return to their equilibrium state due to the concentration gradient and subsequently induce a charge/current decay in the ESPC.10 Figure 4b shows an EPSC output of the fabricated synaptic transistor (W = 420 μm, L = 115 μm) for a Poisson distribution input spike train of λ-1 = 10 ms for approximate 3.5 s. The EPSC reaches a peak current of 0.24 μA and eventually decays to the noise floor of the measurement apparatus. This depression and refractory-like output characteristics have been observed in real-world biological system as previously described in the literature.43,44 Figure S11 shows the EPSC response for varying transistor dimensions triggered with a similar Poisson distributed spike train. These EPSC ACS Paragon Plus Environment


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reaches a peak current of 0.082 μA and 0.049 μA before eventually decaying to the noise floor for the synaptic transistors of W/L = 100 μm/90 μm and W/L = 200 μm/90 μm respectively. The transfer of information in a synaptic neuron network is highly dependent on the dynamic changes in the synaptic weight between neurons and can occur on a timescale from milliseconds to a few seconds.45 This phenomenon has been identified as short-term synaptic plasticity and is known to play a critical role in cognitive functions.46 To demonstrate these short-term plasticity behaviours, a pair of consecutive input spikes of 1 V (20 ms pulse width) with inter-spike duration, Δt, ranging from 0.25 ms to 500 ms, were applied to the gate electrode. The EPSC response with a Vds of 0.5 V on the synaptic transistor was measured as illustrated in Figure 5a. The paired-pulse facilitation (PPF) is a means of quantifying plasticity mechanism on a neuron and is exclusively a pre-synaptic phenomenon.47 The PPF manifest when a pre-synaptic neuron is subjected to two stimulus spikes consecutively which results in larger postsynaptic responses for the second stimulus spike than the initial spike.48 Thus, the PPF ratio is defined as the ratio of the amplitude for the second EPSC to the first EPSC (β2 / β1). Figure 5b shows the PPF ratio for the synaptic transistor with a different combination of channel width and length as a function of the spike interval. The maximum PPF ratio was 1.9, 1.85 and 1.78 for W/L of 4, 2 and 1 respectively at Δt = 0.25 ms. The PPF behaviour in an EGFET has been described in the literature as the accumulation of protons at the interface of the semiconductor channel coupled with slow equilibrium dynamics of ions.12,14 Here, the initial pre-synaptic spike induces the accumulation of protons at the sodium alginate – indium oxide interface during the formation of the EDL. In the absence of pre-synaptic stimulus, the EDL gradually diminishes as ions are redistributed into their equilibrium states. Upon the application of a secondary stimulus, in rapid succession, a stronger EPSC response is triggered as the pre-existing EDL remains in effect due to the slow ion dynamics. Thus, a shorter inter-spike interval produces a higher facilitation ratio resembling to those observed in a biological system.45 The fabricated synaptic transistors were also shown to be capable of the dynamic filtering of spiking information based on the stimulus frequency. In Figure 5c and d, the EPSC response and gain was measured for an input spike train consisting of 20 stimulus spikes (1 V, 20 ms) of varying frequency with a constant VDS of 0.5V applied across the source and drain electrodes. Figure 5c shows clearly that the peak response of the EPSC increases with the applied frequency which suggests the behaviour of a high pass filter. Figure 5d illustrates the EPSC gain in relation to the applied frequency which was defined as the amplitude ratio of the initial and last post-synaptic response of the transistor. These frequency-dependent synaptic responses are considered a fundamental mechanism in various neural computation such as sound localisation.49 Synaptic network for image processing. The integration of the post-synaptic response of neurons was is one of the basic functions of neuronal computation in a neural network.50 To demonstrate the potential of these synaptic transistors, we have fabricated a single layer synaptic neural network as illustrated in Figure 6a. The synaptic network was composed of three pre-synaptic inputs and a single postsynaptic output. These individual pre-synaptic transistors were subjected to a spatiotemporally correlated pre-synaptic stimulus which was integrated by a post-synaptic transistor to generate the specific pattern of synaptic output. An external comparator and sampler were used in conjunction to the fabricated neural network post-synaptic output as a buffered firing circuit and digital interface. As the integrated EPSC signal exceeds a predefined threshold value, a spike was triggered based on the integrate-and-fire mechanism. The post-synaptic summing synaptic transistor was biased with a VDS of 0.5 V and the source of the transistor was connected to a transconductance amplifier followed by the firing circuit. To demonstrate the image processing capabilities, we chose an image of a ladybug defined in a pixel grid of 100×100 pixels as shown in Figure 6b. The presynaptic input test sequence was based on a Poisson distributed spike train corresponding to the RGB values of the image as determined by Eq. 3:


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n

P( n)=

(α λ )

n!

e− α λ

(3)

where P(n) is probability of a spike, λ is the firing rate, n is the stimulus window length and α is the normalised RGB colour value. The test sequence for the synaptic network was generated with a stimulus window length of 8192 samples and a maximum firing rate of 100 Hz. For simplicity, the encoding of the input stimulus was split into three input channels, namely the red, green and blue colour as depicted in Figure 6a and the stimulus event were mutually exclusive (no simultaneous inputs within the same time frame). The pre-synaptic test sequence of a pixel colour was encoded in the form of a latency temporal coding scheme or “time-of-arrival” code. More sophisticated versions of this coding scheme have been observed in biological systems such as echolocation, auditory localisation as well as visual system.51 The post-synaptic response of the ANN was decoded based on the spike density within the latency window and was then correlated with the strength of the pixel colour. The decoded RGB values is described by Eq. 4:

RGB( i )=

1

Tw

Ti + 1

∑ E (t ) ,

where i ∈ {1,2,3}

Ti

(4)

where RGB is the normalised colour strength, TW is the window length, E(t) is the post-synaptic response as a function of time, Ti is the latency window and i specifies the latency window of a specific colour. To show an influence of the synaptic strength and their influence on the colour filtering operations, we fabricated two sets of ANNs in which one of the network had two presynaptic transistors of reduced width, namely the green and blue pre-synaptic input transistors. (see Figure S12a, b). Both sets of ANNs had the summing post-synaptic transistor of the same device dimensions. Figure 6c and d show the reconstructed images for the fabricated synaptic neural network. Here, we have demonstrated the capabilities of altering the coefficient of the filtering operation by means of changing the weight of the synaptic transistor or the dimensions of the channel.

Conclusions In this work, we have successfully developed a protocol for fabricating a fully solution process transparent synaptic transistor. This method offers a simplified way of fabricating low-cost, large area ANNs as well as general purpose microelectronics. In addition, we have experimentally demonstrated that the sodium alginate gated In2O3 gated transistor can form the basic building block for realising an ANN. The presented EGFET intrinsically possesses short-term synaptic plasticity capabilities which can be exploited to imitate synaptic functions such as the paired pulse facilitation, dynamic filtering and EPSC integration. The emulation of these synaptic functions is due to the hydrogenation and hydroxylation of In2O3 surface which introduces profound hysteresis properties in the fabricated transistors. By altering the dimension of the EGFET, we have shown that synaptic strength of these transistors can be tuned to suit the application at hand. Importantly, the ANN, fabricated using these transistors, has been shown to be capable of performing image processing operations. Here, we have shown the capabilities to fabricate ANN with multiple pre-synaptic inputs via solution processes methodologies. At present, the device dimensions of the proof of concept synaptic transistor are large, in the order of a 100 μm, however EHD deposition methods are capable of nanometre pattern resolution. EHD printing is superior compared to conventional ink-jet printing due to the higher achievable resolution by means of printhead nozzle size reduction. Sub-micron patterning using EHD printing system still represents an interesting research area in terms of improving the reproducibility and development of a live visualisation system. Besides that, the usage of solution process metal oxide (non-silicon based) transistor creates a pathway for fabricating flexible 3D circuit architectures for higher density electronics and to mimic more closely the 3D architecture of the brain. This will allow the development of more sophisticated neural network in the future with much greater complexity with ACS Paragon Plus Environment


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regard to their neural computations. Finally, the availability of low-cost, solution process rapid prototyping tools for the fabrication of ANNs will greatly enhance research in the field of artificial intelligence by increasing their accessibility to a broader research community namely; the neuroscience and the artificial intelligence research communities.

Experimental Section EHD printer configuration. The EHD printer setup is shown in Figure S1 which consists of a Newport XY100 linear x-y stage and two Scientifica micro-manipulators. The micro-manipulators were used as the print-head work distance controller and the camera aligner. The print-head composed of a glass pipette, tip diameter of 5μm, connected via a platinum wire to a custom-built high voltage pulse width modulator. The counter substrate was constructed out of aluminium with an electronic heat pad adhered onto the bottom. Glass pipettes were drawn using a Stutter P-97 pipette puller from glass capillaries of outer diameter, 1.0 mm and inner diameter 0.58mm. The outer layer of these pipettes was coated with a 50 nm thick Cr layer using a Thermionics VE180 electron-beam evaporator at a pressure of 10-7 Torr. Prior to the deposition process, the glass pipettes were loaded with the metal oxide precursors and mounted onto the print-head. Metal oxide precursor solution synthesis. Each of the 0.1 M indium oxide and aluminium oxide precursor solutions were prepared by dissolving 0.03 g In(NO3)3·xH2O and Al(NO3)3·9H2O in 1 ml of 2-methoxyethanol respectively. The 0.1 M indium tin oxide precursor solution, with an In:Sn ratio of 9:1, was prepared by dissolving 0.03g In(NO3)3·xH2O with 0.002g SnCl2·2H2O in 1 ml of 2-methoxyethanol. Lastly, 10μl of acetylacetone and 7μl of ammonium hydroxide were added to each of the precursor solutions followed by 8 hours of stirring. The 4wt% sodium alginate solution was prepared by dissolving alginic acid sodium salt in de-ionised water followed by mechanical stirring. ITO etchant was obtained by adding 3 wt% Ferric (III) Chloride to deionised water and buffered in a 1:1 volume ratio with a solution of 37% hydrochloric acid for 15 seconds. All reagents used as is for synthesis were purchased from Sigma Aldrich. Fabrication of electrolytic gated thin film transistors. The electrolytic gated transistors were fabricated on a 1 mm-thick Thermo-Scientific microscope glass slide. The prepared ITO solutions were spin coated at 3000 rpm for 60s onto the glass slide followed by thermal annealing at 350 °C in an inert nitrogen environment. The source and drain electrodes were later defined with a SUSS MicroTec SLP300 laser direct write lithography and subsequently wet-etched at 80○C with the buffered FeCl3 etchant. Using our in-house built electro-hydrodynamic printer, the In2O3 semiconducting layer was deposited on the channel. An applied voltage of 600 V at 50 % duty cycle was used between the print head and the substrate with a working distance of 15μm. The stage translation speed in the x-y plane was limited to 100μm s-1. Lastly, the sodium alginate electrolyte solution deposited onto the channel using a glass pipette followed by natural desiccation process at room temperature for 30 min under ambient condition. To characterise the properties of the indium oxide precursor back gated transistors, a thermally grown 100nm silicon oxide on a heavily doped p type silicon wafer as well as a sol gel-based alumina coated silicon wafer was used respectively. The aluminium oxide layer on the silicon wafer was deposited via spin coating of alumina precursor at 3000 rpm followed by thermal annealing at 350 ○C for 1 hr. This process was repeated 5 times to achieve the desired dielectric thickness (see Figure S8). The prepared In2O3 precursors was then spin coated at 3000 rpm and thermally annealed at 350○C for 1 hr. The 50nm Cr source and drain electrodes were deposited using a Thermionics VE180 electron-beam evaporator at a pressure of 10-7 Torr with the aid of a shadow mask. Material Characterisation and Electrical Measurement. The electrical characterisation of the transistors and synaptic circuit were performed using the Agilent E5270B Precision IV Analyser in ACS Paragon Plus Environment

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conjunction with a Cascade Microtech Summit Semi-Automated Probe Station. FTIR measurements were performed using a Thermofisher NicoletTM iSTM50 FTIR spectrometer. UV-Vis spectrophotometric measurements were performed using an Agilent Technologies Cary 300. The morphology of precursor root printed functional materials was investigated via helium-ion beam microscopy (HIM) (Carl Zeiss, Orion Nanofab, Peabody MA, USA), where accumulated charges on glass substrates were suppressed by the electron beam flood gun. HIM images were captured at an accelerating voltage of 30 kV and the ion beam current was approximately 0.2 pA. Optical profilometry measurements were performed using a Bruker ContourGT. X-ray photoelectron spectroscopy (XPS) measurements were carried out on a Kratos Axis Ultra XPS.

ASSOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publications website at DOI: Electrohydrodynamic Printer Setup; Sol-gel precursor morphology and material characteristics; transistor electrical characteristics.

AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] *E-mail: [email protected] Author Contributions All authors have discussed the results and given approval to the final version of the manuscript. Notes The authors declare no competing financial interest

Acknowledgements This work was supported by the Australian Research Council Centre of Excellence for Integrative Brain Function (ARC Centre Grant CE140100007).



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Table 1: Performance characteristics for various non-contact deposition techniques Techniques

Deposition Resolution

References

EHD

200 nm

This work

EHD

1.5μm

Choi et. al., 200852

EHD

80 nm

Galiker et. al., 201225

Aerosol jetting

10 μm

Christenson et. al., 201153

Inkjet

50 μm

Sirringhaus et. al.,200054

Inkjet

200 μm

Ando et. al., 201755



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Figure 1 Schematic representation of the fully solution processed synaptic network using metal salt combustion precursors and the transistor morphology. (a) ITO solutions were initially spin coated on a glass substrate and thermally annealed. (b) The source, drain and gate electrodes for the coplanar transistor structure was defined by direct write laser-lithography and wet-etching. (c) An EHD deposition technique was used to define the n-type In2O3 channel followed by (d) the deposition of sodium alginate electrolyte using a glass pipette to realise the transistor device. (e) Optical image of the deposition process. Scale bar, 100 μm. (f) Optical image showing the array of transistors.


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Figure 2. Electrical measurement of the transfer characteristics of the electrolytic gated transistors. (a) Cyclic ID-VG transfer characteristic curve and (b) ID-VD output characteristic curve of the fabricated transistor (W/L = 4). (c) and (d) Optical profilometry images of the fabricated transistors with a W/L ratio of 4 and 1 respectively. Scale bar, 400 μm.



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Figure 3. Composition and material analysis of the In2O3, ITO and sodium alginate film. (a) This graph presents the UV-vis absorption versus wavenumber of a desiccated sodium alginate film coated on a quartz substrate. (b) Transmittance spectrum of the synaptic network circuit fabricated on a glass substrate indicates the optical clarity of the device. (c), (d) XPS wide-scan analysis spectral of the In2O3 and ITO films.


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Figure 4. Excitatory post-synaptic current. (a) Poisson distributed pre-synaptic spike train (λ-1 = 10 ms). The illustrated graph has been modified for better visual representation of spike train. (b) EPSC response triggered by the applied spike train. (c) Biological synapse and the analogous transistor based artificial synapse.



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Figure 5. Short term plasticity exhibited by fabricated synaptic transistors. (a), i Pre-synaptic spike pairs with a time interval, Δt. (a), ii EPSC response from the pre-synaptic spike pairs. (b) Paired pulse facilitation as a function of the pulse interval, Δt, for synaptic transistors of various device dimensions (width and length of the transistor is denoted by W and L respectively). (c) Measured EPSC triggered by spike trains of different frequency. (d) EPSC gain as a function for the spike trains of different frequency.


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Figure 6. Colour filtering algorithm implemented on an artificial spiking neural network. (a) Schematic diagram of the spike train decoding circuit with various size factor (W/L). The input and summation nodes are represented by the blue and green line respectively. (b), (c) and (d) represents the original, decoded all-colour and decoded red-only 100×100-pixel image respectively. Artwork used in this publication was derived from Wilkinson, ladybug on a leaf, 201956.




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