High-Performance Flexible Single-Crystalline Silicon Nanomembrane

Subscriber access provided by UNIVERSITY OF TOLEDO LIBRARIES

Functional Inorganic Materials and Devices

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High-k Nb2O5Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate Guoxuan Qin, Yibo Zhang, Kuibo Lan, Lingxia Li, Jianguo Ma, and Shihui Yu ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b00470 • Publication Date (Web): 22 Mar 2018 Downloaded from http://pubs.acs.org on March 26, 2018

Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.

is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.

Page 1 of 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Applied Materials & Interfaces

High-Performance Nanomembrane

Flexible Thin-Film

Single-Crystalline Transistors

with

Silicon High-k

Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate Guoxuan Qin†,‡,*, Yibo Zhang†,‡, Kuibo Lan†, Lingxia Li†, Jianguo Ma† and Shihui Yu†,* †

School of Microelectronics, Tianjin University, Tianjin, 300072, P. R. China

‡

Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, Tianjin,

300072, P. R. China

ACS Paragon Plus Environment

ACS Applied Materials & Interfaces 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Abstract A novel method of fabricating the flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high-k Nb2O5-Bi2O3-MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. The SiNMs are successfully transferred to a flexible PET substrate, which has been plated indium-tin-oxide (ITO) conductive layer and high-k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ~109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ~nA leakage current at the applied voltage of 3 V. The transistor is shown to work at high current on/off ratio of above 104 and the threshold voltage is ~1.3 V, with over 200 cm2V-1s-1 effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric has great potential for applications in the high performance integrated flexible circuit.

Keywords: flexible, single-crystalline, BMN, TFT, nanomembrane


Page 2 of 31

Page 3 of 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Introduction Flexible electronics, one of the most emerging and promising microelectronic technologies, have attracted more attention in recent years due to their unique properties such as light weight, bendability and adhesion to irregular shape of surfaces, etc. Promising applications include flexible displays, flexible circuits, skin-like pressure sensors, and conformable RFID tag1-9. Flexible thin-film transistors (TFTs) are an essential and fundamental element for most of the flexible applications. However, the fabrication of high-performance, highly-integrated transistors on flexible substrates has been limited by the high temperature manufacturing technique. Recently, low-temperature fabrication methods and low-cost fabricating process have been reported to achieved high-performance TFT devices on flexible substrates such as inkjet printed materials TFT, Tungsten oxide-based TFT and 2-D materials TFT10-15. However, all these methods still have their limitations for the incompatible process with Si based CMOS technology. Searching a compatible fabrication process for the high performance flexible TFTs is challenging. Semiconductor nanomembranes (NMs) are monocrystalline structures with thicknesses of less than a few hundred nanometers which have finite-size and quantum characteristics in their electronic, mechanical and optical properties16-21. Si nanomembranes (SiNMs) are transferable and can be attached to specific flexible substrate by a compatible technology with traditional CMOS process, which are considered to be the best candidate for manufacturing flexible devices22-24. With this



technique, a variety of flexible microelectronic devices have been realized, examples including flexible thin-film transistors, flexible diodes, flexible photodetectors, etc25-37. As for these flexible SiNM thin-film transistors, only evaporating SiO or CVD SiOx at low temperatures can be used as the gate dielectrics38,39, thus suffering from their low quality and low dielectric constant compared to high-temperature thermal-grown SiO2 gate dielectrics. On the other hand, high dielectric constant dielectrics (high-k), such as ZrO2, HfO2, Ta2O5, and Lu2O3, have been widely investigated to replace SiO2 as gate dielectrics in recent years in TFTs for improving their driving ability and reducing their operating voltage and power consumption. Although these materials can be deposited at an amorphous state by low-temperature atom-layer-deposition (ALD) as low as 50 °C40, there are lots of defects in their amorphous structure which may cause high leakage current. To achieve better crystalline structures, the required ALD deposition temperature is then over 200 °C, which exceeds the maximum temperature that most flexible substrates can sustain. Other materials with higher dielectric constant (>50) such as strontium titanate41, barium strontium titanate42, barium zirconate titanate43 are not suitable to be deposited by ALD because of their complex constituent, while other deposition methods such as magnetron sputtering require over 500 °C deposition temperature to form high-quality dielectric layer. Consequently, we propose here to solve this dilemma by using a new amorphous dielectric material: Nb2O5-Bi2O3-MgO or bismuth magnesium niobium (BMN) ceramics, which is hoped to keep high dielectric constant and low current


Page 4 of 31

Page 5 of 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


density at amorphous state with room temperature deposition by magnetron sputtering. In this paper, flexible single-crystalline SiNM thin-film transistors with high-k BMN ceramics as gate dielectric have been fabricated on plastic substrates. The characteristics of both the BMN gate dielectric layer and BMN-SiNM heterostructure are measured and analyzed, demonstrating small leakage current, smooth heterostructure contact and high gate controlling ability for the flexible transistors. Performance of the flexible transistors with different dimensions and bending conditions are also characterized. The underlying mechanism of the performance variations for the flexible TFTs are discussed by modeling and theoretical analysis. Experimental Section The abridged general view of the fabrication process is shown in Figure 1. Magnetron sputtering was used to deposit ~100 nm ITO on 175 µm PET substrate which the electrical resistivity of the top ITO layer was ~5 Ω/cm. Then Bi1.5MgNb1.5O7 gate layers films were deposited on ITO/PET substrates by Radio Frequency magnetron sputtering from the BMN ceramic target at room temperature. Before sputtering, the vacuum chamber was evacuated down to a base pressure of 9.0 ×10-6 Torr. High purity Ar and O2 were introduced through separate mass flow controllers. The total pressure was maintained at 10 mTorr, and the O2/Ar ratio was 3:17. The depositing power was fixed at 100 W. The BMN gate layers films with different thickness were obtained by changing the deposition time. Then the fabrication started from a silicon-on-insulator (SOI), which contains 200 nm Si



membrane on the top and 450 nm silicon dioxide buried oxide layer between top and bottom Si. First the SOI was cleaned by acetone and isopropanol (IPA) in the ultrasonic wave cleaner for each 5 minutes, after that the source and drain regions were patterned by the lithography process. And then 4×10e15 cm2 dose and 40 Kev injection energy were adopted to carry on the phosphorus (P) ion implantation. Next 850 °C, 45 mins furnace thermal annealing in N2 atmosphere was employed to rebuild the lattice structure of Si. Then a 15 µm×15 µm square hole arrays was patterned where the distance of adjacent holes was 50 µm on SOI. Afterwards this Si holes were etched in reactive ion etching (RIE) system. SOI was then put in hydrofluoric acid (HF, 49% HF: water=1:3) for 45 min to remove the buried oxide layer. The released ~0.7cm × 0.7cm size Si nanomembrane was floated away from the handling substrate in DI water, and then transferred onto the BMN/ITO/PET substrate. The contact between the Si nanomembrane and the BMN gate dielectric layer was measured to be almost ohmic contract. Finally, ~100 nm/30 nm Au/Ti stacks were evaporated to form the electrodes. The frequency-capacitance and frequency-damping factor character was measured by Agilent 4285 and the capacitance-voltage and direct current character was measured by Keithley 4200 SCS Semiconductor analysis meter. Result and Discussion Figure 2a shows the XRD patterns of BMN ceramic gate dielectric layers deposited on ITO coated flexible PET substrate at room temperature. It can be seen that there is a very strong diffraction peak of the PET substrate near 30°, while the other peaks belong to ITO electrode. No more peaks could be detected in all the films


Page 6 of 31

Page 7 of 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


except the peaks from the ITO coated flexible PET substrates, indicating that the BMN gate dielectric layers deposited at room temperature are amorphous. Similar results have been observed for bismuth zinc niobium (BZN) and other oxide thin films prepared at room temperature44. SEM images for 100 nm thick BMN ceramics have been shown in Figure 2b. Smooth surface and no certain morphology are observed from the SEM image in Figure 2b. This result is in good agreement with the analysis of XRD characteristics (all the gate layers are of an amorphous nature). 80 nm and 120 nm thick BMN have been also grown for comparison. Their SEM images have been shown in Figure S1a and b in the supporting information. Figure 2c shows the leakage current–voltage characteristics of BMN gate dielectric layers with different thicknesses. It indicates that the thickness and surface roughness have an apparent effect on leakage current. The 120 nm thick BMN gate dielectric layer exhibits the lowest leakage current of ~31.5 pA/cm2 at an applied voltage of 3 V. The leakage current is related to the thickness of the BMN layer, as well as the surface roughness and the number of defects in films. The dielectric properties of BMN gate dielectric layers with different thickness are presented in Figure 2d. The relative dielectric constant is ~109 at 1 kHz for all the BMN gate dielectric layers and slightly varying with different layer thickness. The relative dielectric constant is ~30 times larger than that of thermally grown SiO2, and thus much higher than those of evaporating or CVD SiOx. Different from the dielectric constant, the dielectric losses decrease with the increase of film thickness. At low frequency, the overall dielectric loss is dedicated by the polarization loss and



Page 8 of 31

leakage conductance loss. The former is strongly affected by space dipole determined by defects in thin films, while the latter results mainly from the imperfect insulator properties of thin films. Figure 2f shows the leakage current of the SiNM-BMN structure (the microscope image of transferred SiNM on flexible substrate has been shown in Figure S2a). The current increases to ~23 nA when the applied voltage increases to 3 V. The leakage current for this heterogeneous structure is much larger than that of BMN gate dielectric layer (~pA, as shown in Figure 2c) for the reason that the carrier drift in the SiNM (slightly doped) when the voltage is applied between the ITO and top metal electrode. Another reason is that the contact area between BMN gate dielectric layer and Si membrane is imperfect and thus causing a larger leakage current. Figure 2g illustrates the frequency-capacitance characteristics of the SiNM-BMN-ITO structure at the frequency from 1 KHz to 1 MHz. The capacitance of the heterogeneous structure is defined as follow: (1) where C is the heterostructure capacitance, Cbulk is the semiconductor capacitance which depends on the depletion width and inversion layer charge of the Si membrane and Cox is the BMN capacitance. The capacitance decreases from ~33.4 pF to ~8.1 pF as the frequency increases. This is because that, at low frequency, mobile electrons accumulate in the inversion layer near the Si/BMN interface, while the heterostructure capacitance is mainly contributed to BMN capacitance Cox, resulting in a high capacitance. Figure 2h shows the capacitance-voltage characteristics at 100 kHz and 1 MHz as a function of voltage. The heterogeneous structure of SiNM transferred on


Page 9 of 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


BMN gate dielectric layer shows a typical p-type MOS characteristics with clear accumulation and inversion regions. The heterogeneous capacitance is mainly depended on Cox at negative voltage. When the applied voltage increases forming the inversion layer at the Si/BMN interface, at high frequency as 1Mhz and 100Khz, the heterogeneous capacitance which is equal to the series capacitors of BMN thin film and depletion capacity in Si membrane tends to be stable. The compatible C-V characteristics indicate that there is a tight connection between the transferred SiNM and BMN gate dielectric layer, forming a stable p-type MOS like structure. From the analysis with Figure 2, the heterostructure exhibits excellent surface and electric characteristics. The photo of the finished flexible SiNM TFTs with BMN gate dielectric on a PET substrate is shown in Figure 3a. The structural schematic of the flexible TFT is shown in Figure 3b. The microscope images of the TFTs with channel width/channel length (W/L) of 30 µm/5 µm and 50 µm/3 µm are shown in Figures 3c and d as examples. Schematic diagram for the flexible TFTs with detailed definitions of W and L is shown in Figure S3. Double channel structure is employed for the TFT. Figure 3e plots the transfer characteristics for the W/L=50 µm/3 µm TFT. The drain current reaches to ~1.6 µA with only ~pA leakage current when VDS is 0.1 V. The 330 mV/dec subthreshold swing can be also observed, which indicates that the TFT can work on a high speed at subthreshold region. The current on/off ratio is ~104 for the flexible TFT. The highest transconductance reaches to ~2.3 µS at gate voltage of ~2.1 V. The effective channel electron mobility is calculated by the following equation



Page 10 of 31

(2)

where Cox is the capacitance of gate dielectric layer and the effective channel electron mobility is over 200 cm2V-1·s-1. Figure 3f shows the I-V characteristics of the flexible TFT, which are consistent with the calculations by the following equation when the device works at saturation region. !

#$

"

when VDS>VGS-VT

(3)

where the VGS is the voltage between the gate and source and VT is the threshold voltage. Figures 3e and f indicate good dc performance for the flexible SiNM TFTs with BMN ceramics gate dielectric. The characteristics for W/L=30µm/5µm device has been shown in Figures S4a and b. The flexible TFTs are also characterized with different active dimensions, as shown in Figure 4. Figures 4a and b show the transfer curve comparisons between the flexible TFTs with different channel width (W of 50 µm and 30 µm is compared, with same L=5 µm). ~1.3 V threshold voltage is observed for both TFTs. When the TFTs work at linear region, Id is expressed as: %

&#

!

#$

'

'

"(

when VDS

High-Performance Flexible Single-Crystalline Silicon Nanomembrane

Recommend Documents