Hysteresis-Free Carbon Nanotube Field-Effect Transistors Rebecca S. Park,*,† Gage Hills,† Joon Sohn,† Subhasish Mitra,†,‡ Max M. Shulaker,§ and H.-S. Philip Wong† †
Department of Electrical Engineering and ‡Department of Computer Science, Stanford University, Stanford, California 94305, United States § Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, United States S Supporting Information *
ABSTRACT: While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to 100 °C),13 and the fabrication methods to implement gate-all-around structures can be challenging for very large-scale integration (VLSI). For instance, processes used to remove metallic CNTs14,15 are difficult to apply when the CNTs are suspended or wrapped in a dielectric. Despite the challenges, these studies have proven that by reducing the density of traps (i.e., making the interfaces as clean as possible), hysteresis in CNFETs is minimized. Additionally, although negligible hysteresis ranging from 2.5% to 5.5% of the gate-source voltage (VGS) sweep range has been reported using VLSI-compatible CNFET structures,16,17 the focus of the reports was not on illustrating a methodology for reducing hysteresis; the mechanism was not well understood, as the authors only briefly explained and attributed reduced hysteresis to fewer charge traps.18,19 Recently, a method of neutralizing the traps by stacking two layers of dielectric (20 nm ALD deposited Al2O3 + 40 nm magnetron sputtered SiO2) has been implemented to reduce hysteresis.20 However, the device behavior needs to be further studied with scaling down the total gate dielectric thickness. Here, we present a facile approach to overcoming hysteresis to 2 nm are metallic). As the bandgap of the CNT is dependent on the CNT diameter (dCNT) as EG ∼
Figure 6. (a) CNT diameter distribution with a mean value of 1.4 nm and standard deviation of 0.34 nm. Inset shows an example of the scanned CNTs using AFM. (b) Simulation comparing the increase in SS due to the measured (total) VT variation and the dCNT-induced VT variation.
σ(VT , dCNT) =
γ0a0 ⎛ 1 ⎞ σ⎜ ⎟ e ⎝ dCNT ⎠
where γ0 = 2.7 (nearest-neighbor overlap integral) and a0 = 1.42 Å (carbon−carbon bond length).33 Using the above equation, the standard deviation of VT due to dCNT variations is 98.9 mV. Monte Carlo simulations are performed to study the effect of CNT diameter variation on SS degradation as the number of CNTs increases in the CNFETs. Figure 6b compares the simulated SS due to the measured (total) VT variations in CNFETs (which is the same simulated curve from Figure 5b) and the simulated SS due to VT variations only from the dCNT distribution. Although dCNT distribution largely contributes to SS degradation, it alone does not account for the experimental SS degradation. Previous studies show that VT variations from diameter distributions become negligible as the channel length is scaled down (since random fluctuation of fixed charges between oxidesin our case, TiO2/SiO2 interfacebecomes the major source of VT variations due to less averaging effects from random variations).33,34 Therefore, nonideal aspects of device processing, such as random fixed charges on the oxide surface, must be further controlled and improved.
CONCLUSION We have successfully demonstrated a VLSI-compatible and solid-state method to fabricate CNFETs with hysteresis
