Improving Performances of In-Plane Transition-Metal Dichalcogenide

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Surfaces, Interfaces, and Applications

Improving Performances of In-Plane Transition-Metal Dichalcogenides Schottky-Barrier Field-Effect Transistors Zhi-Qiang Fan, Xiang-Wei Jiang, Jiezhi Chen, and Jun-Wei Luo ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b04860 • Publication Date (Web): 08 May 2018 Downloaded from http://pubs.acs.org on May 8, 2018

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ACS Applied Materials & Interfaces

Improving Performances of In-Plane Transition-Metal Dichalcogenides Schottky-Barrier Field-Effect Transistors Zhi-Qiang Fan,†,‡ Xiang-Wei Jiang,‡,* Jiezhi Chen,§ and Jun-Wei Luo,‡,* †

School of Physics and Electronic Science, Changsha University of Science and Technology,

Changsha 410114, China ‡

Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

§

School of Information Science and Engineering, Shandong University, Jinan 250100, China

ABSTRACT: Monolayer schottky barrier field effect transistor based on in-plane hetero-junction of 1T/1T’-phase

(metallic)

and

2H-phase

(semiconducting)

transition-metal

dichalcogenide has been proposed following the recent experimental synthesis of such devices. By using density functional theory and ab initio simulations, intrinsic device performance, sub-10nm scaling, and performance boosting of MoSe2, MoTe2, WSe2, and WTe2 Schottky barrier field effect transistors are systematically investigated. We find that the Schottky barrier heights of these in-plane 1T(1T’)/2H contacts are proportional to their band gaps: the bigger band gap corresponds to bigger Schottky barrier height. For four TMDs, the SBH of 1T/2H contact is always smaller than that of 1T’/2H contact. The WTe2 Schottky barrier field effect transistor can provide the best performance, and satisfy the requirement of high performance transistor outlined by international technology road-map for semiconductors down to a 6 nm gate length. In addition, the replacement of suitable 1T-TMD on the S/D regions in source/drain regions can modulate conduction band Schottky barrier leading to 8.8 nm WSe2 Schottky barrier field effect transistor also satisfying the requirement. More over, the introduction of the underlap can increase the effective channel length and reduce the coupling between the source/drain and the channel leading to 5.1 nm WTe2 Schottky barrier field effect transistor also satisfying the International Technology Roadmap for Semiconductors high performance requirement. The underlying physical mechanisms are discussed and it is concluded that the in-plane Schottky barrier engineering is the key point to optimize such two dimensional devices. KEYWORDS: 1

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transition-metal dichalcogenide, interface, Schottky barrier, field-effect transistor, quantum transport INTRODUCTION Driven by the demands in functionality, performance, and cost over the last decades, the channel lengths of transistors decrease gradually and approximate 10 nm. Minimization of Si complementary metal oxide semiconductor integrated circuits size is an main challenge for present electronics.1-3 In order to satisfy the logic technology requirements, many low-dimensional nanomaterials, such as carbon nanotube, graphene, phosphorene, transition-metal dichalcogenides (TMDs) and the so called X-ene family, are considered as the ultimate channel material candidates of the transistors and have attracted much more attention.4-10 Monolayer TMDs are much attractive among these low-dimensional materials due to their outstanding optical and electronic properties. So far, a lot of devices based on monolayer TMDs have been fabricated, such as sensors,11 spintronic devices,12 photoelectronic devices,13 and fully integrated circuits.14 Unlike bulk TMDs with its indirect band gap, monolayer TMDs were found to be a direct band gap semiconductor (1.0-2.0 eV) and thus favorite the logic transistor applications.15-20 However, there are still some challenges for the monolayer TMD FETs. The first one is the quality of the electrical contact between the metal and the monolayer TMD. Usually, a Schottky barrier (SB) will form in semiconductor-metal interface when a monolayer TMD contacts with the metal lead. This SB plays a very important role on the carrier transport of TMD FETs.21-24 Moreover, the unmatchable lattice at the semiconductor-metal interface and the weak coupling of electronic states will also block the efficiency of carrier injection and reduce the on-state current.25 Thus, how to enhance the coupling at the semiconductor-metal interface and how to enlarge the on-state current are very important for TMD FET. Recently, some research groups found several TMDs can transit from their 2H phase to 1T phase with the help of chemical modification.26-29 Then, the in-plane (IP) 1T/2H/1T MoS2 and WSe2 transistors were assembled in experiment.30-32 In addition, few-layer MoTe2 metal-semiconductor polymorphs within the same atomic planes were characterized 2


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using aberration-corrected scanning transmission electron microscopy.33 The experimental measurement results show these IP contacts have the ultralow contact barrier height. These IP 1T/2H inherent contacts are of great importance because of the absence of interface defect at the perfectly aligned junction. Therefore, in this paper, we introduce the monolayer Schottky barrier field effect transistors (SBFETs) by using monolayer TMDs based on the above 1T/2H contacts. Quantum transport simulations are presented to reveal the performance limits of the TMD-SBFETs following the International Technology Roadmap for Semiconductors (ITRS) requirements of sub-10nm devices. The results reveal great potential of such atomically thin body SBFETs for future applications. METHODS

Figure 1. The schematic IP contact of a 1T-MX2/2H-MX2 interface and a 1T’-MX2/2H-MX2. (b) The diagrammatic structure of the double-gated SBFET based on the (1T’)1T-2H-(1T’)1T monolayer MX2.

The concept of the proposed IP (1T’)1T/2H heterostructures of TMD materials MX2 (M=Mo, W; X=Se, Te) is shown in Figure 1(a). For a certain MX2, its 1T’ and 1T phases are metal while its 2H phase is a semiconductor, with the same lattice constants. Figure 1b schematically shows the structure of a double-gated SBFET based on a IP (1T’)1T-2H-(1T’)1T MX2. The source (S) and the drain (D) of the SBFET are the 1T’-phase or 1T-phase MX2 and the channel is the 2H-phase MX2. LG 3



is the channel length of the SBFET and the corresponding Equivalent Oxide Thickness (EOT) and the Power Supply Voltage (VDD) follow the ITRS high performance (HP) requirements. The calculations of Schottky barrier height (SBH) and the simulations of transfer characteristics are carried out by using the software package Atomistix ToolKit.34 The detail parameter setting is following our previous study.35 The current I (Vds ) under the different gate voltage are obtained by the Landauer formula: I (Vds , Vg ) =

2e { T ( E ,Vds ,Vg )[ f S ( E − µ S ) − f D ( E − µ D )]}dE .36 ∫ h

RESULTS AND DISCUSSION Figure 2a shows how the Schottky barrier height (SBH) is directly obtained from the local density-of-states (LDOS) of the heterostructure.21,22 Here, we also extract the SBH by measuring the energy difference between EF of 1T-MX2 and the conduction band minimum (CBM) of the 2H-MX2 in LDOS without bias. The band alignment results of four 2H-TMDs are shown in Figure 2b which agree with the previous experimental and other theoretical results very well.21,22,37-41 One can see the 1T-EF (solid line) and 1T’-EF (dash line) always locate within the 2H band gap. The SBH is proportional to the band-gap: the bigger band-gap corresponds to bigger SBH. For four TMDs, the SBH of 1T/2H contact is always smaller than that of 1T’/2H contact. WTe2-SBFET has the lowest SBH due to its shortest band-gap.

Figure 2. (a) LDOS of 1T-2H-1T WTe2-SBFET under zero bias voltage and zero gate voltage. EF is set to zero. (b) Band alignments of four 2H-TMDs. Energy difference between solid line and CBM shows SBH of each IP 1T/2H contact. Energy differences between dash line and CBM shows SBH of each IP 1T’/2H contact. 4


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Table 1 The device parameters projected in HP ITRS road map.

Figure 3. (a)-(d) Transfer characteristics of MoSe2, MoTe2, WSe2 and WTe2 1T-2H-1T SBFET with physical gate length scaled to 8.8, 7.3, 6.1 and 5.1 nm. (e) and (f) Transfer characteristics of WSe2 and WTe2 1T’-2H-1T’ SBFET with physical gate length scaled to 8.8, 7.3, 6.1 and 5.1 nm. ON currents are shown in inset tables.

Figure 3 depicts the transfer characteristics (Ids-Vg) of IP TMD-SBFETs with physical gate lengths of 8.8nm, 7.3nm, 6.1nm and 5.1nm. VDD and EOT for each LG follow the ITRS HP 2022 to 2028 requirements in Table 1. The ITRS HP IOFF is indicated by dash black lines in the figure. The ITRS HP ION is defined as the current corresponding to the gate voltage of VON=VOFF+VDD (VOFF is the gate voltage of IOFF as 0.1 µA/µm).35 It is well know, subthreshold swing (SS) is a very important factor to determines how effectively the transistor can be turned off by changing the gate voltage. For four SBFETs with 8.8nm physical gate length, the SS can be close to its thermal dynamic limit. However, it will increase with the reduction of physical gate length due to the increased short channel effect, especially the SBFFT with physical 5



gate lengths of 5.1nm. Transfer characteristics of MoSe2, MoTe2, WSe2 and WTe2 1T-2H-1T SBFETs are shown in Figure 3a-d, respectively. One can find the maximum drain currents of MoSe2-SBFET and WSe2-SBFET with four physical gate lengths are all smaller than the ITRS HP requirements due to larger SBH. The maximum drain currents of MoTe2-SBFET and WTe2-SBFET with four physical gate lengths increase because of the reduction of SBH. The numerical values of ION for four TMD-SBFETs with physical gate lengths are presented in inset figures. The WTe2-SBFET has the best performance with ION as high as 1729µA/µm, 1460µA/µm and 1221µA/µm, which is beyond the ITRS HP requirements for 8.8nm, 7.3nm and 6.1nm physical gate lengths. Unfortunately, WTe2-SBFET with 5.1nm physical gate length can’t be used as a HP transistor because of the larger IOFF (0.4µA/µm) than the ITRS requirement. In addition, MoTe2-SBFET with 8.8nm physical gate length also has a good performance. Its ION is 1236µA/µm which approximates ITRS HP requirement. Next, we further investigate the performances of 1T’-2H-1T’ SBFET. Because the SBH of 1T’/2H contact is always larger than that of 1T/2H contact, we just give the transfer characteristics of WSe2 and WTe2 1T’-2H-1T’ SBFETs in Figure 3e and f. One can find the maximum drain currents will increase gradually with the shorting of the channel length due to the short channel effect. Because the leakage currents are always at the same gate voltage, ON currents are also increase gradually in two 1T’-2H-1T’ SBFETs. However, they are smaller than that of corresponding 1T-2H-1T SBFETs due to the higher SBH. Only 1T’-2H-1T’ MoTe2-SBFET with 5.1nm physical gate length approximates ITRS HP requirement. To explain the best performances of 1T-2H-1T WTe2-SBFET, we offer the transmission spectra at different gate voltages and LDOS of 8.8 nm WTe2-SBFET at the ON state (Vg=1.02 V) in Figure 4. In Figure 4a, the energy gap between the Fermi energy of source EF(S) and the Fermi energy of drain EF(D) is 0.72 eV (qVDD). When the gate voltage increases, the transmission spectrum of high energy will move down and get over the EF(S) turning on the transistor. In order to see the electron transport 6


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more clearly, we show the LDOS and current density of WTe2-SBFET (LG=8.8 nm) at ON states in Figure 4b, where the band profiles of the devices are also schematically depicted. Although the triangular SBs can be formed but not thin enough to allow significant electron tunneling, and the thermal injection dominates the carrier transport. At Vg=1.02 V, the CBM of the center 2H channel can shift over the EF of 1T source region. The SB becomes much thinner and let the electrons transfer through it easily, which can be see clearly from the current density in Figure 4b.

Figure 4. (a) Transmission spectra of 8.8 nm WTe2-SBFET at different gate voltages. The left and right red dashed lines denote the gate voltages of OFF and ON states. (b) LDOS and the current density of 8.8 nm WTe2-SBFET at the ON state (Vg=1.02 V).

The above analysis indicates the ION are dominated by the tunneling through SB at source. This provides the design guidelines of the n-SBFETs: ION enhancement by reduction of SBH. In order to get the SBH reduction and enlarge the ION, we replace S/D regions of 1T-2H-1T MoSe2-SBFET and WSe2-SBFET by1T-MoTe2 and 1T-WTe2, respectively. Figure 5a shows transmission spectra of 1T-2H-1T MoSe2-SBFET before and after the S/D regions replacing by 1T-MoTe2. One can find the transmission spectrum shifts to left after the S/D regions replacing by 1T-MoTe2 leading to the reduction of the SBH. As a result, in Figure 5b, the ION is boosted up from previous 784 µA/µm to 1121 µA/µm. Figure 5c shows transmission spectra of 1T-2H-1T WSe2-SBFET before and after the S/D regions replacing by 1T-WTe2. One can find the transmission spectrum also shifts to left after the S/D regions replacing by 1T-WTe2 leading to the reduction of the conduction band SBH. Therefore,the ION is 7



boosted up to 2011 µA/µm which is 2 times larger than that of forward 1T-2H-1T WSe2-SBFET. The enhanced performance makes it also satisfy the ITRS HP requirements.

Figure 5. (a) and (b) Transmission spectra and transfer characteristics of MoSe2-SBFET before and after the S/D regions replacing by 1T-MoTe2. (c) and (d) Transmission spectra and transfer characteristics of WSe2-SBFET before and after the S/D regions replacing by 1T-WTe2.

In addition, we also replace S/D regions of 1T-2H-1T MoSe2-SBFET and MoTe2-SBFET by1T-WSe2 and 1T-WTe2, respectively. Figure 6a and c show the changes of the transmission spectra are very small after the S/D regions replacing by 1T-WSe2 and 1T-WTe2 leading to the tiny reductions of the SBH. As a result, the transfer characteristics of two junctions are similar to their previous performances, see Figure 6b and d. In a word, the adjustment on performance of the 1T-2H-1T TMD-SBFETs induced by changing chalcogen species are very significant than that induced by changing transition-metal species.

8


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Figure 6. (a) and (b) Transmission spectra and transfer characteristics of MoSe2-SBFET before and after the S/D regions replacing by 1T-WSe2. (c) and (d) Transmission spectra and transfer characteristics of MoTe2-SBFET before and after the S/D regions replacing by 1T-WTe2.

In Figure 3d, 5.1nm WTe2-SBFET can’t satisfy the ITRS HP requirements due to the increased short channel effect which enlarge the SS of SBFET.42 To weaken the short-channel effect, underlap (UL) structures, which extends the channel length without covering of metal gate, are introduced in WTe2-SBFET with 5.1nm physical gate length. UL can increase the effective channel length and reduce the source/drain-channel coupling, thereby can significantly lower tunneling leakage current and the SS.42 In this work, we introduce the underlap region between the source and the channel (SUL) or between the channel and the drain (DUL), separately. Figure 7a shows the comparison of the transfer characteristics with or without UL for 5.1nm WTe2-SBFET. A short SUL, which the length is 0.2 LG, can significantly lower tunneling leakage current and the SS leading to the IOFF satisfy the ITRS HP requirement (0.1 µA/µm). In addition, the maximum drain currents also decrease in comparison with WTe2-SBFET without UL. Although the ION drops down to 942 µA/µm, it is still beyond the ITRS HP requirements for 5.1nm physical gate lengths 9



(900 µA/µm). However, a same length DUL (0.2 LG) can’t lower tunneling leakage current and the SS significantly. So, a longer DUL (0.4 LG) is introduced which decreases the leakage current to 0.03 µA/µm. More important, we find the DUL has a little effect on the maximum drain current. As a result, the ION rise to 1420 µA/µm which is beyond the ITRS HP requirements for 5.1nm physical gate lengths largely.

Figure 7. (a) IOFF suppression by source or drain underlap design to increase effective channel length for 5.1nm WTe2-SBFET. LDOS of SUL WTe2-SBFET (b) and DUL WTe2-SBFET (c) at Vg=0.9 V. The triangular conduction band SBs are marked with red rectangular wire frames. Two transmission eigenstates, ES1 and ES2, at the EF of source of the ON state for SUL WTe2-SBFET (d) and DUL WTe2-SBFET (e). The isovalues are fixed 0.2 for all eigenstates.

To explain the different effects of SUL and DUL on the maximum drain currents, we show LDOS of two junctions at Vg=0.9 V in Figure 7b,c. From the figure, one can see the UL can’t modulate the SBH what ever at the source or at the drain. When the gate voltage increases, the CBM of the 2H-channel region will shift down leading to form the triangular conduction band SBs. At Vg=0.9 V, the triangular conduction band SBs in Figure 7b is thicker than that in Figure 7c because the UL locates between the source and the channel. The thicker triangular conduction band SBs make the electrons difficult to tunnel through the barrier. This can be explained by the transmission eigenstates at the EF of source in Figure 7d,e. For SUL structures, the incoming wave functions of one eigenstate (ES1) delocalize over the whole device 10


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including the central channel and drain. However, the incoming wave functions of another eigenstate (ES2) just localize on the source which can be see clearly in Figure 7d. For DUL structures, in Figure 7e, we find the incoming wave functions of two eigenstates (ES1 and ES2) delocalize over the central channel and drain. That’s why the maximum drain currents of WTe2-SBFET with SUL are lower than that with DUL. Table 2. Benchmark of the Ballistic Performance Upper Limits of the 6 SBFETs against the ITRS Requirements for HP Devices of the Next Decades.

Device WSe2 (1T-WTe2 S/D) WTe2 WTe2 WTe2 WTe2 (DUL=0.4 LG) WTe2 (SUL=0.2 LG)

LG (nm)

SS ION/ IOFF (mV/dec)

Cg (fF/µm)

τ (ps)

DPI (fJ/µm)

8.8

75

2.0×104

0.219

0.073

0.115

8.8 7.3 6.1

61 73 93

1.7×104 1.5×104 1.2×104

0.302 0.295 0.234

0.128 0.136 0.129

0.160 0.141 0.104

5.1

85

1.3×104

0.154

0.076

0.063

5.1

96

9.5×103

0.194

0.131

0.079

Table 2 summarizes the figures of merits of 6 devices which satisfy ITRS HP requirement. For WTe2-SBFET, its SS will increase gradually with the reduction of physical gate length. Because WTe2-SBFET with SUL structure has the highest SS, its ION/IOFF ratio is smallest in all device. Although WSe2-SBFET with the S/D regions replacing by 1T-WTe2 doesn’t has lowest SS, its ION/IOFF ratio is biggest in all device due to the huge rise of the ON current. The intrinsic gate capacitance Cg is another key parameter and is defined as C g = ∂Qch / ∂VG , where QCH is the total charge of the channel. One can see Cg will decrease slowly with the reduction of physical gate length and is generally smaller than the half ITRS values (Table 1). The intrinsic transistor delay time τ is defined as τ = ∂Qch / ∂I ds . We find transistor delay times of 8.8nm, 7.3nm and 6.1nm WTe2-SBFETs are all less than one third of ITRS values. WSe2-SBFET with the S/D regions replacing by 1T-WTe2 has the lowest transistor delay time ( τ =0.073 pS), which indicates the S/D regions replacing will be a effective way to lower the transistor delay time. We estimate the Dynamic Power 11



Indicator (DPI) per width by the equation DPI = Vdd × I ON × τ . The figure shows the DPI of 8.8nm, 7.3nm and 6.1nm WTe2-SBFETs are all less than half ITRS values and also decreases slowly with the reduction of physical gate length. The DPI of WTe2-SBFET with UL structure are smaller than other four device. That means the UL can be used as a effective modulation to reduce the DPI. CONCLUSIONS In conclusion, we have simulated the performances of the monolayer SBFETs based on four IP hetero-junction of 1T-phase and 2H-phase TMDs. Our study shows that the SBH of these IP 1T/2H contacts are proportional to their band gaps (EG): the smaller EG corresponds to smaller SBH. It is found that the WTe2-SBFET provides the best performance, and it can satisfy the ITRS HP requirement down to a 6 nm gate length. In addition, the replacement of suitable 1T-TMD on the S/D regions can modulate conduction band SB leading to WSe2-SBFET (LG=8.8 nm) also satisfying the ITRS HP requirement. More over, the introduction of the UL can increase the effective channel length and reduce the source/drain-channel coupling leading to 5.1 nm WTe2-SBFET also satisfying the ITRS HP requirement. The underlying physical mechanisms are discussed and it is concluded that the IP SB engineering is the key point to optimize such 2D devices. AUTHOR INFORMATION Corresponding Author *E-mail: [email protected]; [email protected] Notes The authors declare no competing financial interest. ACKNOWLEDGMENTS This work was supported by the National Natural Science Foundation of China (Grant Nos. 11674039, 11574304 and 11774388), the Scientific Research Fund of Hunan Provincial Education Department (Grant No. 15A004). X. W. Jiang acknowledges the support to this work by the Youth Innovation Promotion Association CAS (grand No. 2016109) and Chinese Academy of Sciences-Peking University Pioneer Cooperation 12


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Improving Performances of In-Plane Transition-Metal Dichalcogenide

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