Interface engineering for controlling device properties of organic anti

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Interface engineering for controlling device properties of organic anti-ambipolar transistors Kazuyoshi Kobashi, Ryoma Hayakawa, Toyohiro Chikyow, and Yutaka Wakayama ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b14652 • Publication Date (Web): 26 Dec 2017 Downloaded from http://pubs.acs.org on December 26, 2017

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ACS Applied Materials & Interfaces

Interface

engineering

for

controlling

device

properties of organic anti-ambipolar transistors

Kazuyoshi Kobashi,†,‡ Ryoma Hayakawa,† Toyohiro Chikyow,† and Yutaka Wakayama*,†,‡

†

International Center for Materials Nanoarchitectonics (WPI-MANA), National Institute for

Materials Science (NIMS), ‡

Department of Chemistry and Biochemistry, Faculty of Engineering, Kyushu University

1-1 Namiki, Tsukuba 305-0044, Japan

ACS Paragon Plus Environment

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ABSTRACT: The main purpose of this study is to establish a guideline for controlling the device properties of organic anti-ambipolar transistors. Our key strategy is to use interface engineering to promote carrier injection at channel/electrode interfaces and carrier accumulation at a channel/dielectric interface. The effective use of carrier injection interlayers and an insulator layer with a high dielectric constant (high-k) enabled the fine tuning of device parameters, and in particular the onset (Von) and offset (Voff) voltages. A well-matched combination of the interlayers and a high-k dielectric layer achieved a low peak voltage (0.25 V) and a narrow onstate bias range (2.2 V), indicating that organic anti-ambipolar transistors have high potential as negative differential resistance devices for multi-valued logic circuits.

KEYWORDS: anti-ambipolar transistor, pn-heterojunction, negative differential resistance, carrier injection, high-k dielectric, organic field-effect transistor


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Introduction Negative differential resistance (NDR) is a nonlinear carrier transport property, where the electrical current decreases with increasing bias voltage. Owing to this uniqueness, NDR has the potential for various electronic applications, including memory, fast switches and multi-valued logic circuits.1–5 In particular, multi-valued logic circuits are expected to be promising candidates for future electronic device architecture.4,5 To date, the Esaki diode and the resonant tunnelling diode have been investigated as NDR devices.6,7 However, these NDR devices have a fatal bottleneck, namely a poor peak-to-valley ratio (PVR). In spite of the fact that a large PVR of more than 104 is needed for practical applications in electronic circuits,8,9 previously reported PVRs have all been below 30 at room temperature.10 Recently, gate-tuneable anti-ambipolar transistors have attracted considerable attention11-16 as an alternative solution for NDR devices instead of tunnelling-based diodes. The electrical current and device structure are illustrated schematically in Fig. 1. The characteristics of the device structure are a partially overlapped pn-heterojunction in the middle of the transistor channel, and the p- and n-type channels are separately connected with respective electrodes. The drain current flows within a certain gate bias range when both the p- and n-channels are conductive simultaneously. As a result, a sharp increase and decrease in electrical current can be induced by supplying a gate bias voltage, which is analogous to that of the NDR in terms of nonlinearity. Therefore, anti-ambipolar transistors offer potential as NDR devices. The performance of an anti-ambipolar transistor can be characterized by certain parameters, namely onset (Von) and offset (Voff) gate bias voltages, on-state bias range (∆V=Voff −Von), peak current (Ipeak) and voltage (Vpeak) at the maximum current and PVR (=Ipeak/Ivalley) as shown in Fig. 1. Among these parameters, an advantage of the anti-ambipolar transistor is that it can be


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assigned a large PVR of more than 104. Such a high PVR can be achieved due to the small valley current (Ivalley) compared with conventional diode-based NDR devices.11 If we are to progress to the next step, we must search for guidelines to control the other parameters. The purpose of this study is to establish ways to manipulate these device parameters, with the particular aim of realizing a low operation voltage (low Vpeak) with a narrow ∆V. This is because these parameters are required if we are to design low power multi-valued logic circuits. Our key strategic approach is “interface engineering”. To achieve our purpose, we employ interlayers between electrodes and channels and a high-k gate-insulating layer to adjust carrier injection and to reduce the operating voltage, respectively.

Experimental methods Device fabrication. The device and molecular structures are shown schematically in Fig. 2a. Highly doped Si wafers with a thermally grown SiO2 layer (200 nm) were used as substrates. These work as a bottom gate electrode and a gate dielectric, respectively. The substrates were ultrasonically cleaned with acetone and isopropyl alcohol in sequence, followed by ultraviolet/ozone cleaning. Poly(methyl methacrylate) (PMMA) solution (1 wt.% in toluene) was spin-coated on the SiO2 surface at 6000 rpm for 60 sec to form a 10-nm-thick film. The films were then baked in an oven at 120 °C for 1 hour. The PMMA layer is indispensable for terminating the defects on the SiO2 surface and thus facilitating carrier transport through the channels. On this surface, organic semiconductor layers of α-sexithiophene (α-6T) as a p-type channel and N,N′-dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C8) as an n-type channel were thermally evaporated in a vacuum with a background pressure of 10–7 Pa through corresponding shadow masks. Both layers were grown at a fixed deposition rate of 1.0


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monolayer (ML)/hour at a substrate temperature of 60 °C. Such slow deposition rates are advantageous for realizing up-right orientations of molecules, layer-by-layer growth for fine thickness control and flat interface between 6T and PTCDI-C8. The thicknesses were 3 MLs for α-6T and 12 MLs for PTCDI-C8, respectively. The energy level diagram of a thus prepared pnheterojunction was confirmed with photoelectron yield spectroscopy and optical absorption spectra as shown in Fig. S1a. Subsequently, Au thin films as source and drain electrodes with and without charge injection layers (MoO3 and Cs2CO3) were deposited by thermal evaporation through another set of shadow masks. Device geometries, such as the length (L) and width (W) of the channel and the pn-heterojunction length (∆L), are shown in a photograph in Fig. S1b in the Supporting Information. With regard to the high-k gate dielectric, an Al2O3 film was grown directly on highly doped Si wafers. First, the SiO2/Si substrates were chemically cleaned by the Shiraki method,17 followed by HF treatment to etch the SiO2 surface layer. Then, the substrates were immediately transferred into an atomic layer deposition reactor. A 30 nm-thick Al2O3 film was deposited by alternating exposures of Al(CH3)3 and H2O vapour at a substrate temperature of 250 °C. The following processes used for device fabrication are the same as those used for the above mentioned pristine devices. Device characterization. The carrier transport properties of the devices were measured using a semiconductor device analyser (Agilent B1500A). All the measurements were performed in a vacuum at room temperature.

Results and discussions


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The red line in Fig. 2b shows the drain current (ID) - gate voltage (VG) curve of p-type operation obtained from a pristine device, where the SiO2 layer worked as the gate dielectric and gold electrodes were in direct contact with the channel layers. The device properties are summarized in Table S1 in the Supporting Information. A Vpeak of −40 V was needed to yield a PVR of 1.2×102 and a ∆V of 14 V. Here, VG was swept from 0 V to –60 V at a constant sourcedrain bias voltage (VD) of –60 V. This current flow scenario is analogous to that of shootthrough current (STC), which is transient current generated by the simultaneous operation of both p- and n-type transistors in CMOS circuits.18 An important factor in terms of realizing the STC-based mechanism is that the organic semiconductors are intrinsically semiconducting in general because of large energy gaps (2 eV ~ 3 eV). The intrinsic carrier concentration is negligibly small and no drain current is observed when only forward drain bias was applied. This is a normally-off mode. In this condition, the applied bias potential is divided into source-gate and drain-gate electrodes. As a result, VG can work as an effective parameter for tuning the large increase and decrease in the drain current in the VD (0 < VG < VD) range. For example, a low VG (0 V ~ −28 V) causes a large VD–VG (60 V ~ 32 V), yielding a potential gradient mainly in the PTCDI-C8 layers that make it conductive. However, no drain current was observed due to the small VG, which is lower than the threshold voltage of the 6T channel. In the mid-VG range (−28 V ~ −53 V), well balanced VG and VD-VG values make both the 6T and PTCDI-C8 layers conductive, which allows a high drain current flow. A further increase in the VG region above −53 V reduces the drain current. This is due to the low conductance of the PTCDI-C8 layer caused by the reduced VD–VG Three sets of energy level diagrams in the insets of Fig. 2b explain the operation mechanism of this anti-ambipolar transistor.


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Most previously reported anti-ambipolar transistors were realized by using transition metal dichalcogenide (TMDC) thin films as the channel layers.11–16 In contrast to organic semiconductors, TMDCs have high intrinsic carrier concentrations due to their small band gaps (1 eV ~ 2 eV); drain current flows under a forward bias condition even without a gate bias voltage.19,20 This is a normally-on mode. Therefore, the current flows of the TMDC-based antiambipolar transistors can be explained as simple overlaps of the respective ID-VG characteristics of the pristine n- and p-channel transistors. As a result, a wide ∆V range even beyond 40 V1113,15,16

is possibly required depending on the channel materials.

When we consider the operation mechanism, Von and Voff are primary factors that determine other parameters (∆V, Vpeak, Ipeak and PVR). It is noteworthy that these depend on the threshold voltages (Vth) of individual α-6T and PTCDI-C8 transistors. The threshold voltage of organic field-effect transistors (OFETs) is generally tuneable by inserting charge injection layers, such as WO3, MoO3, V2O5, Cs2CO3 or LiF layers.21–23 These interlayers between the contact electrode and semiconducting channel layers effectively reduce the carrier injection barrier to decrease contact resistance,24 which suppress the voltage drop at the interface. As a result, the threshold voltage is lowered. Based on these facts, a MoO3 interlayer was employed to enhance hole injection in this study because it is generally known that MoO3 has energy states in the band gap, and those levels are located between the Fermi level of Au and the HOMO level of 6T and, as a result, hole injection can be promoted.25,26 The purple line in Fig. 3a shows an ID-VG curve, in which a MoO3 interlayer was inserted at the α-6T/source interface. The ID-VG curve (red line) of the pristine device is duplicated from Fig. 2b as a reference. Von was clearly reduced from −34 V to −26 V, while Voff remained around −45 V ~ −48 V. This is a result of enhanced hole injection


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from the source to the α-6T channel. The reduction in Von accompanied variations in other parameters, which are an increase in ∆V, Ipeak and PVR and a decrease in Vpeak. To confirm our discussion, we simulated the electrical transport as shown in Fig. 3b. These curves were numerically estimated from the output characteristics of the PTCDI-C8 and α-6T transistors with and without a MoO3 interlayer, respectively (see Figs. S3a-d in the Supporting Information). This simulation was based on the assumption that a CMOS inverter is composed of individual transistors, and a voltage (VDD) of −60 V is supplied as illustrated in the schematic circuit diagram in the inset. These curves clearly coincide with those in Fig. 3a, providing two important pieces of evidence. One is that the electrical current can be explained in terms of shoot-through current as with the CMOS device. The other is that the interlayer for the carrier injection is effective for controlling the anti-ambipolar properties. A similar tendency was confirmed with Cs2CO3 interlayers. Cs2CO3 has been already known to be decomposed during thermal evaporation to produce metallic Cs. Then, the metallic Cs reduces the contact resistance to enhance electron injection due to its low work function.27–29 The ID-VG curve (purple) in Fig. 4a shows an n-type operation obtained from a device with a Cs2CO3 interlayer at a PTCDI-C8/source interface. The ID-VG curve of the pristine device (red) is also shown for comparison. As shown here, enhanced electron injection by the interlayer resulted in the reduction of Von from 9.8 V to 1.9 V, while Voff remained constant at around 23 V. Figure 4b shows another ID-VG curve (purple) for a p-type operation. In this device, both MoO3 and Cs2CO3 interlayers were inserted at the interfaces between electrodes and α-6T and PTCDIC8 channels, respectively. Enhanced carrier injection from both electrodes caused significant broadening of the on-state bias range (∆V= 33 V).


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It is worth emphasizing that the interface engineering for carrier injection is a distinct advantage of organic semiconductors as the anti-ambipolar transistors, particularly when compared with TMDC-based counterparts. With TMDC transistors, contact engineering at a metal/semiconductor interface is hampered due to a strong Fermi level pinning effect.30,31 This effect fixes the threshold voltages and makes fine control of the device parameters difficult. On the other hand, metal/semiconductor interface engineering is well established in OFETs. For example, the threshold voltages of OFETs can be tuned by changing the work functions of contact metals or by introducing a charge injection layer.21,32,33 In this study, the device design flexibility of organic semiconductors has been adopted for the anti-ambipolar transistor. Next, the concept of the interface engineering was expanded with the aim of lowering the operation voltage (Vpeak) and narrowing the on-state bias range (∆V). The first strategy for this purpose is to adopt Cs2CO3 interlayers for both PTCDI-C8 and α-6T channels. As discussed in Fig. 4a, the Cs2CO3 interlayer enhanced carrier injection to the PTCDI-C8 channel and thus reduced Von. Conversely, we expected the Cs2CO3 interlayer at the α-6T/electrode interface to work as a barrier layer and, as a result, Voff would be reduced. The red and purple lines in Fig. 5a show the ID-VG curves of the n-type operation obtained from the pristine device and that obtained with Cs2CO3 interlayers with both electrodes. These curves were normalized by the maximum current (Ipeak) for ease of comparison. Vpeak was reduced significantly from 17 V to 2.4 V. Then, both Von and Voff shifted toward a lower gate bias voltage in parallel to the extent we expected. Another approach for reducing Vpeak is to employ a high-k gate dielectric insulator. Gate capacitance (Cox), which is an important parameter for charge accumulation at an organic semiconductor/dielectric interface, is given by the ratio between the permittivity (εox) and


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thickness (tox). A 30 nm-thick Al2O3 (k = ~9)34 layer is more effective than a 200 nm-thick SiO2 (k = 3.9) layer in this regard. The green line in Fig. 5a shows an ID-VG curve obtained from a device with both Cs2CO3 double interlayers and an Al2O3 gate dielectric. As shown here, Vpeak was significantly reduced to 0.25 V. Another improvement was observed in ∆V, which was narrowed to 2.2 V. The graphs in Fig. 5b shows the variations in Vpeak and ∆V. Both are similarly reduced by introducing Cs2CO3 interlayers and an Al2O3 gate dielectric. A main impact of the Cs2CO3 interlayers was a large decrease in Vpeak. A high-k Al2O3 dielectric was effective particularly on ∆V and Vpeak. The combination of the Cs2CO3 interlayers and the high-k Al2O3 dielectric achieved a two-order decrease in Vpeak and a one-order decrease in ∆V. By contrast, Ipeak remained of nanoampere order (13 nA~ 64 nA), although it also exhibited a constant decrease with this interface engineering. An additional benefit of interface engineering can be found in the drain bias voltage (VD). The VD value should be larger than the threshold voltage, and so a VD of −60 V was necessary with the pristine anti-ambipolar transistor as shown in Fig. 2b. In contrast, a VD of 10 V was enough to drive the green ID-IG curve in Fig. 5a. In this manner, VD was notably reduced owing to the lowered Vth. It should be noted that the device with the Cs2CO3 interlayers and Al2O3 gate dielectric showed one order degradation of PVR (1.4×103) compared to that of the pristine device (5.9×104), although the Ipeak was on the same nanoampere order. The reason can be ascribed to leakage current though the gate dielectric layer to increase Ivalley. Further optimization of the thickness and deposition conditions of the Al2O3 gate dielectric will refine this issue.

Conclusion


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In conclusion, we established a guideline to control device parameters of organic antiambipolar transistors. The leading parameters to determine PVR, Vpeak and ∆V were Von and Voff. A superiority of organic semiconductors against TMDCs counterparts is that the Von and Voff are widely tunable by carrier injection interlayers and high-k gate dielectric. Appropriate parallel use of the Cs2CO3 interlayers and Al2O3 gate dielectric achieved the significant low operating voltage at 0.25 V and narrow on-state bias range of 2.2 V. These results suggest that our device is a potential candidate for realizing functional circuit such as multi-valued logic circuit in next generation electronic device architectures.


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Figure captions

Figure 1. Schematic illustrations of the device structure and drain current (ID)-gate voltage (VG) curve of an anti-ambipolar transistor. The sharp increase and decrease in the drain current can be explained in terms of shoot-through current, which can be observed at transient states between pand n-type operations in a CMOS inverter. The device performance parameters are characterized by peak-valley ratio (PVR=Ipeak/Ivalley), onset (Von) and offset (Voff) bias voltage, on-state bias range (∆V=Voff-Von) and driving voltage (Vpeak). Here, Von and Voff are determined by extrapolating the slopes of the √ID-VG curves.


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Figure 2. (a) Device and molecular structures. PTCDI-C8 and α-6T are employed as n- and ptype transistor channels, respectively. (b) ID-VG curve of the p-type operation of the pristine device. Three sets of energy level diagrams represent the operation mechanism of organic antiambipolar transistor. Drain current can flow within a certain VG range around −40 V, allowing a clear increase and decrease in drain current as with an NDR device.


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Figure 3. (a) ID-VG curves of the p-type operation obtained from a device with a MoO3 interlayer at an α-6T/source interface (purple) and a pristine device (red). A distinct difference can be assigned to the lowered Von induced by enhanced carrier injection from the source to the α-6T channel. (b) ID-VG curves simulated from individual output characteristics of α-6T and PTCDI-C8 pristine transistors. The shapes of the curves coincide well with the experimental data (Fig. 3a), proving the SCT-based operation mechanism and the effectiveness of the interlayer in controlling the operating bias voltage.


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Figure 4. (a) ID-VG curves of the n-type operation obtained from a device with a Cs2CO3 interlayer at a PTCDI-C8/source interface (purple) and a pristine device (red). (b) ID-VG curves of the p-type operation obtained from the device with both MoO3 and Cs2CO3 interlayers at respective interfaces (purple) and pristine device (red).


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Figure 5. (a) ID-VG curves of the n-type operation obtained from the pristine device (red), the device with double Cs2CO3 interlayers at both interfaces on SiO2 (purple) and that on the Al2O3 (green) film. These curves are normalized at the maximum current for comparison. (b) Variations in the Vpeak and ∆V of respective device architectures.


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AUTHOR INFORMATION Corresponding Author *E-mail: [email protected]

Notes The authors declare that they have no competing financial interest.

ACKNOWLEDGMENT This research was supported by the World Premier International Center (WPI) for Materials Nanoarchitectonics (MANA) of the National Institute for Materials Science (NIMS), Tsukuba, Japan, JSPS KAKENHI Grant Numbers JP15K13819 and JP23686051.

Supporting Information Fig. S1 (a) Energy level diagram and (b) optical image of anti-ambipolar transistor. Table S1. Device properties (Von, Voff, V, Vpeak, Ipeak and Peak-to-valley ratio). Fig. S2. Output curvers of the α-6T and PTCDI-C8 transistors with and without interlayers. Table S2. Vth, carrier mobilities and on/off ratios of the respective OFETs


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Interface engineering for controlling device properties of organic anti

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