Low-Temperature Side Contact to Carbon Nanotube Transistors

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Low-Temperature Side-Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length Gregory Pitner, Gage Hills, Juan Pablo Llinas, Karl-Magnus Persson, Rebecca S. Park, Jeffrey Bokor, Subhasish Mitra, and H.-S. Philip Wong Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.8b04370 • Publication Date (Web): 24 Jan 2019 Downloaded from http://pubs.acs.org on January 25, 2019

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Low-Temperature Side-Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length

Gregory Pitner1, Gage Hills1, Juan Pablo Llinas2, Karl-Magnus Persson1, Rebecca Park1, Jeffrey Bokor2, Subhasish Mitra1,3, H.-S. Philip Wong1

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Department of Electrical Engineering, Stanford University, Stanford, CA, USA

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Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA

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Department of Computer Science, Stanford University, Stanford, CA, USA

Keywords Carbon nanotube field-effect transistor, contact resistance, side contact, scaled transistor, variations, beyond-Si

Abstract Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of VLSI circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon

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nanotubes. Low-temperature fabrication (e.g. < 400°C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, high contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance in series with the channel resistance reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains unstudied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. In this work we investigate by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact length. These CNFET contacts are ≈15 nm shorter than the state-of-the-art Si CMOS “7 nm node” contact length allowing for multiple generations of future scaling of the transistor contacted gate pitch. For 10 nm contacts we report contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at VDS = 0.7 V compared to the best reported 200 nm contacts to-date, corroborated by results in this work. Our analysis of RC from 232 single-CNT


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CNFETs between the long contact (e.g. 200 nm) and short-contact (e.g. 10 nm) regimes quantifies the resistance variation and projects the impact on CNFET current variability versus number of CNT in the transistor. The resistance distribution reveals contact length dependent RC variations become significant below 20 nm contact length. However, a larger source of CNFET resistance variation is apparent at all contact lengths used in this work. To further investigate the origins of this contact length independent resistance variation we analyze variation of RC in arrays of identical CNFETs along a single CNT of constant diameter and observe random occurrence of RC even on correlated CNFETs. Main Text Introduction Researchers are exploring the use of semiconducting carbon nanotubes (CNTs) as the channel material for high-performance energy-efficient transistors in future computing systems. Due to the inherently thin channel body and the excellent charge transport properties of the CNT, carbon nanotube field-effect transistors (CNFETs) can deliver major benefits over incumbents and alternatives such as FinFETs, nanosheets, and nanowires made with bulk Si, Ge, or III-V semiconductors1. For example, experimental CNFETs are demonstrated for channel lengths down to 5 nm2,3 and operate at lower voltage with superior drive current


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than the best silicon transistors2,4. Furthermore, CNFETs can be fabricated below 400°C which is essential for a monolithic 3D technology platform in which logic and memory are sequentially fabricated layer by layer and interconnected with conventional back-end-of-line nanoscale vias that provide high interconnectivity density5–8. Computing systems using CNFET in a monolithic 3D device technology promise multiple orders of magnitude improvement in computational speed and energy efficiency for abundant-data applications such as big-data analytics and machine learning9. Advances towards using CNT as a channel material for VLSI systems have been demonstrated in various experiments, including the CNT imperfection-immune VLSIcompatible design paradigm10–12 that overcomes mispositioned and metallic CNTs, solid-state CNT complementary doping techniques2,13–15 threshold voltage (VT) control without hysteresis16,17, and dense assembly of aligned CNTs for high drive current transistors4,18,19. These advances have enabled large-scale functional demonstrations of CNT circuits and systems7,20–22. Despite recent progress on CNFET contacts, the reduction in CNFET drive current due to high metal-to-CNT contact resistance (RC) of CNFETs with short contact length (LC) remains a key barrier to a viable CNFET technology beyond the 5 nm node. Theoretical work has previously modeled the behaviors of the distributed contact to CNT across the long-contact and short-


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contact regime as a transmission line consisting of the series resistance (rs) along the CNT and the parallel conductance (gc) between the metal and the CNT23. Figure S1 illustrates the key issue. As the contact length enters the short-contact regime, it is projected that there will be a sharp increase in contact resistance proportional to 1/(gcLC) because the current has to flow across a finite distributed conductance between the metal and semiconductor23,24. One possible solution to this contact resistance increase in CNFETs is to utilize an end-contact geometry that does not increase RC as the contact dimension shrinks due to the contact-length invariant metal-to-CNT overlap. Cao, et al., have demonstrated RC of 18 kΩ for an end contact with ≈9 nm contact length (defined by the dimension of the metal line rather than the metal-to-CNT overlap length) using fabrication temperatures ranging from 650-850°C4,25. However, the high temperature end-contact formation process does not meet the requirements for monolithic-3D integration and lower RC is desired. Previous experimental studies of short distributed side contacts to CNFETs remain limited. Franklin, et al., has measured the distributed side-contact resistances for several metals when shrinking the contact dimensions from the long contact regime down to 20 nm15-16. Existing experimental data establishes excellent RC for long contacts. However there is a


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clear 1/LC trend for short contacts which presents the challenge of high RC for short CNFET contacts. Further experimental study is essential for a clear understanding of the path forward for CNFET as a technology. In this work we investigate by experiments the RC down to 10 nm contact length to determine for the first time the magnitude of the low-T contact resistance challenge for CNFETs beyond the 5 nm node. These CNFETs are fabricated entirely below 200°C to ensure monolithic 3D compatibility. We report a contact resistance of 6.5 kΩ for 10 nm contacts, which sets a new record. Statistical data on the RC variability is collected from a total of 232 single-CNT CNFETs for contact lengths between 200 nm and 10 nm to understand the origins and impact of RC variability. A new RC measurement methodology that accurately extracts the metal parasitic wiring resistance and controls for CNT diameter with correlated CNFETs provides valuable perspectives on the components that contribute to the overall CNFET resistance. Experimental Methods We fabricated palladium side-contacts to CNT down to ≈10 nm contact lengths, then extracted the contact resistance using a methodology that decouples several contributions to the overall CNFET resistance. The cross-section schematic shown in Figure 1a defines the local back-gate CNFET structure and labels


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dimensions for channel length (LCH) of 50 nm and contact length (LC) between 10 – 200 nm used in this paper. Supplementary information section 1 discusses tradeoffs between this backgated CNFET test structure versus a top-gated CNFET structure for studying the contact resistance. Figure 1b illustrates the test site array of CNFETs where one test site contains up to 8 identical short-channel CNFETs that are correlated along a single CNT.

Therefore contact resistance reported in this work

has units of kΩ per CNT for one contact.

Figure 1. CNFET RC Test Structure. (a) Cross-section schematic of the back-gated CNFET structure used in this work, defining the contact length LC and channel length LCH. The LC ranges from 200 nm to 10 nm, and LCH remains fixed at 50 nm. (b) Illustration of a single test site with up to 8 identical CNFETs fabricated along a single CNT of constant diameter. (c) Top-down SEMs of the as-fabricated single-CNT CNFET test site


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highlighting the large features patterned by optical lithography, and two metal pads connected symmetrically to each CNFET contact. (d) High magnification SEM verifying the patterned CNFET contacts have nominal contact lengths between 200 nm and 10 nm with a single CNT. Scale bars 100 nm. (e-f) Cross-section high resolution bright-field transmission electron microscope images highlighting the metal contact dimension for the shortest side-contacts to CNT reported todate ≈10 nm. The contacts in (e) display RC = 7.6 kΩ and the contacts in (f) display RC = 6.5 kΩ. Reference lines with labeled dimension are indicated on the widest part of the metal, however the contact is narrower at the metal-to-CNT interface. Figure 1c shows a typical device site post-fabrication using scanning electron microscopy, where each CNFET contact symmetrically connects to probe pads above and below the CNFET to allow for a direct measurement of the metal parasitic resistance. Each test site includes 8 CNFETs with the same contact length, and different test sites target contact lengths between 200 nm to 10 nm. Fabrication of 10 nm metal contacts required a careful procedure, including electron-beam lithography single-pass line exposure, granular dose arrays, thin PMMA resist, high-contrast developer, and thin metal films


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for liftoff. The fabrication steps are detailed in the supplementary information section 2. Each CNFET was inspected by SEM after electrical measurements to confirm the channel is formed by a single CNT and also to directly measure the contact dimensions. The typical dimensions of the fabricated CNFET contacts are indicated in Figure 1d, with a single CNT visible in each SEM and metal dimensions down to ≈10 nm. The dimensions of the shortest contacts were confirmed by high resolution transmission electron microscopy cross sections as shown in Figure 1e-f.

It is

apparent from these images that the metal wire narrows as it approaches the surface likely due to PMMA under-exposure and under-development, indicating the contact dimension is less than the value we report taken at the widest point of the contact. The dimensions reported in the test-sites shown in Figure 1d-f are typical and representative of the entire population, and we will discuss the effects of line edge roughness in a later section. The methodology used to extract RC from single-CNT CNFETs deserves careful treatment. Contact resistance in higher dimensional channel materials (e.g. 3D Si, 2D MoS2) is typically studied by extracting RC using the transmission line method (TLM), which is challenging to apply to single-CNT CNFETs due to variations in the electrical behaviors. Supplementary


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information section 3 and supplementary Figure S2 describe the practical challenges we encountered applying the standard TLM structures to CNFETs. Figure 2a defines a simple model for the components of CNFET resistance (RCNFET) including: the parasitic metal wiring resistances (2RM) between the pads and contact, the channel resistance (RCH) that is a function of VGS and VDS biases, and the contact resistances (2RC) defined as inclusive of the metal-CNT interface resistance and quantum resistance. Our methodology aims to extract RC by 1) decoupling RM using test structures on each CNFET and 2) measuring RCNFET in a regime where the RCH contribution is minimized. This allows us to use the assumption of 2RC >> RCH due to this work’s short channel CNFETs, and therefore estimate the upper bound RC as (RCNFET – 2RM)/2. In subsequent sections when we report RC values using this approximation, we mean to convey that the real RC is equal to or less than our reported RC.


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Figure 2. RC Measurement Methodology. (a) Define total CNFET resistance components: 2 × parasitic metal wire resistance (RM), 2 × contact resistance (RC), and channel resistance (RCH). We define contact resistance to include both the quantum resistance RQ and metal-CNT interface resistance RM-CNT. (b) IDVGS curve for the lowest resistance CNFETs in each contact length at VDS = -0.05 V. (c) The same devices re-plotted to illustrate RCNFET is sampled at fixed overdrive VGS – VT = -2 V to compensate for differences in transistor threshold voltage. (d) The sensitivity of RCNFET to VGS – VT is presented for the same devices as (b) illustrating that the CNFET resistance is being sampled in the regime with less gate voltage dependence and minimal channel resistance. (e) Plot of metal resistance versus contact length. Metal resistance is extracted from a symmetric


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test structure with two probe pads accessing each metal contact to the CNFETs. Inset: SEM of test structure, scale bar is 200 nm. Due to symmetry, the RM is half the total path resistance. For shorter CNFET contacts the metal resistance is comparable to the contact resistance and must be directly measured to report accurate RC values.

Each CNFET was electrically characterized to extract RCNFET by measuring the ID-VGS curve in the linear regime with VDS = 0.05 V to ensure low RCH (e.g. the device is not in the saturation region). The ID-VGS curves for the lowest resistance CNFETs at each contact length are shown in Fig 2b. To account for differences in the threshold voltage (VT), all RCNFET values were extracted for a constant overdrive (VOV) of VOV = VGS – VT = 2 V as illustrated in Fig 2c. This value of VOV was critical to measuring a distribution of RCNFET values that minimized the contribution of RCH, which could not consistently be achieved when the RCNFET is sampled at a lower VOV. The sensitivity of the extracted RCNFET value to VOV is illustrated in Figure 2d, illustrating that the RCNFET value asymptotically approaches a constant value. We separately extracted RM from a symmetric test structure on each CNFET contact, as described earlier. Figure 2e displays electrical measurements of RM versus LC for symmetric paths to


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each metal contact, where RM is half the resistance of the symmetric path. The inset labels each metal path from 1 to 9. For longer contacts the range of RM values for each group of devices with the same contact length is primarily due to difference in path length for the outermost devices compared to devices in the center (e.g. contacts 1 and 9 have longer paths compared to the center contact 5). The shortest metal contacts show a sharp increase in RM, and added RM variation due to lineedge roughness, which is a significant contribution to the overall CNFET resistance. If a CNFET yielded but had one of its metal leads broken, such that RCNFET could be measured but RM could not (which often occurred for the shortest lines but was rare for LC of 20 nm or longer) we minimize the metal lead resistance subtracted (thus maximizing RC) by assigning an RM value equal to the lowest yielded metal resistance from the same contact size, position and exposure dose. Contact Resistance Data and Discussion The distribution of RC values measured for contact lengths between 10 to 200 nm is reported in Figure 3a, which includes both the shortest low-temperature fabricated contacts and the lowest resistance CNFET contacts reported to-date. The number of devices yielded for each contact length ranges between 9 and 42, as tabulated in Figure 3a inset. We observed a ≈2-3× increase in the lowest and median RC values for the 10 nm contacts compared


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with the longer 60-200 nm contacts. The increasing RC trend for contacts below 30 nm LC is consistent with the distributed contact model for decreasing contact length described earlier27. As shown in Figure 3b this data set includes the lowest reported CNFET RC values for every contact length compared to all previous reports in the literature. To help compare subtle nanofabrication and measurement differences (e.g. device structure, fabrication details, and RC measurement strategy) between this work and the references in figure 3b, the key details of each work are organized in supplementary table S1. We attribute our achievements of low RC values to the combination of 1) metal resistance being more accurately subtracted for each CNFET especially at short contact length, 2) reporting data from a larger set of devices gives a higher probability to observe RC values closer to the lower end of the actual underlying distribution, and 3) sampling current at higher VOV compared to previous studies helped in extracting an RC that is closer to the actual RC by minimizing the RCH component in the total RCNFET. For the shortest ≈10 nm contacts the lowest RC value is 6.5 kΩ and the median value is 18.2 kΩ. This data demonstrates the scalability of low resistance CNFET contacts to 10 nm, which is 15 nm shorter than the anticipated LC for the upcoming 7 nm node foundry Si-CMOS.28 Further, experimental RC data for low resistance contacts with short contact lengths will enable a


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projection of the behavior of CNFET with properly scaled LC beyond the 5 nm node.29

Figure 3. Experimental RC data. (a) Cumulative distribution function (CDF) of contact resistance data. An increase in the contact resistance is observed in the resistance of the shortest contacts as expected from the distributed contact model. The x-axis is presented in log scale to capture the entire resistance distribution. Inset: Table quantifying number of CNFETs in the RC distribution for each contact length. The shortest contacts are reported as a range of LC to account for line edge roughness. (b) The best and median RC values from this work are compared to previously reported side- and endcontacts to CNFETs, and demonstrate lower resistance. The best RC for 10 nm LC is 6.5 kΩ.

The data from Cao 2015 was

fabricated at 850°C, while this work’s contact was fabricated at 25°C by metal evaporation.


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The measured distribution of RC values allows for projecting the drive current impact of short contacts at the transistor level. In Figure 4a-b we use the virtual source CNFET model that has been calibrated to experimental data for a 15 nm LCH CNFET30,31 to quantify the degradation in the CNFET drive current due to short contact lengths. The simulation parameters are listed in Figure 4c based on model calibration from Lee, et al.30,31 With a single CNT per CNFET the model predicts a 13% degradation in ION comparing the best 200 nm contact to the best 10 nm contact from this work at a VDS of 0.7 V, and a 35.5% degradation when comparing the 10 nm median RC values against the median 200 nm contact RC from this work. Even considering this degradation, a 10 nm contacted CNFET with our median RC value that has 150 CNT/µm in the channel can achieve ≈1.5 mA/µm of on-current density at VDS = -0.5 V by simple linear extrapolation from Figure 4a (with IOFF density 100 pA/µm). Furthermore, we can project the ION variability due to the RC distribution, which at first glance appears concerning due to the >10× spread in values of RC observed for 10 nm LC. However, realistic CNFETs contain multiple CNTs which reduces the impact of the RC variability due to an averaging effect. To explore this trend, in Figure 4b we simulate ION variation versus number of CNTs in a CNFET using a Monte-Carlo sampling of our experimental distribution. We observe that the overall variation quickly averages out with


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multiple CNTs and improves more gradually for more than 5 CNTs per channel corresponding to 33 nm device width (roughly corresponding to the fin pitch for a 7 nm FinFET28) for a CNT density of 150 CNT/µm. Interestingly, the increase in variability between the 10 nm contacts and long contacts in our CNFETs is less than the magnitude of overall variability at long contact lengths. Therefore, future work to minimize performance degradation due to RC variation should begin with the goal of understanding and improving the RC distribution in the simpler case of long contact lengths.

Figure 4. Device-level impact of RC degradation and variation. (a) A calibrated Virtual-Source CNFET current model30,31 is utilized to quantify the on-current degradation due to short contact lengths. VGS is 1.75 V and IOFF is 0.6 pA/CNT (b) A Monte-Carlo simulation of the ION variation (standard deviation / mean = 𝜎𝐼𝑂𝑁/𝜇𝐼𝑂𝑁) versus number of CNTs in the CNFET by randomly sampling from the experimental RC distribution for four contact


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lengths. The penalty for RC variation decreases with number of CNT, but all contact lengths experience an ION variability magnitude larger than the difference between 10 nm and 100 nm contacts. Therefore a future goal should be to understand the mechanisms that contribute to RC variation for all contact lengths, not just the shortest contacts. (c) Default parameters used in the calibrated VS-CNFET model publication, and the RC values used in part (a).

In order to improve the RC variability, we must first understand the underlying mechanisms causing the observed spread. We considered several possible origins of the variation, which future studies should explore more thoroughly: contact length variations, CNT diameter variations, and random defects. Figure 5a re-plots the RC cumulative distribution from Figure 3a with a linear x-axis to facilitate a discussion about the shape of the distribution. Each contact length distribution displays a shape with two distinct regions, which we will discuss separately: the body and the tail. The body of the distribution has a clear dependence on the contact length below 20 nm LC. Figure 5b plots the standard deviation of the 0-50th percentile devices comprising the body of the distribution versus contact length. This standard deviation (a few kΩ) of the 0-50th percentile devices increases with shorter contact length. In figure


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S4 we quantify the root-mean-squared line edge roughness (LER) for lines with several contact lengths from SEMs in figure 1d. The 10 nm lines have the largest roughness of 4.4 nm and the roughness decreases for longer contacts both in terms of the LER and as a fraction of the nominal line width. Therefore we attribute this variation in RC to line edge roughness of the narrow metal lines changing effective LC for shorter LC devices. The impact of this line edge roughness more significantly influences the shortest metal lines, consistent with the observed trend.

Figure 5. RC Variability Analysis. (a) Re-plotting the CDF data from Figure 3a in a linear scale and highlighting values for RC < 40 kΩ shows that the distributions contain two distinct shapes: 1) the body of the distribution that comprises the lowest RC values at each LC, and 2) the long tail of the high resistance distribution. (b) The standard deviation of the distribution body (defined as 0 to 0.5 of the CDF) shows a clear LC dependence. We attribute this increase in standard deviation to line edge roughness in the steepest part of the RC


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vs LC curve for short contacts. (c) However, standard deviation of the tail of the distribution (from the kink at the boundary between the body and the tail to 1 of the CDF) is significantly larger for long and short contacts than the standard deviation of the body, suggesting a separate mechanism is responsible.

However, the standard deviation of the distribution tail is large (10s of kΩ) for both long (e.g. 100-200 nm) and short (e.g. 10-20 nm) contacts as shown in Figure 5c, which plots the standard deviation of the tail (from the edge of the body to the 100th percentile device) of the RC distribution. This indicates a separate mechanism contributes to the tail of the distribution, and this mechanism may not solely depend on the contact length. One likely source of contact resistance variation that has been widely discussed in the literature is CNT diameter. Smalldiameter CNTs give rise to a larger Schottky barrier and the Schottky barrier can change the contact resistance by orders of magnitude.32,33 Another potential source of variation is random defects due to contaminating particles, lithography failures, nearby traps/charges, or other CNT imperfections that lead to outlier transistor behavior. The CNFET test structure used in this work uniquely correlates an array of up to 8 identical CNFETs along a small region of a single-CNT, which allows for inspection of whether the RC tail is due to diameter variation or


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random mechanisms. The CNT diameter was inspected in 15 test sites (each test site contains one correlated CNFET array) using atomic force microscopy. The reported diameter is averaged over more than 20 scans on both sides of the CNFET array. In supplementary figure S3 we plot the RC values versus CNT diameter and observe no clear trend versus the measured CNT diameter. However we do observe mostly clustered RC on the same CNT, with frequent random outliers with >5× larger resistance. This suggests the tail of the distribution is dominated by random defect mechanisms such as lithography defects, process residues, CNT damage, or traps. Conclusions In this work we have performed experiments in order to investigate the behavior of low-temperature fabricated Pd p-type CNFET contacts down to 10 nm contact length. We report record low contact resistances for contact lengths from 10 nm to 200 nm. The results addressed a key concern about contact resistance of properly scaled CNFETs for which the gate length and the contact length must be scaled down together. Our statistical RC data at each contact length describe the typically achievable RC for accurate CNFET on-current projection and enable an analysis of multi-CNT CNFET ION variability. To improve the RC-induced variations, future work should aim to minimize contact metal line edge roughness and investigate the origin of the random


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defects responsible for the distribution tail. For CMOS circuits, future work should also duplicate this analysis with other contact metals capable of achieving low contact resistance of n-type CNFETs. Acknowledgement This work is supported in part by the DARPA ERI 3DSoC program, and member companies of the Stanford SystemX Alliance. We appreciate Rich Tiberio’s valuable advice about e-beam lithography and Jim McVittie for fruitful discussions.

Part of

this work was performed at the Stanford Nano Shared Facilities (SNSF) and Stanford Nanofabrication Facilities (SNF), supported by the National Science Foundation under award ECCS-1542152. This work was supported in part by the Office of Naval Research BRC and MURI programs under grant N00014-16-1-2229. J.P.L. is supported by the Berkeley Fellowship for Graduate Studies and by the NSF Graduate Fellowship Program. Supporting Information The supporting information discusses in greater detail the local back-gate test structure, CNFET fabrication procedure, transmission line measurements, distributed contact model, and data from the correlated CNFET test structures.


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Low-Temperature Side Contact to Carbon Nanotube Transistors

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