Low-Voltage Organic Single-Crystal Field-Effect Transistor with Steep

Mar 6, 2018 - Anodization is a promising technique to form high-k dielectrics for low-power organic field-effect transistor (OFET) applications. Howev...
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Low-Voltage Organic Single-Crystal Field-Effect Transistor with Steep Subthreshold Slope Fangxu Yang, Lingjie Sun, Jiangli Han, Baili Li, Xi Yu, Xiaotao Zhang, Xiaochen Ren,* and Wenping Hu* Tianjin Key Laboratory of Molecular Optoelectronic Sciences, Department of Chemistry, School of Sciences, Tianjin University & Collaborative Innovation Center of Chemical Science and Engineering, Tianjin 300072, China S Supporting Information *

ABSTRACT: Anodization is a promising technique to form high-k dielectrics for low-power organic field-effect transistor (OFET) applications. However, the surface quality of the dielectric, which is mainly inherited from the metal electrode, can be improved further than other fabrication techniques, such as sol−gel. In this study, we applied the template stripping method to fabricate a low-power singlecrystalline OFET based on the anodized AlOx dielectric. We found that the template stripping method largely improves the surface roughness of the deposited Al and allows for the formation of a high-quality AlOx high-k dielectric by anodization. The ultraflat AlOx/SAM dielectric combined with a single-crystal 2,6-diphenylanthracene (DPA) semiconductor produced a nearly defect-free interface with a steep subthreshold swing (SS) of 66 mV/decade. The current device is a promising candidate for future ultralow-power applications. Other than metal deposition, template stripping could provide a general approach to improve thin-film quality for many other types of materials and processes. KEYWORDS: organic field-effect transistor, anodization, template stripping, subthreshold swing, single-crystal, low-power transistor

1. INTRODUCTION The organic field-effect transistor (OFET) devices fabricated based on single-crystalline semiconductors are ideal candidates because they favor the charge transport in the channel region since they are free of grain boundaries, and they provide a nearly defect-free semiconductor/dielectric interface. Singlecrystal OFET devices have demonstrated high performance with field-effect mobility exceeding 10 cm2/(V s)1−7 and an on/off ratio larger than 108.4,5,8 However, most of these devices are using thermally grown SiO2 dielectrics, and as such, their operating voltage is relatively large. To meet the energy requirement for future portable electronics or self-powered devices, the operating voltage and the overall power consumption of OFETs should be as low as possible. During the transistor operation, charging and discharging the dielectric capacitor contributes the majority of the dynamic power dissipation, and it is proportional to the square of saturation gate voltage.9,10 While the leakage current through the gate dielectric and the channel current at the off state dominate the static power dissipation, the subthreshold swing (SS) of the transistor also plays a critical role in total power consumption because it determines how much gate voltage is necessary to increase the drain−source current by 1 order of magnitude. Due to the thermionic injection nature of FET, the theoretical minimum value of SS at room temperature is 60 mV/decade.11 The application of high-k dielectrics such as HfO2,12 ZrO2,13 BaSrTiO3,14 and AlOx15−22 successfully reduces the power consumption of OFETs because they can turn on the OFET at only a few volts while preventing a severe gate leakage current © XXXX American Chemical Society

at the same time. One of the major fabrication methods for high-k dielectrics is the sol−gel method, a vacuum-free process that provides a high-quality thin film with a surface roughness as low as 0.3 nm, which forms a good dielectric/semiconductor interface. However, the sol−gel method usually involves a hightemperature postannealing process that may limit the selection of flexible substrates. Electrochemical anodization is a promising technique to form a highly uniform, barrier-type, densely packed dielectric thin film such as AlOx and TiOx.20−23 OFETs based on anodized metal oxide dielectrics have been demonstrated for use in transistor memory devices,24 complementary ring oscillators,20 ultraflexible imperceptible tactile sensor arrays,21 large-area temperature sensor array devices,25 and ultralow voltage transistors.23 Compared to the sol−gel method, anodization can be performed at room temperature, but the surface roughness of the dielectric is hard to reach below 1 nm although it exhibits some self-healing during the anodization. The final formed dielectric surface roughness is primarily determined by the quality of the deposited Al or Ti gate electrode. Conventional vacuum depositions without cryogenic substrate cooling, such as thermal evaporation or sputtering, may make it difficult to Special Issue: Materials and Interfaces for Next Generation Thin Film Transistors Received: November 2, 2017 Accepted: February 26, 2018

A

DOI: 10.1021/acsami.7b16658 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces create an ultrasmooth surface (roughness < 1 nm).20 Since the dielectric/semiconductor interface is the most important interface for FET devices, to further explore the potential of the anodization technique, the surface quality of this method must be improved. In this work, we have fabricated a low-voltage OFET device by using single-crystalline 2,6-diphenylanthracene (DPA) as semiconductor and anodized AlOx as the dielectric layer. More importantly, rather than the conventional Al metal deposition process, we optimized the surface roughness of the as-deposited Al gate electrode down to 0.53 nm by applying the “template stripping” method.26 The high-quality AlOx dielectric together with the single-crystalline DPA semiconductor created a nearly defect-free dielectric/semiconductor interface. As a result, the OFET can operate at 3 V with a field-effect mobility of about 1.2 cm2/(V s), and the subthreshold swing of OFET reaches 66 mV/decade, which is very close to the theoretical limitation at room temperature. Both the gate leakage current and off-state channel current are below 1 pA. The steep subthreshold slope and low leakage current of the device enable its usage in future high-speed, low-power electronics. Additionally, the application of the “template stripping” method not only is useful for anodized metal oxide but also may be a general approach to improve thin-film quality for many other types of materials and processes.

2.2. Characterization. Intelligent mode atomic force microscopy (AFM) was performed using a Bruker Dimension Icon. Transmission electron microscope (TEM) and selected-area electron diffraction (SAED) measurements were conducted using a JEOL 2011F TEM. The sample for the cross-section TEM was prepared using a focused ion beam technique. All the electrical characterizations were performed in air by using the Keithley 4200 semiconductor parameter analyzer. The field-effect mobility of OFET at the saturation region is estimated from the transfer I−V based on the following equation

IDS =

W μ Ci(VG − Vth)2 2L FET

(1)

where IDS was the drain−source current and W and L indicate the channel width and length, respectively. The exact values of W and L were obtained from an optical image of the device (Figure S1). μFET is the desired mobility, and VG and Vth refer to the gate and threshold voltages, respectively. Ci is the unit-area capacitance of the dielectric layer, which was obtained based on capacitance-frequency measurement, and the SS value was determined by data fitting using transfer I−V. A small gate voltage sweeping interval of 0.01 V was used to obtain a sufficient number of data points for accurate SS calculation.

3. RESULTS AND DISCUSSION Figure 1 shows the schematic drawing of the template stripping method. The fabrication procedures were described in detail in

2. EXPERIMENTAL SECTION 2.1. Device Fabrication. A heavily doped Si wafer with 300 nm SiO2 was used as a template for Al deposition. The Si wafer went through standard ultrasonic cleaning procedures prior to use. 100 nm Al was then thermally evaporated onto the wafer with a deposition rate larger than 4 nm/s. After deposition, the UV-curable adhesive (optical adhesive, OA) was directly put on the Al surface and pressed using a piece of a glass slide. The sample was then exposed to a UV lamp for 2 h to completely cure the OA. The OA/glass was then mechanically cleaved from the Si wafer, so the ultraflat Al surface was exposed and ready for the next anodization process. The Al electrode on the glass/ OA support was put into a citric acid/sodium citrate-mixed electrolyte for anodization (pH approximately 7). The anodization process comprised two stages. In the first galvanostatic anodization, a constant current of 0.7 mA/cm2 was used. The applied voltage increases linearly due to the increase in thickness of the AlOx, which was approximately 1.4 nm/V. In this work, we set the maximum voltage to be 15 V, so that the final thickness of AlOx was 1.4 × 15 + 2 = 23 nm, in which 2 nm is the native oxide formed before anodization. In the second potentiostatic anodization, the voltage remained constant, but the current dropped exponentially. In this study, the whole process was finished within 5 min when the current dropped to 5% of the initial value. After anodization, the sample was rinsed with deionized water and carefully blown dry under the nitrogen flow. Next, the sample was immersed in a 5 × 10−3 M tetradecylphosphonic acid (TDPA) solution (with 2-propanol as the solvent) for 1 h to form the selfassembled monolayer (SAM) on the AlOx surface. To finish the OFET device fabrication, the physical vapor transport (PVT) method was employed to grow high-quality DPA crystals. The growth parameters adopted a growth temperature of 160 °C with 5 h under 10 Pa. There are two methods to preparing DPA crystals on the AlOx dielectric layer: (1) the DPA crystals were grown in situ on the AlOx dielectric layer and (2) single crystals of DPA were grown first on the SiO2/Si substrate. There is a high probability that the DPA crystal would grow vertically on the substrate. As such, under the assistance of a micromanipulator probe station with a high-resolution microscope, we manually transferred the DPA crystal onto the AlOx dielectric layer. The complete OFET device was finished by transferring “Au strip film” with the shape of 200 × 80 μm in size onto the DPA crystal on the AlOx substrate to act as source/drain contact electrodes.

Figure 1. Schematic drawing of the template stripping method: (i) Si wafer with atomic flat surface is used as template; (ii) Al is thermally evaporated onto the Si wafer; (iii) optical adhesive is directly put onto the Al as adhesion or stand along support; (iv) a piece of glass together with optical adhesive (OA) as support, after solidification of OA, where the support is mechanically cleaved from Si wafer; and (v) the exposed ultraflat Al surface is ready for next-step fabrication. The center is an optical image of ultraflat Al with stand along OA support.

the Experimental Section above. Template stripping was developed for the preparation of ultraflat metal thin film in the study of well-ordered SAMs26 and was applied to highperformance OFET devices in this study. The attached mechanical support may either be OA and a glass slide or a bare OA. After being mechanically peeled off, the latter one can stand alone and acts as a flexible substrate, as shown in the center of Figure 1. On top of the Al electrode, the dielectric layer is then formed by anodization of Al and TDPA SAM treatment. Next, we will characterize the surface quality of Al/ B

DOI: 10.1021/acsami.7b16658 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces AlOx prepared by this method and compare it with conventional thermally evaporated thin films. Figure 2a is the AFM image of thermally evaporated Al on the SiO2 substrate. The best root-mean-square (rms) roughness

Figure 3. (a) Cross-section TEM image of Al/AlOx/SAM deposited onto glass substrate; (b) the cross-section TEM image of Al/AlOx/ SAM deposited based on template stripping method; (c) the zoomedin image of (a), where the interfaces are marked by solid lines; and (d) the zoomed-in image of (b), where the interfaces are marked by solid lines.

comparable to the thickness of AlOx. This relatively rough surface of AlOx inherited from Al morphology may scatter the carriers transported in an OFET device or have a negative influence on the electrical strength of the dielectric. Carbon and Pt coating is deposited for sample preparation. In Figures 3b and 3d, the ultraflat Al attached to the OA support generates AlOx with highly uniform thickness and sharp interfaces. The thickness of AlOx estimated from Figure 3d is 23 nm. Due to the weak contrast and small thickness of the SAM, it cannot be distinguished in the TEM images. The cross-section TEM images together with the AFM results prove that the template stripping method successfully modifies the roughness of the Al electrode and thus guarantees the growth of a high-quality, uniform high-k dielectric. The hybrid dielectric is ready for OFET device fabrication. DPA crystal was selected as the organic semiconductor for our study due to its impressive charge transport ability.1,28 We prepared a well-defined single-crystalline DPA on AlOx dielectric layer by PVT or the “probe-assisted” method.29,30 Figure 4a shows a typical DPA crystal grown on an ultraflat AlOx dielectric layer during PVT growth. The crystals preferentially display a regular geometric shape with a large lateral size. Cross-polarized microscopy exhibits angle-dependent polarized light intensity for the DPA crystal (Figure 4b). With the 45° rotation of the polarization angle, the crystal extinguishes cross-polarized light simultaneously as determined by the ordered crystallographic alignment. The crystallinity, structure information, and growth direction were further investigated by TEM combined with SAED. The SAED pattern shows sharp diffraction spots, demonstrating its highly crystalline nature (Figure 4c). We can index this SAED pattern by lattice parameters from the single-crystal structure: a = 17.973(8) Å, b = 7.352(3) Å, c = 6.245(3) Å, α = γ = 90°, β = 90.646°, and a space group of P21/c. According to the twodimensional layer-type structure of DPA (Figure S3a), zone axes of [001] and [010] were determined as the two growth directions from the SAED pattern. By simulating the growth morphology, the DPA crystal was found to readily crystallize into a two-dimensional hexagonal configuration (Figure S3b). Atomic force microscopy (AFM) topography presents the flat surface and smooth boundary of an as-formed 2D hexagonal

Figure 2. (a) Surface morphology of thermally evaporated Al on Si wafer, and the rms roughness of the image is 1.27 nm; (b) surface morphology of Al made by the template stripping method, and the rms roughness of the image is 0.53 nm; (c) surface morphology of templated stripping Al after anodization, and the rms roughness of the image is 0.67 nm; (d) surface morphology of templated stripping AlOx after SAM treatment, and the rms roughness of the image is 0.92 nm. The scanning area of all the images is 9 μm2.

that we could achieve for the as-deposited Al was 1.28 nm. The grains of Al were clearly observed. By using the template stripping method, the roughness of Al was further reduced to 0.53 nm. Compared to as-deposited Al, there is no apparent peak or valley in the scanning area. The surface morphology of the template stripping Al after anodization and SAM treatment are shown in Figures 2c and 2d, respectively. Although anodization is known as a self-healing process due to the polishing effect, it uses electrolytes to etch away the largest spikes on the Al surface during immersion. It is worth noting that the anodization provides a highly uniform thin film over a large area. In Figure S2, the AlOx exhibits uniform morphology over a 400 μm2 scanning area and has the same rms roughness as is shown in Figure 2c. After SAM treatment, the rms roughness further increases to 0.92 nm, an increment that is mainly attributed to the presence of many small dots on the surface (Figure 2d) and may hurt the device performance or introduce trap states. Those small dots may come from the aggregation of TDPA SAMs. To improve the SAM treatment process, novel methods such as stamp printing could be applied.22,27 The AFM images suggested that the template stripping Al can improve surface morphology compared to the as-deposited method. Although the rms roughness slightly increases after anodization and SAM formation, the overall value is still smaller than 1 nm. We also compared the morphology of the Al/AlOx/SAM hybrid dielectric prepared through different methods by using TEM. Figure 3a is the cross-section TEM image of the Al/ AlOx/SAM hybrid dielectric on a glass substrate, and Figure 3c is the corresponding zoomed-in image. In Figure 3c, the height variation of the AlOx upper surface is around 10 nm, which is C

DOI: 10.1021/acsami.7b16658 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces

Figure 4. DPA crystal growth and characterization. (a) Optical images of individual DPA crystal grown on AlOx dielectric layer. The inset in the image is a schematic chemical structure of the DPA molecule. (b) Cross-polarized optical micrographs of the DPA crystal, and the uniform color change confirms that the DPA crystal is a single crystal. (c) TEM image of individual DPA and its corresponding SAED pattern. (d) AFM image of a hexagonal DPA crystal.

Figure 5. (a) Cross-section TEM image of completed OFET device fabricated based on template stripping method; (b) capacitance-frequency characterization of an Al/AlOx/SAM/Au device, and the area of top Au electrode is 0.042 mm2; (c) leakage current density of an Al/AlOx/SAM/Au device, and the area of top Au electrode is 0.042 mm2. Inset of figure is the schematic drawing of an Al/AlOx/SAM/Au device. (d) Breakdown test of an Al/AlOx/SAM/Au device; (e) transfer I−V of OFET device, where the blue line is the drain−source current, the red line the gate−source current, and the green line the square root of the drain−source current; and (f) zoomed-in drain−source current of OFET at the subthreshold region, where the solid line represents the linear fitting of the data.

of the a-axes (17.793 Å) of the known DPA crystal structure (Figure 4d), suggesting a layer-by-layer growth mode. The completed cross section of the OFET device is shown in Figure 5a. All of the interfaces in the device exhibit negligible height variation over several μm (Figure S4). This device is

crystal (Figure 4d). The thickness was determined to be 27 nm, which was suitable for constructing transistor devices. In addition, the surface of the DPA crystal contains terraced morphology, and the profile of the terraced position reveals a step height of approximately 1.8 nm, consistent with the length D

DOI: 10.1021/acsami.7b16658 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces Table 1. Comparison of the Electrical Characteristics of Recently Reported High-k OFETs dielectric

method

AlOx AlOx/PS AlOx/PS AlOx/SAM AlOx/SAM AlOx/SAM AlOx/SAM TiOx/SAM AlOx/SAM AlOx/SAM AlOx/SAM

sol−gel PEALD ALD oxygen plasma oxygen plasma oxygen plasma anodization anodization anodization anodization anodization

process temperature [°C] 300 110 120 80 80 80 room room room room room

temperature temperature temperature temperature temperature

organic semiconductor

subthreshold swing [mV/dec]

mobility [cm2/(V s)]

on/off ratio

ref

PDVT-8 TESADT C60 C10-DNTT DPh-BTBT N1100 pentacene DNTT DNTT DNTT DPA

65 85 300 68 90 100 230 77 182 145 66

2.41 1.3 2.2 4.3 0.4 0.2 0.47 1.72 3 1.9 1.2

107 106 105 108 106 106 2 × 104 105 107 106 4 × 106

15 16 17 18 19 19 20 23 21 22 this work

stress stability measurement are shown in Figure S6. After a 2000 s VG = −3 V bias stress, the shift of threshold voltage is around −0.3 V. The field-effect mobility is satisfactory but could be further improved. The main reason for the low mobility is the energy misalignment between the work function of Au source−drain electrodes (−5.1 eV) and the highest occupied molecular orbital (HOMO) of DPA (−5.6 eV), which introduces a hole injection barrier at the drain−source contact. The thickness of the organic single crystal is also critical since it affects the contact resistance. The large contact resistance may lower the drain−source current and therefore reduces the effective mobility. Zhang et al. have also demonstrated that the transistors show a strong dependence of effective mobility on the thickness of organic single crystals.7 Other reasons must also be taken into account, such as the broadening of the density of states (DOS) of DPA induced by dipolar disorder in a high-k dielectric.34 Despite the saturation region, the OFET device demonstrated a very steep subthreshold slope. As Figure 5f demonstrates, the SS obtained by data fitting is 66 mV/ decade, which approaches the theoretical limitation of 60 mV/ decade at room temperature. SS can be a direct measurement of interface trap density, which is described as follows11,35

suitable for studying the intrinsic properties of materials because the trap states originating from structural defects can be minimized. We first characterized the electrical properties of the AlOx/SAM hybrid dielectric, and the results are plotted in Figures 5b and 5c. The unit-area capacitance (Ci) of AlOx/SAM is determined by measuring a metal−insulator−metal (MIM) device. Across the sweeping frequency range, Ci remains almost constant at approximately 290 nF/cm2, allowing the transistor to turn on at 3−4 V. The dielectric constant εr of AlOx/SAM is therefore calculated to be 7.54 based on the following equation

Ci =

ε0εr d

(2)

where ε0 is the vacuum permittivity; Ci is the unit-area capacitance; and d is the thickness (23 nm, as shown in Figure 3d). Figure 5c represents the leakage current density through the MIM structure. As a result of the high-quality AlOx and SAM passivation, the hybrid dielectric exhibits an extremely low leakage current density that is slightly larger than 10−9 A/cm2 at 2 MV/cm electric field, which, to our knowledge, is among the best recently reported values among high-k dielectrics.21,23,24,31,32 Normally, for a high-k dielectric, due to the large value of unit-area capacitance, the contribution of the displacement current of the capacitor must be considered while performing the leakage current measurement, which can be described by the following equation33

Idis

dV = ACi dt

SS = ln(10)

2 kT ⎛ Ci + q Dit ⎞ ⎜ ⎟ q ⎝ Ci ⎠

(4)

where Dit is the interface trap state density; k is the Boltzmann constant; T is the absolute temperature; and q is the elementary charge. Dit in this work is 1.81 × 1011/cm2·eV. The combination of the organic single crystal, the ultraflat dielectric surface, and the high unit−area capacitance is responsible for the low interface trap density and the steep SS. We compared recently reported organic transistors based on various fabrication techniques with emphasis on SS performance in Table 1. To the best of our knowledge, the SS in this work is among the best of the reported OFETs, and though AlOx prepared by the sol−gel method gives a steeper SS of 65 mV/ decade,15 this may be attributed to the smoother surface of AlOx (rms roughness of approximately 0.3 nm). However, this method requires 300 °C postannealing. Suppression of SS plays a critical role in reducing the total power dissipation of a working transistor. In an integrated circuit, if Vth of the transistor is too close to 0 V, the channel cannot turn completely off at VGS = 0 V with a poor SS, resulting in a relatively large off-state current and large static power consumption.11 The strategy to further reduce the SS based on eq 4 could be continuing to optimize the interface trap state density by SAM passivation or to increase the unit−area

(3)

where Idis is the displacement current of the capacitor; A is the area of top contact electrode; and dV/dt is the voltage sweeping rate. To determine the displacement current density jdis, A from eq 3 is normalized. For the current MIM device, in order to suppress jdis down to a reasonably small value (