Modulating the Interface Chemistry and Electrical Properties of

Jul 5, 2019 - Figure 1b shows the As 3d XPS spectra for S1, S2, and S3 samples as ... Compared with S1 and S3, there is a slight shift of the Hf 4f pe...
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Article Cite This: ACS Omega 2019, 4, 11663−11672

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Modulating the Interface Chemistry and Electrical Properties of Sputtering-Driven HfYO/GaAs Gate Stacks by ALD Pulse Cycles and Thermal Treatment Shuang Liang,† Gang He,*,†,‡ Die Wang,† Lin Hao,† Miao Zhang,† and Jingbiao Cui§

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†

School of Physics and Materials Science, Radiation Detection Materials & Devices Lab, Anhui University, Hefei 230039, P. R. China ‡ Institute of Physical Science and Information Technology, Anhui University, Hefei 230601, P. R. China § Department of Physics and Materials Science, The University of Memphis, Memphis, Tennessee 38152, United States S Supporting Information *

ABSTRACT: In the current work, a detailed exploration on the cleaning effect of intrinsic oxide existing at the GaAs/ HfYO interface by using an atomic-layer-deposition-derived trimethylaluminum (ALD TMA) precursor as functions of TMA pulse cycles and postannealing temperature has been evaluated via X-ray photoemission spectroscopy (XPS) measurements and electrical characterization. According to XPS analyses, it can be noted that the intrinsic As oxides, Ga oxides, and As0 are effectively reduced from the HYO/GaAs gate stack after ALD TMA treatment with 20 pulse cycles. Meanwhile, optimized electrical parameters, such as the largest permittivity (k), the lowest hysteresis, and the minimum leakage density (Jg), have also been obtained for the HfYO/GaAs gate stack with 20 pulse cycles of ALD TMA. Based on the optimized pulse cycles of 20 ALD TMA, postannealing temperature-dependent interface quality and electrical performance of GaAs-based devices based on the HfYO/GaAs gate stack have also been investigated. The HfYO/GaAs/Al metal-oxide semiconductor capacitor annealed at 300 °C with optimized pulse cycles of 20 displays the greatest dielectric constant of 38, the minimum Jg of 3.28 × 10−6 A cm−2, and a small hysteresis of 0.01 V. Meanwhile, the leakage current transport mechanism at low temperature (77−327 K) has been discussed systematically. decrease the speed of the CMOS devices.10 As a result, III−V compound semiconductors with high mobility are being investigated as one of the promising technology boosters to enhance MOSFET performance. Among III−V semiconductors, more attention has been paid to the investigation of GaAs-based channel materials for continuing the scaling of MOSFETs devices due to its larger band gap, higher breakdown field, and higher carrier mobility than other candidates.11−13 However, due to the existence of native oxides, GaAs are likely to form extrinsic defects attributed to the high interface state density (Dit). The high Dit associated with the dielectric/III−V interface causes Fermi-level pinning at the midgap and large capacitance frequency dispersion, which leads to the degraded electrical performance.14,15 Additionally, the oxygen atoms in high-k gate dielectrics can diffuse easily into the substrate, leading to the formation of a low-k interfacial layer and increased oxygen vacancies between high-k and the GaAs substrate. It is reported that the existing

1. INTRODUCTION With the development of Si-based integrated circuits, the traditional SiO2-based complementary metal-oxide-semiconductor field effect transistor (CMOSFET) devices have reached limited scaling. Thus, much efforts have been devoted to the investigation of HfO2-based high-k gate dielectrics due to its wide band gap, high refractive index, high thermal stability, and excellent chemical properties.1−5 However, lower crystallization temperature and smaller permittivity make it incompatible for future high-performance CMOS devices. To increase the dielectric constant and the crystallization temperature, rare earth elements, such as Y, Dy, and Gd, have been incorporated into HfO2, and some optimized performance has been observed.6−8 Based on our previous publication, it has been detected that incorporating Y into HfO2 can increase the crystallization temperature and decrease oxygen vacancies as well as reduce the interfacial defects, therefore reducing the leakage current and improving the dielectric interfacial quality.9 However, due to the introduction of high-k gate dielectrics, the electron mobility of MOSFET devices degrades inevitably, resulting from the influence of the Coulomb and phonon scatterings at the interface, which would definitively © 2019 American Chemical Society

Received: May 10, 2019 Accepted: June 19, 2019 Published: July 5, 2019 11663

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Figure 1. Ga 2p (a), As 3d (b), and O 1s (c) XPS spectra of S1, S2, and S3 as a function of TMA pulse cycles.

HYO deposition. Postdeposition annealing (PDA) under a vacuum atmosphere for Al/HYO/TMA/GaAs MOS devices was performed to obtain the preferable electrical properties. The effect of different pulse cycles of the ALD TMA precursor and postdeposition annealing temperature on the interface chemistry and electrical properties of HYO/TMA/GaAs gate stacks has been investigated systematically.

native oxides (As2O3, As2O5, Ga2O3) and element of As on the GaAs surface directly attribute to the higher Dit.16 To realize GaAs-based MOSFETs with high performance, passivating the interface chemistry of GaAs before high-k gate dielectrics deposition has been recently investigated to overcome fermilevel pinning. Recently, numerous surface-passivation methods for III−V substrates upon gate stack deposition, including chemical cleaning, deposition of the interfacial passivation layer, and nitridation treatment, have been adopted and proved to control and reduce the GaAs interfacial intrinsic oxides. For chemical cleaning treatment, diluted hydrofluoric acid, ammonia, and sulfur ammonia solutions have been used, and dangling bonds of the GaAs surface will be passivated effectively, reducing the possibility of oxygen adsorbing on the substrate surface.16,17 By introducing the interfacial passivation layer, improved interface quality at the high-k/ GaAs interface has been detected.18−21 Several studies have investigated the interface chemistry of III−V semiconductors passivated by atomic-layer deposition (ALD) precursors and demonstrated improved performance. As one of the ALD precursors, trimethylaluminum (TMA) is reactive and can eliminate the native oxides by the self-cleaning (SC) effect.22−26 On the basis of the previous observations, it can be seen that the first interaction on the surface of GaAs by TMA passivation is not self-limiting but self-cleaning effects, which can remove the native oxides. In some investigations, it was observed that after the first ALD cycle, the surface interaction stops and the formation of a 1 nm-thick Al2O3 passivation layer was detected.27−29 By calculation, ligandexchange and charge-transfer routes have been confirmed to be effective to remove GaAs surface arsenic oxide.30 In addition, by placing the GaAs substrate under a nitrogen or ammonia atmosphere and annealing to form the interfacial passivation layer, nitridation treatment would usefully restrain further oxidation of the GaAs substrate.31,32 In the current work, Y-doped HfO2 (HYO) gate dielectrics has been selected to reduce the oxygen vacancies and suppress the leakage density. Since sulfur passivation has been proved to be effective in controlling the interface chemistry,33,34 combining sulfur passivation and other passivation methods can be a great choice. In the current work, to reduce the interface native oxide and prevent oxidation as well as to decrease the surface defect density, GaAs wafers were passivated by diluted HBr and (NH4)2S solutions. Then, different cycles of TMA were introduced to passivate the GaAs substrate and decrease the surface mutual diffusion. Finally, the as-processed wafers were transferred to the chamber system for

2. RESULTS AND DISCUSSION 2.1. Interface Chemistry Analyses of HYO/TMA/GaAs Gate Stacks. X-ray photoemission spectroscopy (XPS) characterizations were performed to analyze the interface chemistry of HYO/TMA/GaAs gate stacks with different TMA pulse cycles. All of the collected XPS data were calibrated accurately by a C 1s peak (284.6 eV). Figure S1 displays the survey spectra of S1, S2, and S3 samples with the binding energy ranging from 0 to 1300 eV, where S1, S2, and S3 refer to 15, 20, and 25 TMA pulse cycles of the TMA precursor, respectively. As shown in Figure S1a, only Hf, Y, O, Ga, As, and C are observed, suggesting that the films are free of some other impurities and that HYO gate dielectrics has been obtained successfully. However, the Al component is not observed from the survey spectra owing to its low concentration. Figure S1b presents the high-resolution Al 2p spectra clearly as a function of the TMA pulse cycle. Based on Figure S1b, it can be seen that Al exists in all of the samples. Moreover, the Al 2p XPS peak centered at 74 eV has been observed, representing the formation of the Al2O3 passivation layer, and the slight increase of the Al 2p peak intensity is accompanied with the increase of TMA pulse cycles. As a result, it can be concluded that the generation of Al-related compounds has been proved by ALD TMA pretreatment on the surface of GaAs. To evaluate the cleaning effect of the ALD TMA precursor, the interface chemistry of HYO/GaAs gate stacks as a function of TMA pulse cycles has been investigated systematically. Figure 1 demonstrates the Ga 2p and As 3d XPS spectra for three samples by measuring the HYO/TMA/GaAs gate stacks each. The displayed Ga 2p XPS spectra in Figure 1a are decomposed into four peaks centered at binding energies of 1117.68, 1118.01, 1118.58, and 1119.17 eV, which can be attributed to Ga−As, Ga−S, Ga2O, and Ga2O3 bonding states, respectively. For three samples, no obvious change in the intensities of the Ga−S bond has been observed after TMA treatment. However, it can be obviously seen that the Ga oxides’ peak intensities of sample S2 (20 cycles of TMA) have a substantial reduction and those of samples S1 and S3 with 15 11664

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1c displays TMA-pulse-cycle-dependent O 1s XPS spectra of the three samples. Four fitted subpeaks, attributed to Hf−Y− O, Al−O, Ga−O, and As−O components, are detected for all of the samples. The same reduction trend in Ga−O and As−O intensities is also observed for the S2 sample, suggesting the suppressed growth of the interfacial layer. Therefore, it can be inferred that a suitable TMA pulse cycle can make the scavenging effect on As or Ga oxides. As shown in Figure 2, the Hf 4f and Y 3d XPS spectra of three samples have been investigated as a function of TMA

and 25 TMA pulse cycles increase relatively, which mainly results from the fact that the ALD TMA precursor with 20 pulse cycles can suppress the formation of Ga oxides. Thus, the self-cleaning (SC) effect with respect to the reduction in Ga oxides during 20 TMA pulse cycles has been detected clearly, which can be attributed to the ligand-exchange reaction between the metal precursor and native oxides. According to our previous investigation, it can be concluded that the reduction in Ga−O bonds can be explained by the following chemical reaction35,36 Al(CH3)3 + Ga 2O3 → Al 2O3 + 2Ga(CH3)3 ↑

(1)

The TMA precursor depletes part of gallium oxides and leads to the production of some volatile substances. If the supplied TMA precursor is not enough, much more gallium oxides still exist on the surface of GaAs due to the inadequate ligandexchange reaction. When the pulse cycles for TMA increase from 20 to 25, the observed increase in Ga oxides can be due to the conversion of As oxides into Ga oxides described by the following possible chemical reaction mechanism As 2 O3(s) + 2GaAs(s) → Ga 2O3 + 4As

(2)

As 2 O3(s) + 6GaAs(s) → 3Ga 2O(s) + 8As↑

(3)

This abovementioned thermal conversion is conductive to the further accumulation of GaOx on the surface of GaAs. As a result, it provides sufficient energy for the underlying Ga species to diffuse through the AlOx overlayer formed between TMA and native oxides. Figure 1b shows the As 3d XPS spectra for S1, S2, and S3 samples as functions of TMA pulse cycles. The six deconvoluted peaks are represented as Hf 5p1/2 (∼39.11 eV), As−Ga (∼40.10 eV), As0 (∼41.06 eV), As1+ (As2O, ∼43.61 eV), As3+ (As2O3, ∼44.57 eV), and As5+ (As2O5, ∼45.39 eV). It is observed that the intensities of As0, As1+, As3+, and As5+ oxides reduce from S1 to S2 and increase from S2 to S3, indicating a similar trend with Ga 2p XPS spectra. It is obvious that ALD TMA with the SC effect also helps reduce AsOx and As0 and suppress these intrinsic impurities effectively. Peculiarly, the 20 TMA pulse cycles have an obvious scavenging effect on As0 and arsenic oxides compared with 15 and 25 pulse cycles. In addition, due to the high affinity of Ga−O bonds, more As−As bonds are formed on the surface. On the basis of the ligand-exchange theory, arsenic oxides react with TMA following the formula Al(CH3)3 + As 2 O3 → Al 2O3 + As(CH3)3 ↑

Figure 2. Hf 4f (a) and Y 3d (b) XPS spectra of S1, S2, and S3 samples as a function of TMA pulse cycles.

pulse cycles. For Hf 4f XPS spectra demonstrated in Figure 2a, typical Hf 4f XPS spectra with spin−orbit doublets have been found for all of the samples. Compared with S1 and S3, there is a slight shift of the Hf 4f peak to the lower binding energy for the S2 sample, and the same trend has happened to Y 3d XPS spectra shown in Figure 2b, which can be attributed to the difference of the atom radius between Y and Hf elements and the change in the chemical state of Hf and Y elements. In addition, the shift in binding energies of Hf 4f and Y 3d spectra related to the TMA pulse cycles indicates that Fermi-level shifting toward a flat band condition occurs.39 On account of the XPS investigations, it can be concluded that the arsenic oxide, element arsenic, and gallium oxide can be fruitfully reduced on the HYO/GaAs interface while introducing 20 pulse cycles in the ALD TMA precursor. 2.2. Electrical Properties of HYO/TMA/GaAs Gate Stacks. The double-sweep C−V typical characteristic curves for Al/HYO/GaAs capacitors as a function of TMA pulse cycles measured at high frequency are shown in Figure 3a. As we know, the effect from the interface state of the MOS capacitor can be avoided by measuring the C−V curves at high

(4)

10Al(CH3)3 + 6As 2 O5 → 5Al 2O3 + 12As0(3As4 ) ↑ + 15C2H6↑ 3+

(5)

5+

which can reduce As and As and create volatile gases. For short TMA pulse cycles, some native oxides covering the surface of GaAs will be consumed via the ligand-exchange reaction. One of the possible mechanisms of the SC effect is the reaction of TMA with diffused Ga and As species, and this process continues until these native oxides can no longer be available.37,38 This may be one of the important factors to understand the ALD TMA SC mechanism for a GaAs surface processed by only TMA pulse cycles but without water or oxygen. For longer TMA pulse cycles, the formed Al2O3 prevents the consumption of As oxides, and only suitable Al2O3-layer thickness is beneficial to the GaAs surface. Figure

Figure 3. (a) Capacitance−voltage (C−V) characteristics of S1, S2, and S3; (b) leakage current density−gate voltage (J−V) characteristics of S1, S2, and S3. 11665

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Table 1. Parameters of S1, S2, and S3 MOS Capacitors Extracted from C−V and J−V Curves samples S1 S2 S3

K 36.1 38.3 36.7

Cox (pF) 870.5 910.6 877.8

Vfb (V) 1.91 1.35 1.80

ΔVfb (V)

Qox (cm−2)

Nbt (cm−2)

J (A cm−2)

0.06 0.02 0.04

−3.25 × 10 −2.39 × 1013 −3.09 × 1013

−1.04 × 10 −3.62 × 1011 −6.99 × 1011

6.87 × 10−5 4.20 × 10−5 2.3 × 10−3

13

12

Figure 4. As 3d (a), Ga 2p (b), and O 1s (c) XPS spectra of S2, S4, S5, and S6 as a function of annealing temperature.

frequency (1 MHz).30 From Figure 3a, it can be seen that compared with S1 and S3, a higher accumulation capacitance (Cox) and good saturation region have been observed for the S2 sample, indicating the improved interface quality and the reduction of Ga/As oxides when using 20 TMA pulse cycles. Due to the existing SC effect for the ALD TMA precursor, the formed Al2O3 passivation layer with the blocking role will prevent the diffusion of Ga/As oxides and suppress the formation of the interface layer on the GaAs surface. In addition, the smaller and negligible hysteresis voltage (ΔVfb) than those of S1 and S3 has been detected for the S2 sample, implying fewer slow states in the dielectric and near/at the interface due to the reduction of Ga and As oxides in the S2 sample with 20 TMA pulse cycles. The dielectric constants (k) are calculated to be 36.1, 38.3, and 36.7 for S1, S2, and S3 samples, respectively. It can be seen that with the increase in the ALD TMA pulse cycle from 15 to 20, an obvious increased dielectric constant was observed, which can be attributed to the reduction of gallium and arsenic oxides and the suppressed low-k layer. However, there is a slight reduction in k for the S3 sample, which results from the formation of a low-k Al2O3 passivation layer. The extracted flat band voltage (Vfb) values are 1.91, 1.35, and 1.80 V for S1, S2, and S3 samples, respectively. The shift in Vfb toward the positive direction implies the existence of negative oxide charges in HYO films and the introduced electronegative S2− from the (NH4)2S passivation solution. It can be seen that after TMA pretreatment with different pulse cycles, C−V curves for S1 and S2 have negative shifting in Vfb compared with S1, which can result from the reduced oxygen vacancies or the negative charges at the interface layer. For S2, the observed smallest ΔVfb of 0.02 V can be attributed to the less oxygen vacancies in the gate dielectrics. As a result, it can be inferred that S2 with the 20 TMA pulse cycle can delay the oxygen diffusion and suppress the formation of oxygen vacancies, leading to the reduced Vfb. The oxide charge densities (Qox) are calculated to be −3.25 × 1013, −2.39 × 1013, and −3.09 × 1013 for S1, S2, and S3 samples, respectively. All of the extracted electrical

parameters are listed in Table 1. The smallest Qox for S2 implies the least negative oxide charges, which originates from the least oxygen vacancies in HYO thin films. Based on Table 1, it can be noted that compared with S1 and S3, the border trapped oxide charge density (Nbt) for S2 has a significant decrease, which is attributed to the suppressed Ga and As diffusion. Meanwhile, the reduced Nbt also results in the reduced ΔVfb. The leakage current density (J) via applied bias voltage (V) for three samples is plotted in Figure 3b. The observed larger leakage current in the S1 sample comes from the larger trapped charges and the larger interface state density. After exposing ALD TMA with 20 pulse cycles for the S2 sample, the reduction in leakage current was detected, which can be attributed to the reduced trapped charges and oxide charges in the interface layer, associated with the reduction of Ga/As oxides and As elements at/near the HYO/GaAs interface after TMA passivation. However, for the S3 sample, an apparent increase in the leakage current was observed, indicating the degraded interface quality. As a result, it can be noted that ALD TMA with 20 pulse cycles can more effectively reduce the interface state density and improve the interface quality. However, to achieve the optimized electrical performance, further investigation is still needed. 2.3. Interface Optimization of HYO/TMA/GaAs Gate Stacks by Annealing. To investigate the evolution of the interface stability of HYO/TMA/GaAs gate stacks as a function of postdeposition annealing (PDA) temperature, XPS measurements were also performed, and more detailed interfacial information has been obtained. Figure 4 displays the annealing-temperature-dependent As 3d, Ga 2p, and O 1s XPS spectra for the HYO/TMA/GaAs gate stack. From Figure 4a, the intensities of the As−As bond and As5+ peaks for the S4 sample lower than other samples have been observed, indicating that As0 and As5+ have been reduced. With the increase in annealing temperature, the As oxide content saw an increased tendency, which will lead to the Fermi-level pinning effect at high annealing temperatures over 300 °C.40 The same 11666

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Figure 5. Determination of VBM (a) and band gaps (b) for S2, S4, S5, and S6.

trend has been detected from the evolution of Ga 2p and O 1s XPS spectra, shown in Figure 4b,c, suggesting that annealing at 300 °C suppresses the regrowth of Ga/As oxides, and the optimized interface chemistry indicates its potential application in CMOS devices. 2.4. Band Alignment Modulation by Annealing. As a candidate of high-k gate oxides in CMOS devices, the suitable band offset (BO) between the oxide and the semiconductor substrate plays an important role. It is critical to obtain MOSFETs devices with excellent performance by using a highk gate oxide with BO larger than 1 eV to inhibit the flow of electrons from the semiconductor to the metal. The monitored offsets in the valence-band spectra can be used to draw the energy-band alignment for HYO and the GaAs substrate. Based on the model proposed by Kraut,41 the valence-band offset (ΔEv) values of HYO/GaAs gate stacks as a function of annealing temperature are calculated by using the following equation ΔEv(HYO‐GaAs) = Ev (HYO) − Ev (GaAs)

Figure 6. Schematic band diagram of the HYO films for S2, S4, S5, and S6.

(6)

Ev is the valence-band edge determined by the linear epitaxial method displayed in Figure 5a. By linear extrapolation, the Ev of GaAs is calculated to be 0.36 eV. The ΔEv values of S2, S4, S5, and S6 are 1.65, 1.53, 1.91, and 1.99 eV, respectively. Based on Figure 5a, it can be noted that increased ΔEv has been observed with the increase in the annealing temperature, which may originate from the existing native oxides at the high-k/ III−V interface.32 For S4, the reduction in ΔEv can be attributed to the reduced intrinsic oxides existing at the HYO/ GaAs interface after processing by the ALD TMA precursor and the optimized annealing temperature. The conduction band offset (ΔEC) at the HYO/GaAs interface can be calculated by the following equation

°C annealing temperature is suitable for MOS devices with high performance. 2.5. Modulation of Electrical Properties by Rapid Thermal Annealing. To optimize the electrical properties of the HYO/TMA/GaAs gate stack with 20 pulsing cycles, PDA was carried out with the annealing temperature ranging from 300 to 500 °C. Figure 7a shows the annealing-temperaturedependent C−V characteristics of Al/HYO/TMA/GaAs MOS capacitors measured at 1 MHz. The extracted electrical parameters are listed in Table 2. Compared with S2, it can be seen that the S4 sample annealed at 300 °C demonstrates optimized C−V behavior with ignorable ΔVfb, including the suitable dielectric constant of 36, a larger slope in the depletion

ΔEC(HYO‐GaAs) = Eg (HYO) − ΔEv (HYO‐GaAs) − Eg (GaAs)

(7)

Band gaps (Eg) of all samples deposited on quartz substrates were determined by a UV−vis spectroscope and are shown in Figure 5b. The ΔEC values for all of the samples are calculated to be 2.10, 2.43, 1.98, and 1.83 eV. Figure 6 shows a schematic diagram of energy-band alignment for S2, S4, S5, and S6 samples. Apparently, reduction in ΔEC was observed with increased annealing temperature, which is due to the increased native oxides at the HYO/GaAs interface. For the S4 sample, the calculated ΔEv and ΔEC are larger than 1 eV, suggesting that HYO/TMA/GaAs pretreated by 20 pulse cycles and 300

Figure 7. (a) Capacitance−voltage (C−V) and (b) leakage current density−gate voltage (J−V) characteristic curves for S2, S4, S5, and S6. 11667

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Table 2. Parameters of S2, S4, S5, and S6 MOS Capacitors Extracted from C−V and J−V Curves samples S2 S4 S5 S6

K 38.3 36.0 35.7 21.0

Cox (pF) 910.6 858.2 858.0 506.8

Vfb (V) 1.35 0.94 1.84 2.17

ΔVfb (V) 0.02 0.002 0.07 0.14

regime, and the smallest ΔVfb of 0.002, which may be attributed to the optimized interface chemistry. With the increase in annealing temperature, increased ΔVfb and reduced accumulation capacitance have been observed, which may be attributed to the increased density of the interface state caused by a considerable amount of As−O, As−As, and Ga−O chemical bonding states at the GaAs/HfYO interface. As we know, the positive shift in Vfb indicates the existence of negative oxide charges in the dielectrics. Compared with other samples, a smaller positive Vfb shift has been observed in the S4 sample, implying the presence of less negative oxide charges and optimized interface quality. Figure 7b shows the annealing-temperature-dependent leakage current characteristics. It can be seen that the smallest leakage current density of 3.55 × 10−6 A cm−2 for the S4 sample has been observed, which mainly can be due to the reduced border trap charges and interface states. However, on increasing the annealing temperature from 400 to 500 °C, increased leakage current has been detected, which may come from the interface trap-assisted tunneling because of the high interface states existing at the HYO/GaAs interface. As a result, it can be concluded that annealing the HYO/TMA/GaAs gate stack with an appropriate temperature effectively prevents the formation of a low-k interfacial layer and contributes to the reduced oxygen-vacancy-related interface states or the increased ΔEC, leading to the reduced trap-assisted tunneling current. Figure 8 shows the C−V characteristics of Al/HYO/TMA/ GaAs MOS capacitors with frequencies ranging from 1 to 0.6 MHz. It can be seen that the frequency dispersion in the accumulation region is more prominent for S2, S5, and S6, which can result from the higher interface state density. For the S4 sample, the C−V curve exhibits a smaller frequency dispersion at the accumulation region, indicating the lower

Qox (cm−2) −2.39 −1.53 −3.09 −2.15

× × × ×

13

10 1013 1013 1013

Nbt (cm−2) −3.62 −3.41 −1.19 −1.41

× × × ×

11

10 1010 1012 1012

J (A cm−2) 4.20 3.55 2.30 7.19

× × × ×

10−5 10−6 10−4 10−3

density of interface states after 300 °C heat treatment. Following the percentage frequency dispersion formula defined as [C0.6M/C1M − 1] × 100%, frequency dispersions are calculated to be 20.1, 7.5, 17.0, and 40% for S2, S4, S5, and S5, respectively. Apparently, the evolution of the frequency dispersion related to the annealing temperature agrees with the XPS results and electrical measurements. The presence and formation of interfacial Ga/As oxides for HYO/TMA/GaAs processed with annealing treatment produce associated high trap density and contribute to the larger frequency dispersion, leading to the deteriorated electrical performance. 2.6. Current Transport Mechanism Analysis. To analyze the leakage current conduction behaviors of the 300 °C-annealed Al/HYO/TMA/GaAs MOS capacitor, the temperature-dependent gate leakage current has been extensively investigated in the current work. Figure 9 plots the J−V

Figure 9. Low-temperature leakage current characteristics of the S4 sample with the temperature ranging from 77 to 327 K.

characteristics for the 300 °C-annealed MOS capacitor with the measured temperature ranging from 77 to 327 K. From Figure 9, it can be seen that under the same absolute voltage, the leakage current density under gate injection is much larger than that under substrate injection, which is due to the different energy bands under different injection modes. The values of leakage current density for different temperatures (77−327 K) are determined to be 1.49 × 10−7, 2.96 × 10−7, 6.89 × 10−7, 8.67 × 10−7, 3.17 × 10−5, and 3.4 × 10−4 A cm−2 at a gate voltage of 2 V. The lowest leakage current density was observed for the 77 K-processed sample. With the increased processing temperature, the leakage current density demonstrates an increased trend, which may result from the transformation of the current conduction mechanism (CCM) with various temperatures. It is known that the CCM of MOS devices mainly includes Poole−Frenkel (PF) emission, Fowler−Nordheim (FN) tunneling, and Schottky emission (SE). In the current work, various types of CCM through gate oxides will be presented under gate injection and substrate injection modes. Poole−Frenkel (PF) emission involves a mechanism that is similar to Schottky emission, namely, the thermal excitation of electrons may emit from traps into the conduction band of the dielectric layer. Therefore, PF emission is sometimes called the

Figure 8. Frequency-dependent capacitance−voltage (C−V) characteristics curves for S2 (a), S4 (b), S5 (c), and S6 (d). 11668

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Figure 10. PF emission plots for the S4 MOS capacitor under (a) substrate injection and (b) gate injection.

where A* is the effective Richardson constant, φB is barrier height, εr is the vacuum permittivity constant, εo is the optical dielectric constant, kB is the Boltzmann constant, m0 is the free electron mass, and m*ox is the electron effective mass. Figure 11

internal Schottky emission. Considering an electron in a trapping center, the Coulomb potential energy of the electron can be reduced by an applied electric field crossing the dielectric film. For PF emission, the leakage current and electric field (E) should satisfy the following relational expression ÄÅ É ÅÅ −q(ϕ − qE /πε ε ) ÑÑÑ ÅÅ ÑÑ o ox t JPF = (qμNC)E expÅÅ ÑÑÑ ÅÅ kBT ÑÑÑ ÅÅÇ (8) Ö where μ is the electronic drift mobility, NC is the density of states in the conduction band, kB is the Boltzmann constant, ϕt is the trap energy level, and εox is the oxide dielectric constant. The In(J/E) vs E1/2 are plotted in Figure 10a,b under substrate injection and gate injection at different temperatures. The εox can be calculated from the slope of curve slope =

q3/πεox kBT

Figure 11. SE emission plots for the S4 MOS capacitor under gate injection.

(9)

The extracted εox values are in agreement with the previous results obtained from C−V curves and demonstrate a decreased tendency with the increase of the measured temperature. Therefore, it can be concluded that the dominant CCM is governed by PF emission for substrate injection at 277−327 K in the lower electric field (0.36−1.21 MV cm−1) and for gate injection at 177−377 K in the medium electric field (1.66−2.01 MV cm−1). The trap energy-level values (ϕt) can be calculated by the following formula: intercept = ln C −

qϕt kBT

shows the ln(J/T2) versus E1/2 plots measured at 77−277 K at the medium field region (1.69−2.01 MV cm−1) under gate injection. The slopes of the SE plots can be expressed as slope = 1/kT q3/4πε0εopt

where εopt and the refractive index n = εopt have been determined and are shown in Figure 11. It is apparent that the n values measured at 77 and 127 K deviate from the reported results and agree with the reported results at 177− 277 K,42 suggesting that SE emission dominates the CCMs under gate injection in the medium field region. The intercept of the linear fitting lines is related to the m*ox and φB and can be expressed as intercept = ln 120(mox * /m0) − qφB/kT. Combined with FN-induced CCM, mox * and φB can be determined. FN tunneling follows the CCM of carriers passing through the insulating layer in a large electric field, which is a quantum mechanical effect of the electron wave-function penetrating barrier. Therefore, FN tunneling is independent of temperature, which can be expressed as the following formula ÄÅ É ÅÅ 4 2m * φ 3/2 ÑÑÑ ÅÅ q3E2 T B Ñ ÑÑ ln(JFN ) = expÅÅÅ− ÑÑÑ 2 Å 3 η qE 16π ηϕox ÅÅ ÑÑ (13) ÅÇ ÑÖ

. It can be noted that the ϕt value

under substrate injection is smaller than that under gate injection. Under gate injection, more energy is needed for the thermally excited electrons crossing the trap level, indicating that the leakage current under positive voltage is lower than that under negative voltage. The carrier transportation of Schottky emission results from thermionic emission while the electrons gain enough energy and cause leakage current. The SE emission mechanism can be expressed by the following formula ÄÅ É ÅÅ −q(φ − qE /4πε ε ) ÑÑÑ ÅÅ r 0 Ñ 2 B ÑÑ JSE = A*T expÅÅ ÑÑ ÅÅ k T ÑÑÑ B ÅÅÇ (10) Ö A* =

* 4πqkB 2mox 3

h

= 120

* mox m0

(12)

where mT* is the tunneling effective mass in the HYO film. In the current work, mT* = mo* has been assumed. If FN tunneling

(11) 11669

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dominates the CCM, ln(J/E2) versus 1/E should be plotted linearly. Figure 12 displays ln(J/E2) versus 1/E under negative

current density. Based on the optimized pulse cycles of 20 ALD TMA, postannealing-temperature-dependent interface chemistry and electrical properties of the HYO/GaAs gate stack have been investigated. It can be seen that As0, As5+, and Ga−O chemical states from the HYO/GaAs interface are reduced obviously after 300 °C-annealing treatment. Meanwhile, the optimized electrical performance, including the greatest dielectric constant of 38, the minimum leakage current density of 3.28 × 10−6 A cm−2, and the smallest hysteresis of 0.01 V, was achieved for the 300 °C-annealed GaAs-based MOS capacitor. The leakage current mechanism analyses measured at low temperature have demonstrated that PF emission is dominant at 277−327 K in the lower electric field (substrate injection) and at 77−377 K in the medium electric field (gate injection); SE emission mainly conducts from 177 to 227 K in the medium electric field. In the higher electric field with the temperature ranging from 77 to 327 K, FN tunneling dominates the transportation mechanism. As a result, it can be concluded that the HYO/GaAs gate stack with optimized pulse cycles of 20 ALD TMA and modulated annealing temperature of 300 °C displays potential application as high-k gate dielectrics candidates in future III−V electronics.

Figure 12. FN tunneling plots for the S4 MOS capacitor under gate injection.

bias in a higher electric field (2.94−4.16 MV cm−1) with the temperature changing from 77 to 327 K, implying that the CCM is dominated by FN emission under gate injection in the medium field region. The slope of the fitted linear line can be expressed as slope = −6.83 × 107 (m T* m0)φ 3 . Combined B

4. EXPERIMENTAL DETAILS 4.1. Sample Preparation and Device Fabrication. In the current work, commercially purchased n-type GaAs wafers with a resistivity of (1.2−1.6) × 10−3 Ω·cm were chosen as the substrates. First, to remove some organic compounds on the surface of the wafers, the GaAs wafers were ultrasonically degreased using acetone, methanol, and isopropanol for 5 min at room temperature. Then, the GaAs wafers were dipped in a HBr solution (HBr/H2O = 1:10) for about 5 min for removing native oxides. After that, the wafers were immersed in an (NH4)2S solution for about 20 min at 50 °C to passivate the surface of the wafers. Following the above steps, the wafers were rinsed by deionized water and blown by N2. After that, these processed wafers were put into an ALD (LabNano 9100, ENSURENANOTECH) chamber and passivated by the TMA precursor. During the experiment, different TMA pulse cycles (15, 20, 25) consisting of TMA (0.02 s)/N2 (8 s) pulses at 200 °C were carried out (denoted samples S1, S2, and S3). Subsequently, these prepared GaAs wafers were transferred into a sputtering chamber (JSD 400, JiaShuo Vacuum Technology Co. Ltd.) immediately. HYO thin films were obtained by cosputtering 99.9% Y metal target and 99.995% HfO2 ceramic target. Radio frequency power and direct current power were set at 4 and 70 W, respectively; the specific atomic ratio of Hf/Y in the HYO films is about 4:1. Moreover, the base pressure and deposition pressure were maintained at 3.5 × 10−4 and 0.5 Pa, respectively, with the mixture ambient of Ar (30 SCCM) and O2 (2 SCCM). 4.2. Device Fabrication and Characterization. To obtain the interface chemistry of HfYO/GaAs gate stacks, about 4 nm-thick HYO films measured by a spectroscopy ellipsometer (SE, SC630, SANCO Co, Shanghai) were prepared for X-ray photoelectron spectroscopy measurements (XPS, ESCALAB 250Xi Thermo Scientific). In the current work, the films were measured by SE in the range of 300−1100 nm with 65 and 70° angles of incidence. During measurements, the Cauchy−Urbach model was selected to fit the experimental data. To fabricate MOS capacitors, 15 nm HYO gate dielectric thin films were deposited on the GaAs substrate. Al/HYO/TMA/GaAs/Al MOS capacitors were prepared by

with the intercept of SE emission at 227 K and the slope of the FN tunneling at 77 K, the relation between mox * and qφB has been determined and is shown in Figure 13. Based on our

Figure 13. Relationships between mox * and qφB extracted from the intercept of the SE plots and the FN plots under gate injection.

previous method, the values of m*ox (m*T ) and qφB are obtained to be 0.33 m0 and 0.84 eV, respectively. As a result, it can be concluded that PF emission is dominant at 177−227 K in the lower electric field (substrate injection) and at 77−277 K in the medium electric field (gate injection). In addition, SE emission mainly conducts at 77−227 K in the medium electric field. FN tunneling is a significant transportation mechanism at 77−327 K in the higher electric field, leading to the increased leakage current density.

3. CONCLUSIONS In the current work, the effect of the pulse cycles of ALD TMA on the interface chemistry of GaAs/HYO gate stacks is investigated by means of XPS measurements and electrical analyses. XPS results have confirmed that the intrinsic As oxides, As0, and Ga oxides are effectively reduced for the HYO/GaAs gate stack after ALD TMA treatment with 20 pulse cycles. Electrical measurements have indicated that 20cycle-based MOS capacitors represent the largest dielectric constant, the lowest hysteresis, and the minimum leakage 11670

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fabricating an Al-top electrode with thickness of about 200 nm and the area of 3.14 × 10−8 m2 through a shadow mask with 300 μm diameter, and Al was also deposited as the back electrode to decrease the contact resistance. Besides, PDA under vacuum ambient was performed at 300, 400, and 500 °C for 5 min, marked as S4, S5, and S6, respectively. Figure S2 displays the detailed flowchart in the current experiment. All C−V and J−V characteristics were measured by a semiconductor analyzer (Agilent B1500A) with Cascade Probe Station. The low-temperature leakage current characteristic J− V curves were measured by Lake Shore Vacuum Probe Station (TTPX). All electrical measurements were carried out in a shielding dark box.

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsomega.9b01358. Flowchart in the current experiment; core-level XPS survey spectra of S1, S2, and S3 samples; high-resolution Al 2p core-level XPS spectra of S1, S2, and S3 samples (PDF)

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. ORCID

Gang He: 0000-0003-4711-0568 Jingbiao Cui: 0000-0003-3408-1016 Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS The authors acknowledge the support from National Natural Science Foundation of China (11774001, 51572002) and the Open fund for Discipline Construction, Institute of Physical Science and Information Technology, Anhui University (S01003101).

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REFERENCES

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