Multilevel Nonvolatile Memristive and Memcapacitive Switching in

May 20, 2016 - In addition, the research on organic multilevel memory devices is continuously increasing because of the demand for larger ultra-high-d...
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Multilevel Nonvolatile Memristive and Memcapacitive Switching in Stacked Graphene Sheets Minji Park, Sungjin Park, and Kyung-Hwa Yoo* Department of Physics, Yonsei University, Seoul, 120-749, Republic of Korea S Supporting Information *

ABSTRACT: We fabricated devices consisting of single and double graphene sheets embedded in organic polymer layers. These devices had binary and ternary nonvolatile resistive switching behaviors, respectively. Capacitance−voltage (C−V) curves and scanning capacitance microscopy (SCM) images were obtained to investigate the switching mechanism. The C−V curves exhibited a large hysteresis, implying that the graphene sheets acted as charging and discharging layers and that resistive switching was caused by charges trapped in the graphene layers. In addition, binary capacitive switching behaviors were observed for the device with a single graphene sheet, and ternary capacitive switching behaviors were observed for the device with the double graphene sheets. These results demonstrated that devices consisting of graphene sheets embedded in the polymer layers can be applied to multilevel nonvolatile memcapacitive devices as well as memristive devices. KEYWORDS: graphene, multilevel, nonvolatile, memristive, memcapacitive

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INTRODUCTION Organic memory devices are receiving considerable attention because of their potential advantages over conventional inorganic electronics, such as their light weight, flexibility, and printability.1−6 In particular, nanocomposites containing organic or inorganic nanomaterials, such as C60,7−10 quantum dots,11,12 and metallic nanoparticles,13−16 have been extensively studied for potential applications in next-generation nonvolatile memory devices. In addition, the research on organic multilevel memory devices is continuously increasing because of the demand for larger ultra-high-density data storage capacities for portable electronic devices. Multilevel systems provide an increased data storage density without reducing the size of a memory element.17−21 For example, multilevel resistive memory switching was demonstrated in a ferroelectric phaseseparated blend-based device18 and a cross-linkable dithienylethene-based device.19 A heterostructure consisting of graphene nanoflakes or graphene oxide sandwiched between polymer layers was also reported to exhibit the multilevel resistive memory switching,20,21 although other researchers reported binary resistive switching in devices with a similar structure.22−26 Here, we report a nonvolatile memory device consisting of one (device I) or two graphene sheets (device II) embedded in poly(methyl methacrylate) (PMMA) polymer layers, as shown schematically in Figure 1. Binary nonvolatile memory devices with a single sheet of graphene flakes22,23 or graphene24−26 © XXXX American Chemical Society

embedded in a polymer layer were previously reported. However, graphene sheets can be stacked in a controlled manner because of their 2D property. Therefore, we have developed devices composed of two graphene sheets embedded in PMMA layers (device II) to investigate whether multilevel resistive memory switching could be achieved. Indeed, these devices yielded ternary resistive switching behaviors, implying that the number of resistance states may increase with an increase in the number of graphene sheets. To explore the switching mechanism, the C−V curves were measured for devices I and II. Both devices showed a large capacitance hysteresis, indicating that the graphene sheets embedded in the PMMA layers acted as charging and discharging layers. Moreover, devices I and II exhibited binary and ternary capacitive switching, respectively. These results demonstrated that devices I and II can be applied to memcapacitive as well as memristive devices.

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EXPERIMENTAL DETAILS

Graphene Growth. Graphene sheets were grown using chemical vapor deposition (CVD) with Cu foil. Cu foils (50 μm thick, Nilaco) were cut to the desired size and utilized as growth substrates. The Cu foil was loaded in the center of a quartz tube, and the quartz tube was Received: February 16, 2016 Accepted: May 20, 2016

A

DOI: 10.1021/acsami.6b01962 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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Figure 1. (a) Schematic of device fabrication procedure. (b) TEM image of the cross section of device I. The inset shows an enlarged view of the graphene layer.

Table 1. Summary of Devices with Different PMMA Layer Thicknesses device I-1 device I-2 device I-3 device I-4 PMMA without graphene

thickness of top PMMA layer (nm)

thickness of bottom PMMA layer (nm)

α

Vdip (V)

400 300 500 300

400 300 300 500

11.3 3.68 15.9 3.05 3.57

1.25 0.45 2 0.5 1.5

500

evacuated for 15 min to prevent oxygen contamination. The Cu foil was heated to 850 °C for 30 min and then annealed for 30 min under an H2 atmosphere (40 sccm) to remove the CuO from the Cu foil surface. Next, a H2 (35 sccm) and C2H2 (5 sccm) mixture gas was introduced for 30 min for graphene growth, followed by cooling the sample down to room temperature for 2 h under an Ar atmosphere (200 sccm). Device Fabrication. We fabricated two types of devices, devices I and II, as shown in Figure 1a. Commercially available quartz substrates coated with indium tin oxide (ITO, 100 nm) were employed after cleaning with acetone and treating with O2 plasma. The CVD-grown graphene sheet was transferred onto an ITO/quartz substrate using a PMMA transfer method.27,28 Briefly, a PMMA (950 000 MW, 9 wt % in anisole, MicroChem) layer was spin-coated on a graphene/Cu foil at 3000, 4000, or 5000 rpm for 60 s and baked at 180 °C for 60 min, followed by O2 plasma treatment to remove the graphene uncovered by PMMA. Then, the Cu foil was dissolved in a Cu etchant (APS-100, Transene), and the graphene/PMMA sheet was transferred onto the ITO/quartz substrate. To stack two graphene sheets, the graphene transfer process was repeated one more time. Next, a top PMMA layer was spin-coated at 3000, 4000, or 5000 rpm for 60 s and baked at 180 °C for 60 min. As top electrodes, 250 nm thick circular Al electrodes with a diameter of 50 μm were deposited with a shadow mask using an electron beam evaporator. A transmission electron microscopy (TEM) image obtained from the cross section of device I revealed that the graphene had five layers (Figure 1b). To investigate the thickness dependence of the PMMA layers on the device performances, devices with different PMMA thicknesses,

VSET (V) 2.5 2.45 2.75 2.5

± ± ± ±

0.12 0.05 0.25 0.25

VRESET (V) −2.5 −2.5 −2.6 −2.7

± ± ± ±

0.1 0.5 0.4 0.7

devices I-1, I-2, I-3, and I-4, were prepared by changing the spincoating speed, as summarized in Table 1. The thickness of the PMMA layer was estimated from field-emission scanning electron microscopy (FESEM) images obtained from the cross sections of the devices (Figure S1). The current−voltage (I−V) curves were measured using a semiconductor device analyzer (Keithley 4200), and the C−V curves were measured using a separate semiconductor device analyzer (Keysight B1500A). In these measurements, the bottom ITO electrode was grounded, and the bias was applied to the top Al electrode.

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RESULT AND DISCUSSION First, we characterized device I-1, which had a structure of ITO/PMMA/graphene/PMMA/Al (Figure 1a). Figure 2a shows the representative I−V curves of device I-1. Typical bipolar resistive switching behaviors were observed, as reported in other studies.24−26 Initially, device I-1 was in a highresistance state (HRS), and it remained in this HRS at low voltages. When V was increased further, an abrupt transition to a low-resistance state (LRS) occurred at V ≈ 2.5 V (VSET). This LRS was maintained until the LRS was switched back to the HRS at V ≈ −2.5 V (VRESET). These bistable reversible resistive switching behaviors with an on/off ratio of approximately 104 were reproducible, and the variations in the switching parameters were relatively narrow (Figure S2). For comparison, we also measured the I−V curves for a device without graphene B

DOI: 10.1021/acsami.6b01962 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces

Figure 2. Representative I−V curves measured for (a) device I-1 and (b) device without graphene sheet. “1” denotes a starting point. (c) C−V curves measured at f = 100 kHz for device I-1. (d) I−V curves plotted on semilogarithmic scales for device I-1 and device without the graphene sheet. (e) I−V curves plotted on semilogarithmic scales for devices I-1, I-2, I-3, and I-4. (f) I−V curves plotted on log−log scales for devices I-1, I-2, I-3, and I-4 and the device without the graphene sheet.

curves were possibly ascribed to the different bottom (ITO) and top (Al) electrodes. To investigate the effects of the PMMA layer thickness, we prepared more devices, devices I-2, I-3, and I-4, which had different top or bottom PMMA layer thicknesses (Table 1). Figure 2e shows representative I−V curves for these devices. Devices I-2 and I-4, which had the same top PMMA layer thicknesses, exhibited similar values of Vdip and VSET, although | VRSET| was higher for device I-4 than for device I-2. In contrast, devices I-2 and I-3, which had the same bottom PMMA layer thicknesses, yielded similar values of VRESET, although Vdip and VSET were higher for device I-3 than for device I-2. In the I−V curve measurements, the bottom ITO electrode was grounded, and the bias was applied to the top Al electrode. Thus, these findings suggested that charges were injected from the Al top electrode into the PMMA layer, and the transport of injected charges was affected by the presence of the graphene sheet embedded between the PMMA layers. To take into account carrier injection processes, the I−V curves are plotted on log−log scales in Figure 2f. At very low

(ITO/PMMA (500 nm)/Al, Figure 2b). This device exhibited no hysteresis, indicating that the resistive switching was attributed to the graphene embedded in the PMMA layer. To investigate the role of the graphene layer, the C−V curves were measured for device I-1at f = 100 kHz (Figure 2c). When V was swept to positive voltages, C increased abruptly around VSET. Then, high-capacitance states were maintained until there was a sudden drop in C around VRESET. These results implied that charges were trapped in the graphene layer by applying the positive voltages of V > VSET, and trapped charges remained in the graphene layer until the negative voltages of |V| > |VRESET| were applied, leading to bistable resistive switching behaviors. In Figure 2d, the I−V curves measured for device I-1 and the device without graphene are plotted on semilogarithmic scales. We noted that the I−V curves of device I-1 in an HRS were similar to those of the device without graphene. When V was swept to positive voltages, I decreased slightly at low values of V and then rapidly increased. As a result, a conductance dip was observed at Vdip. In contrast, when V was negative, I decreased monotonically with decreasing V. These asymmetric I−V C

DOI: 10.1021/acsami.6b01962 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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Figure 3. Schematic of resistive switching in device I.

Figure 4. Representative I−V curves measured for device II on (a) linear and (b) semilogarithmic scales. The numbers denote a sequence of voltage sweeping. (c) Current response of device II measured with Vread = 1 V after applying voltage pulses repeatedly to switch the LRS, IRS, or HRS (top inset).

bias voltages (V < Vdip), I was very small and nearly independent of V, suggesting that the number of injected charges was too small to contribute the conduction. However, after repeating the I−V curve measurements several times, the conductance in this voltage range slightly increased, and the conductance dip disappeared (Figure S3). These results suggested that some charges might be trapped on defects in the PMMA layers, and they were not completely released by applying the negative bias voltages, leading to an increase in conduction. However, for Vdip < V < VSET, I increased with the relationship I ∝ Vα, and the value of α increased with an increase in the thickness of the top PMMA layer (Table 1), which can be explained in terms of a trapped-charge-limited current (TCLC) model that predicts α > 2 for the traps distributed exponentially within the forbidden energy gap.29,30

In addition, we measured the I−V curves at different temperatures (Figure S4). The conduction at very low voltages was nearly independent of temperature. However, as the temperature increased, the conductance in the range of Vdip < V < VSET increased, and the value of α decreased, which is consistent with the TCLC model. Moreover, binary resistive switching was found to be stable even at 100 °C, although the resistance in the LRS increased with increasing temperature, as reported by others.22 The above results suggested a model, as shown in Figure 3. When V is applied to the Al electrode, charges are injected from the Al electrode to the LUMO level of the PMMA layer, and they are transported in the direction of the applied voltage through the tunneling among the PMMA molecules (V < VSET). However, because the energy level of graphene is within D

DOI: 10.1021/acsami.6b01962 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces

Figure 5. (a) C−V curves measured at f = 100 kH for device II. “1” denotes a starting point. (b) Capacitance response of device II obtained at f = 100 kHz after applying voltage pulses repeatedly to switch the LRS, IRS, or HRS (right inset). (c) SCM images measured for device II in the HRS, IRS, and LRS.

Figure 6. Schematic of resistive switching in device II.

the representative I−V curves of device II. Unlike device I-1, this device exhibited ternary resistive switching behaviors. When V was swept from 0 to 5 V, two abrupt electrical transitions occurred. One transition was from the HRS to an intermediate resistance state (IRS) at V ≈ 2.95 V (VSET1), and the other transition was from the IRS to the LRS at V ≈ 4.1 V (VSET2). Subsequently, when V was swept to negative voltages, two similar transitions were observed. One transition was from the LRS to the IRS at VRESET1 ≈ −2.7 V, and the other transition was from the IRS to the HRS at VRESET2 ≈ −3.25 V. Furthermore, when V was swept to positive voltages after a sequence of 0 V → −4 V → 0 V, the device was in the HRS; however, after a sequence of 0 V → −3 V → 0 V, the device was in the IRS (Figure 4b). These observations implied that the HRS and IRS states could be controlled by applying |V|> | VRESET2|and |VRESET2| > |V| > |VRESET1|, respectively. The reversible switching of the three different resistance states, HRS, IRS, and LRS, is demonstrated in Figure 4c. First, a voltage pulse with an amplitude of +5 V and a width of 2 ms

the lowest unoccupied molecular orbital (LUMO) and highest occupied molecular orbital (HOMO) levels of PMMA, injected charges are trapped in the graphene layer. When charges are trapped in the graphene layer, the PMMA and graphene layers act as a donor and an acceptor and are charged positively and negatively, respectively. Consequently, an internal electric field is induced in the PMMA (V ≈ VSET).24 For V > VRESET, some of the injected charges are free and accelerated by the local internal field. As a result, the device switches to an LRS (V > VSET). This LRS is maintained until the charges trapped in the graphene layer are released by applying negative voltages (V ≈ VRESET). Son et al.24 proposed the formation of conducting filaments as a possible switching model. However, the hysteric C−V curves rule out the possibility of filamentary formation because the filamentary formation may not lead to capacitance hysteresis. Next, we characterized device II, which has a structure of ITO/PMMA (400 nm)/graphene/PMMA (400 nm)/graphene/PMMA (500 nm)/Al (Figure 1a). Figure 4a shows E

DOI: 10.1021/acsami.6b01962 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces was applied to switch to the LRS, and I was measured at Vread = 1 V. Subsequently, the LRS was switched to the HRS by a voltage pulse with an amplitude of −5 V and a width of 2 ms, and I was measured. Then, the HRS was switched to the IRS by applying a voltage pulse with an amplitude of −3 V and a width of 5 ms, followed by a voltage pulse with an amplitude of +3.5 V and a width of 2 ms. These three different states could be repeatedly switched. To investigate the retention characteristics, we measured I with V = 1 V at 100 °C as a function of time in the HRS, IRS, or LRS (Figure S5). No significant changes in I were observed within 103 s for all the states, indicating that device II can be applied to multilevel nonvolatile memory devices. The C−V curves of device II measured at f = 100 kHz are shown in Figure 5a. When V was swept to positive voltages, two transitions were observed, as in the I−V curves. There were sudden increases in C around VSET1 and VSET2, and then high capacitance values were maintained. However, when V was swept to negative voltages, there was a sudden drop in C around VRESET2, followed by a further gradual decrease, although another device II exhibited two transitions upon applications of negative voltages (Figure S6). These results suggested that the first transition might have occurred when the injected charges were trapped in the upper graphene sheet, and the second transition occurred when they were trapped in the lower graphene sheet (Figure 6). To investigate the relationship between the resistance states and the capacitance states, device II was switched to LRS, IRS, or HRS by applying voltage pulses, and C was then measured (Figure 5b). LRS, IRS, and HRS yielded values of C corresponding to the high-, intermediate-, and low-capacitance state, respectively, demonstrating that device II can be applied to multilevel memcapacitive as well as memristive devices. In addition, we obtained SCM images for device II in the HRS, IRS, and HRS (Figure 5c). Device II in the HRS could not be distinguished from the surroundings because it had low capacitance values. However, device II in the LRS was clearly observed, supporting the conclusion that the resistive switching was closely related to the capacitive switching.

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This work has been financially supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT, and Future Planning (Grant Nos. 2011-0017486 and 2012R1A4A1029061).

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REFERENCES

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CONCLUSIONS We fabricated devices with structures consisting of ITO/ PMMA/graphene/PMMA/Al (device I) and ITO/PMMA/ graphene/PMMA/graphene/PMMA/Al (device II). Devices I and II exhibited binary and ternary nonvolatile memory characteristics, respectively, implying that the number of switching states might be affected by the number of graphene sheets embedded in the PMMA layer. A comparison with the I−V curves of the device without graphene showed that the conductance of device I in the HRS could be explained by the TCLC model. In addition, the C−V curves and SCM images revealed that the graphene sheets acted as charging and discharging layers, and the resistive switching was caused by the trapped charges in the graphene layers. These results demonstrated that devices consisting of graphene sheets embedded in insulating polymer layers might be applied to multilevel nonvolatile memcapacitive devices as well as memristive devices.

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.6b01962. F

DOI: 10.1021/acsami.6b01962 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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DOI: 10.1021/acsami.6b01962 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX