n-Si(001) Interface Ensured by

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Strong Fermi-Level Pinning at Metal/n-Si(001) Interface Ensured by Forming an Intact Schottky Contact with a Graphene Insertion Layer Hoon Hahn Yoon, Sungchul Jung, Gahyun Choi, Junhyung Kim, Youngeun Jeon, Yong Soo Kim, Hu Young Jeong, Kwanpyo Kim, Soon-Yong Kwon, and Kibog Park Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.6b03137 • Publication Date (Web): 14 Dec 2016 Downloaded from http://pubs.acs.org on December 17, 2016

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Strong Fermi-Level Pinning at Metal/n-Si(001) Interface Ensured by Forming an Intact Schottky Contact with a Graphene Insertion Layer Hoon Hahn Yoon,

Jeon,

‡

†

Sungchul Jung,

Yong Soo Kim,

¶

†

Gahyun Choi,

Hu Young Jeong,

§

†

Junhyung Kim,

Kwanpyo Kim,

and Kibog Park

†

‡

Youngeun

Soon-Yong Kwon,

k

∗,†,‡

†Department

of Physics, Ulsan National Institute of Science and Technology (UNIST), Ulsan 44919, Republic of Korea ‡School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology (UNIST), Ulsan 44919, Republic of Korea ¶Department of Physics and Energy Harvest-Storage Reseach Center (EHSRC), University of Ulsan, Ulsan 44610, Republic of Korea §UNIST Central Research Facilities (UCRF), Ulsan National Institute of Science and Technology (UNIST), Ulsan 44919, Republic of Korea kSchool of Materials Science and Engineering, Low Dimensional Carbon Materials Center, Ulsan National Institute of Science and Technology (UNIST), Ulsan 44919, Republic of Korea E-mail: [email protected]

Phone: +82 (0)52 2172111. Fax: +82 (0)52 2172130

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Abstract We report the systematic experimental studies demonstrating that a graphene layer inserted at Metal/n-Si(001) interface is ecient to explore interface Fermi-level pinning eect. It is conrmed that an inserted graphene layer prevents atomic interdiusion to form an atomically abrupt Schottky contact. The Schottky barriers of Metal/Graphene/n-Si(001) junctions show a very weak dependence on metal workfunction, implying that the metal Fermi-level is almost completely pinned at charge neutrality level close to the valence band edge of Si. The atomically-impermeable and electronically-transparent properties of graphene can be used generally to form an intact Schottky contact for all semiconductors.

Keywords Schottky barrier, Graphene, Diusion barrier, Intact interface, Fermi-level pinning, Internal photoemission

Text It is very crucial to characterize the electrical properties of a metal/semiconductor junction so called Schottky contact in its electronic and optoelectronic applications. Although there has been a great deal of interests and research activities over past several decades, 13 the fundamental mechanisms of energy barrier formation and carrier transport of a Schottky contact, directly related to the physical and chemical phenomena at interface, are still somewhat arguable. 411 The major complexity of Schottky contact formation comes from intermixing of materials at interface, driven by the diusion of metal and semiconductor atoms. Graphene, a single-layer carbon sheet with honeycomb lattice structure, has been considered as a promising candidate material for future electronic applications mostly due to its remarkable electronic properties. 1215 In particular, the ambipolar characteristic and high car2


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rier mobility of graphene are the main attractors. Another interesting property of graphene is that atoms hardly penetrate through it. This impermeability of graphene relies on the dense electron clouds lling the openings in honeycomb lattice completely. Very recently, it has been reported that a graphene layer sandwiched between metal and semiconductor takes a role of diusion barrier with negligible electrical resistance that prevents materials from intermixing during thermal stressing. 16 There have also been rapidly-growing interests in the electrical properties of metal/graphene and graphene/semiconductor interfaces in the sense of the charge carrier transport between two- and three-dimensional materials. 17,18 In this letter, we demonstrate that a graphene layer inserted at Metal/n-Si(001) interface is particularly useful for investigating interface Fermi-level pinning eect. Based on high-resolution transmission electron microscopy (HRTEM) images and current-voltage (I-V) measurements, it is concluded that an inserted graphene layer minimizes interfacial reactions and eciently protects the Schottky junction from unwanted changes in electrical properties. The internal photoemission (IPE) measurements capable of directly determining interface energy barrier with hot carrier transport show unambiguously that the Schottky barrier of an intact Metal/n-Si(001) junction obtained with a graphene insertion layer is almost independent of metal work-function, implying very strong Fermi-level pinning at interface (Bardeen limit). 1921 The Metal/Graphene/Si and Metal/Si junctions were prepared by following the procedures below. The monolayer graphene synthesized on a Cu foil by chemical vapor deposition (CVD) was purchased from the Bluestone Global Tech, USA. The well-known method was employed for graphene transfer onto an n-type ( ∼1×1015 cm−3 ) Si(001) substrate preprocessed with RCA cleaning and hydrogen passivation, 2227 (See Supporting Information for further details on the transfer method). The graphene transfer was done on the half of Si surface intentionally in order to leave the other half uncovered. After graphene tranfer, circular metal electrodes (Ni, Pt, Ti) were deposited through a shadow mask on the sample surface by using e-beam evaporation. The metal electrodes deposited on the graphene-uncovered

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Photon

A

n-Si(001) Graphene Metal Native Oxide n-Si(001)

Figure 1: The schematic view of IPE measurements on Metal/n-Si(001) junctions with and without a graphene insertion layer. The two zoom-ins illustrate the atomic arrangements at the Metal/Si and Metal/Graphene/Si interfaces. The average diameter of circular metal electrodes is ∼500 µm. area formed the Metal/Si junctions. Finally, we removed the metal-uncovered graphene by reactive ion etching (RIE) to form isolated Metal/Graphene/Si junctions. In this way, we could form the Metal/Graphene/Si and Metal/Si junctions simultaneously on the same Si surface. IPE measurements 2833 (See Supporting Information for details on the IPE measurement system) were carried out to determine the Schottky barriers of the Metal/Graphene/Si and Metal/Si junctions. The cross-sectional schematic view of device structure and measurement conguration are shown in Figure 1. The light with a photon energy varying from 0.8 eV to 1.3 eV was focused onto each metal electrode. The zero bias Schottky barriers were obtained by extracting the threshold of IPE quantum yield and estimating the image force lowering due to the depletion eld. The threshold of IPE quantum yield was obtained by using the relation

Y = C(Eph − φth )m , where Y is the quantum yield, Eph the incident photon energy, φth the threshold, C the proportionality constant, and m = 2 for the metal/semiconductor junction with a thin oxide layer at interface. The actual procedure for extracting the threshold was 4


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Figure 2: The square root of IPE quantum yield as a function of photon energy measured on the Metal/n-Si(001) junctions with (a) Ni, (b) Pt, and (c) Ti electrodes for with and without a graphene insertion layer. The insets show the magnied view of the threshold region with linear extrapolation. The average Schottky barriers φB are listed in table. to t the linear portion of Y 1/2 vs Eph curve near its turn-on point with the relation of

Y 1/2 = C 1/2 (Eph − φth ) and nd the intercept φth of tted linear line with the Eph axis. The IPE yield spectra for the Ni/Graphene/Si and Ni/Si junciton are shown in Figure 2a. 5


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For the Ni/Si junction with no graphene insertion layer, two thresholds are observed. Since the post-annealing process was not performed after Ni deposition, it is quite unlikely to have a stoichiometric Ni-silicide layer formed widely at the interface. Hence, a certain localized reaction between metal and semiconductor atoms, most probably material intermixing by atomic diusion, is considered to occur and induce the change of junction electrical properties. 34,35 It is known that this localized material intermixing can occur during metal deposition on semiconductor even at room temperature. The mixture of Ni and Si atoms has been found to grow from a small island formed at the initial stage of deposition. Since the small islands tend to be scattered sparsely on the Si surface, the mixtures of Ni and Si atoms are expected to be localized and scattered randomly at the interface as well. 36 It is also known that this mixture of Ni and Si atoms bears a Schottky barrier lower in comparison with pure Ni atoms. 8 Therefore, the rst and second thresholds of Ni/Si junction without a graphene insertion layer are likely to indicate the existence of the isolated areas with their local Schottky barriers lower than that of the surrounding, 911 which are formed by the interface material intermixing mentioned just before. On the other hand, for the Ni/Graphene/Si junction with a graphene insertion layer, only one threshold is observed. Averaged over several different junctions, the Schottky barriers extracted from the IPE thresholds are 0.676 ±0.011 eV and 0.939±0.016 eV for the Ni/Si junction and 0.976 ±0.002 eV for the Ni/Graphene/Si junction. These averaged Schottky barriers include the image force lowering. With the IPE measurements, we can make a conjecture that a graphene layer inserted at Metal/Si interface prevents the inter-diusion of metal and Si atoms so that an atomically-abrupt Schottky contact with a uniform Schottky barrier can be formed. The HRTEM images in Figure 3a,b show that the thickness of the native oxide layer at Ni/Si interface varies actually depending on location. Two dierent sites in the same Ni/Si junction were investigated. By analyzing the structural change across the interface for Figure 3a,b, the SiO 2 layer in Figure 3b is found to be thinner than that in Figure 3a. In particular, the SiO 2 layer of the red-circled area looks quite thin. These two HRTEM

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Nano Letters (a) Ni SiO2 Si 2 nm (b) 2 nm (c) Graphene 2 nm Figure 3: (a) and (b): The HRTEM images at two dierent locations in the same Ni/Si junction without a graphene insertion layer, showing the non-uniform native oxide layer. The SiO2 layer of the red-circled area in (b) appears to be particularly thin. (c): The HRTEM image of Ni/Graphene/Si junction where the graphene insertion layer is seen obviously. of SiO 2 layer is spatially inhomogeneous and some areas images signify that the thickness might have pinholes with no SiO 2 layer at all in the Ni/Si junction. As discussed previously, areas with thin SiO layers or pinholes where the material the local Schottky barriers on the 2 intermixing can occur more easily will be lower than the surrounding areas with thicker SiO2 layers. Figure 3c shows the HRTEM image of the Ni/Graphene/Si junction where the graphene layer transferred before the metal electrode deposition is seen clearly. Figure 4a shows the conventional I-V curves measured on Ni/Si and Ni/Graphene/Si junctions. As shown in the gure, the reverse-bias leakage current of Ni/Graphene/Si junc tion is noticeably smaller than that of Ni/Si junction. This is consistent with our conjecture 7 ACS Paragon Plus Environment

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Figure 4: The I-V curves measured on the Metal/n-Si(001) junctions with (a) Ni, (b) Pt, and (c) Ti electrodes for with and without a graphene insertion layer. Each dashed line represents a linear line tted to the thermionic emission model. The average ideality factors n and Schottky barriers φB are shown in table. claiming that the local material intermixing inducing the low barrier patches in the Ni/Si junction can be blocked by the graphene insertion layer. As well-known, the I-V character-

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istics of an inhomogeneous Schottky contact are dominated by low barrier patches although their fraction in the entire contact is relatively small. By adopting the thermionic emission model, 37 the average Schottky barrier is estimated to be 0.743 ±0.018 eV and 0.847±0.017 eV for the Ni/Si and Ni/Graphene/Si junction respectively. The smaller Schottky barrier of Ni/Si junction, in comparison with Ni/Graphene/Si junction, is consistent with the IPE measurements. However, the two-threshold behavior observed in the IPE measurements is not seen here. This single-threshold behavior can be understood by considering the parallel conduction model for the thermionic emission through an inhomogeneous Schottky contact. 38 According to the parallel conduction model calculation adopting the two barriers extracted from the IPE measurements (See Supporting Information for details.), the areal fraction of lower barrier in the Ni/Si junction is estimated to be ∼7.62 %. The IPE and I-V measurements on the Pt/Si and Pt/Graphene/Si junction, shown in Figures 2b and 4b, bear almost identical Schottky barriers for both junctions. This is likely because the material intermixing at the Pt/Si interface is not quite active and the associated low-barrier patches would be very small in size, 4 dierently from the Ni/Si junction. According to Tung, 2,3,9,10 the high-barrier surrounding makes the energy band prole of a small low-barrier patch pinched-o strongly so that the energy barrier seen by the electrons crossing the interface will become almost comparable to the high-barrier surrounding. Hence, the small low-barrier patches would not be revealed in extracting Schottky barriers from the IPE and I-V measurements. By the way, Tung also pointed out that the pinch-o of energy band prole in the small low-barrier patches will be reduced for reverse biases. Then, the small low-barrier patches can provide preferred paths for electron transport and the reverse bias leakage becomes larger than the case with no low-barrier patches. This is actually what is observed in the I-V measurements. The reverse bias leakage current of Pt/Si junction is larger than that of Pt/Graphene/Si junction (Figure 4b). Regarding the Ti/Si junction, the junction was so leaky as shown in Figure 4c. Therefore, the photocurrent in IPE measurements was overwhelmed completely by the junction leakage

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and the corresponding IPE yield could not be dened at all. This implies that the intermixing of Ti and Si atoms at the interface is more active than the Ni/Si and Pt/Si junctions. 39 On the other hand, the Ti/Graphene/Si junction with a graphene insertion layer is much less leaky (∼1000 times smaller) and the IPE yield is well specied as shown in Figure 2c. These measurement results for the Ti/Si and Ti/Graphene/Si junctions support strongly that the graphene insertion layer really makes the Schottky junction intact by greatly reducing the material intermixing at the interface. One thing to note here is that the I-V extracted Schottky barrier of Ti/Graphene/Si junction is somewhat smaller than those of Ni/Graphene/Si and Pt/Graphene/Si junctions. It is always probable to have some small areas missing C atoms in the graphene insertion layer which reect the structural damages generated during the transfer process. In these small areas, the metal and Si atoms can meet directly to bear a certain degree of atomic intermixing. As mentioned previously, the atomic intermixing at Ti/Si interface appears to be more active than Ni/Si and Pt/Si interfaces. Hence, the atomically-mixed small areas of Ti/Graphene/Si junction are very likely to be leakier in comparison with Ni/Graphene/Si and Pt/Graphene/Si junctions. Then, the Ti/Graphene/Si junction itself will appear to be leakier, leading to the smaller I-V extracted Schottky barrier. It is known that the IPE measurements are more suitable than the conventional I-V measurements for determining the Schottky barrier on the prevailing area of a metal/semiconductor junction without being inuenced by the small portion of low-barrier patches. The Schottky barriers on the prevailing areas extracted from the IPE measurements are estimated on average to be 0.976±0.002 eV, 0.976±0.001 eV, and 0.971 ±0.002 eV for the Ni/Graphene/Si, Pt/Graphene/Si, and Ti/Graphene/Si junctions respectively. It is apparent that the extracted Schottky barriers are almost independent of metal work-functions. This implies a very strong Fermi-level pinning at the interface, i.e., approaching the Bardeen limit. 1921 Figure 5 shows the IPE-extracted Schottky barriers φB as a function of metal work-function

φM . 40 From the slope of the linearly-tted line in Figure 5, the pinning factor S , dened to 10


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Schottky Barrier (eV)

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Figure 5: The Schottky barriers of Metal/Graphene/n-Si(001) junctions determined from the IPE measurements vs metal work-functions. The solid black line is the linear t to the measured data. The dashed red and blue line represent (a) the Schottky limt ( S = 1) and (b) the Bardeen limit ( S = 0). The inset shows the alignment of several relevant energy levels (E0 : Vacuum, Ec : Conduction band edge, Ev : Valence band edge, and EF : Metal Fermi-level). be S = ∂φB /∂φM , is obtained to be ∼4.01×10−3 quite similar to the theoretically-predicted value of ∼7.63×10−2 . 4143 By considering the relation φB = S(φM − φS ) + (φS − χs ), where

χs is the Si electron anity, the charge neutrality level at the Metal/Si interface is estimated to be ∼5.025 eV from the vacuum level ( φS ). This implies that the charge neutrality level is positioned ∼0.145 eV above the valence band edge ( φ0 ). At this stage, it looks worthwhile to compare our works with the previously-reported ones of Byun et al. 44 demonstrating that the rectifying behavior of Ni/Si junction turns into the ideal ohmic one simply with a graphene layer inserted at interface. They claimed the two-fold contributions of graphene insertion layer for forming an ohmic contact. One is the modulation of work function by being contacted with the metal layer and the other is to eliminate the Fermi-level pinning at interface. The modulation of graphene work function stems from its intrinsic low density of states. Hence, this phenomenon will occur commonly in the devices of both Byun et al. 44 and us. According to the density functional theory calculations done by Giovannetti et al., 45 the graphene insertion layer is expected to be n-

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doped when being contacted with Ni and Al and p-doped with Pt. However, there is a clear dierence between the works of Byun et al. 44 and us for the interface Fermi-level pinning. Based on their experiments utilizing the conductive AFM with its tip made of doped-Si to form the Ni/Graphene/Si junction on a Ni/Graphene substrate, they reached the conclusion (almost no Fermi-level pinning) opposite to ours (strong Fermi-level pinning). The reason for the completely dierent outcomes for the same Ni/Graphene/Si junction is considered to be the dierence in junction area. The Ni/Graphene/Si junction of Byun et al. 44 is expected to be quite small since it is formed with the AFM tip. The small-area (below a couple of hundreds nm in lateral size) Schottky junctions are known to behave as being unpinned although the interface Fermi-level pinning is quite strong. 46 On the other hand, our Ni/Graphene/Si junction is quite large ( ∼500 µm in diameter) so that it is more suitable to investigate the Fermi-level pinning at interface. More detailed descriptions for dierentiating the small- and large-area Schottky junctions in terms of the inuences of interface Fermi-level pinning on the junction energy band proles can be found in the Supporting Information. In conclusion, it has been experimentally demonstrated that a graphene layer inserted at Metal/n-Si(001) interface can suppress the material intermixing substantially to form an atomically-abrupt Schottky contact. The Fermi-level pinning at the intact Metal/n-Si(001) interface formed with the graphene insertion layer was found to be very strong, matching well with the theoretical prediction. The atomically-impermeable and electronicallytransparent aspects of the graphene insertion layer can provide an ecient platform to explore the interface Fermi-level pinning for all other semiconductor Schottky junctions as well. This graphene insertion layer idea can also be adopted in superconductor/metal, superconductor/insulator, and superconductor/semiconductor junctions to establish an ideal environment for studying the cooper-pair transport across the interface.

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Acknowledgement This work was supported by the National Research Foundation of Korea (2013R1A1A2007070, 2014M2B2A9031944, 2015H1A2A1033714). This work has also beneted from the use of the facilities at UNIST Central Research Facilities.

Supporting Information Available • Supporting Information: Details of sample fabrication process, IPE measurement system, parallel conduction model calculation, and Fermi-level pinning eect depending on Schottky junction area. This material is available free of charge via the Internet at http://pubs.acs.org/ .

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Graphical TOC Entry Photon

0.6

A

n-Si(001) Graphene Metal Native Oxide

Yield 1/2 (relative units )

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

0.4

0.06

0.30

0.05

0.25

0.04

0.20

0.03

0.15

0.02

0.10

0.01

0.2

0.05

0.00

0.00 0.677

0.6

0.940 0.965

1.0

φB (eV)

1.2 Ni/G/Si Ni/Si Ni/Si

Ni/G/Si Ni/Si

0.0 0.6

n-Si(001)

0.8

0.8

1.0

Photon Energy (eV)

17


1.2

0.976 0.676 0.939

n-Si(001) Interface Ensured by

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