Nanoscale Vacuum Channel Transistor - Nano Letters (ACS

Mar 23, 2017 - (6, 7) The lateral type devices with electron emission in plane are suitable for general electronics as the gap size is variable by a p...
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Nanoscale Vacuum Channel Transistor Jin-Woo Han,* Dong-Il Moon, and M. Meyyappan Center for Nanotechnology, NASA Ames Research Center, Moffett Field, California 94035, United States S Supporting Information *

ABSTRACT: Vacuum tubes that sparked the electronics era had given way to semiconductor transistors. Despite their faster operation and better immunity to noise and radiation compared to the transistors, the vacuum device technology became extinct due to the high power consumption, integration difficulties, and short lifetime of the vacuum tubes. We combine the best of vacuum tubes and modern silicon nanofabrication technology here. The surround gate nanoscale vacuum channel transistor consists of sharp source and drain electrodes separated by sub-50 nm vacuum channel with a source to gate distance of 10 nm. This transistor performs at a low voltage (3 microamperes). The nanoscale vacuum channel transistor can be a possible alternative to semiconductor transistors beyond Moore’s law. KEYWORDS: Vacuum field effect transistor, field emission, gate-all-around, cold cathode

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Recently, lateral type vacuum tubes with submicron features have been fabricated using CMOS technology.10,11 However, the gate structure in those studies was a single-gate planar structure as a back gate, which resulted in a weak gate-tochannel control and thus required drive voltages greater than 10 V. The present work rectifies the poor gate control issue with a gate structure that is optimal in terms of current drivability and operation voltage scalability yet feasible in terms of fabrication. In this regard, the gate-all-around structure in lateral devices is used for the first time in vacuum electronics, yielding the highest drive current yet for the lowest drive voltages with nanoscale features in silicon. Bottom-up grown nanowire/nanotube based vacuum devices could also conquer the sub-10 V operation in principle because the vacuum gap can be aggressively reduced by controlling the growth of the material; in addition, the one-dimensional structure is inherently suitable for field emission.12,13 However, the bottom-up approaches face several obstacles at present including the placement of nanomaterial in the channel, alignment, homogeneity, and integration challenges, all of which hindering the development of integrated circuits (IC). We herein report on the fabrication of a nanoscale vacuum channel transistor (NVCT) using top-down silicon technology with no exotic materials. To maximize the gate-to-vacuum channel control, we have implemented a gate structure surrounding the cylindrical vacuum channel. For sub-5 V operation target, an aggressive scaling of the vacuum channel is critical. At a given standard 0.18 μm fabrication facility, we overcame the lithographic limit by photoresist trimming and local sacrificial oxidation process.14,15 Thus, a vacuum channel

hough vacuum tubes initiated the early electronics age, complementary metal−oxide−semiconductor (CMOS) field-effect-transistors (FET) had taken over their role in contemporary electronics.1 The solid-state devices are scalable without loss of performance, consume extremely low power per function, and can be easily integrated into functional circuits enabling large-scale manufacturing. However, the vacuum state provides superior electron transport compared to all semiconductors as collisions and scattering with the crystal lattice do not occur. Thus, the electron velocity in vacuum is much higher than the saturation velocity in silicon and other high mobility semiconductors such as germanium and gallium arsenide. Furthermore, vacuum devices offer more stable operation than solid-state devices under extreme temperature and radiation environments.2,3 The constant electric field scaling theory has been the basis for the advancement of silicon electronics, and critical features such as the gate length and width and the operation voltage are scaled by the same factor so as to keep the electric field constant.4 This scaling has allowed to increase the circuit density and reduce the power consumption. The scalability, integration, and low power consumption in solid-state electronics are realized by continuous advances in semiconductor process technology.5 Similarly, the miniaturization of vacuum tubes can also lead to higher integration and lower operation voltage and power consumption. Indeed, there have been many attempts in the past to adapt the semiconductor processing technology to fabricate vacuum tubes. Advances in micro- and nanoelectromechanical systems have been exploited to construct vacuum devices.6−9 Vertical devices, wherein the electron emission is directed out-of-plane, have found limited application in displays and electron sources.6,7 The lateral type devices with electron emission in plane are suitable for general electronics as the gap size is variable by a photomask layout.8,9 This article not subject to U.S. Copyright. Published XXXX by the American Chemical Society

Received: October 18, 2016 Revised: February 13, 2017 Published: March 23, 2017 A

DOI: 10.1021/acs.nanolett.6b04363 Nano Lett. XXXX, XXX, XXX−XXX

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Figure 1. Schematic illustrations of (a) a silicon nanowire gate-all-around transistor and (b) a nanoscale vacuum channel transistor. Energy band diagrams in the source to channel direction, xz-plane, of the (c) silicon nanowire gate-all-around transistor and (d) the nanoscale vacuum channel transistor. (e) Scanning electron microscope image of the nanoscale vacuum channel transistor.

Figure 2. Finite element simulation results for the electric field. Electric field map of devices with (a) a single gate and (b) the surround gate, cut along the source to channel direction, i.e., xz-plane. VG and VD are 5 and 2 V, respectively. (c) The peak field normalized by the value for the single gate for various gate structures.

voltage increases, the increased free carrier density raises the mobility, but it is eventually limited by the lattice scattering at higher gate voltages. In the NVCT, the electrons confined in the source tunnel quantum-mechanically to the vacuum channel while the electrons are thermionically injected out from the source and then drift though the silicon channel in the silicon transistor. The difference arises in the switching modulation. The gate voltage controls the energy barrier width and the tunneling probability in the NVCT. In contrast, the gate voltage modulates the energy barrier height and the thermionic injection efficiency in the nanowire transistor (Figure 1c and d). But the output I−V characteristics measured from the terminals are analogous so that no discrimination will be found. The old vacuum tubes used a filament heater to enhance thermionic emission. Recently, a laser has been used to harness the photoelectron emission for the same purpose.17,18 However, the use of an external energy source complicates the system and consumes power. Therefore, a vacuum device that emits electrons only by application of a bias voltage with no other external energy supply is desirable. Reducing the vacuum gap size intensifies the local electric field; besides, a gate structure fully wrapping around the emitter tip can also intensify the local electric field. The NVCT fabricated on 8′′ wafers here consists of the source and drain separated by the vacuum gap and the cylindrical vacuum channel surrounded entirely by the gate (Figure 1e). The fabrication details can be found in Figure S1 in the Supporting Information (SI). The vacuum channel length is variable as it is defined with the aid of photolithography, whereas the vacuum channel diameter is fixed across all of the devices. The use of surround gate

length (source-to-drain) of 50 nm and a channel radius (source-to-gate) of 10 nm have been achieved. The 50 nm vacuum channel distance is smaller than the mean-free-path of air molecules under atmospheric pressure.16 Accordingly, the air channel here can be considered as quasi-vacuum, which relieves the vacuum requirement. A finite-element numerical simulation has been used to compare the surround gate with other multiple gate structures for the electrostatic field enhancement. Current−voltage (I−V) characteristics and their parametric statistics are provided at room and high temperatures. The immunity to gamma and proton radiations is also investigated. The structure of the NVCT is similar to the nanowire gateall-around transistor except that the silicon channel is replaced by an empty gap and the source is sharpened for local field enhancement (Figure 1a and b). The operation mechanisms of these two are analogous. In traditional silicon transistors, the channel electrons are supplied rapidly from the source electrode unlike in a MOS capacitor, where the channel inversion layer electrons are produced slowly by thermal generation in the depletion region. The thermal energy of electrons in the source is confined according to the Fermi− Dirac distribution. When a voltage is applied to the gate, some of the more energetic electrons at the source enter into the channel due to the increased channel potential. Once the channel electrons drift toward the drain, the drain current is determined by the drift velocity of the electrons in the channel. The latter is proportional to the carrier mobility, which is influenced by many factors including the free carrier density, scattering with the silicon lattice, and interfaces. As the gate B

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Figure 3. Fundamental electric characteristics of the fabricated devices. (a) Drain current versus drain voltage characteristics of the nanoscale vacuum channel transistor showing an exponential increase in current; a control device with uniformly doped nanowire resistor is also shown. (b) The Fowler−Nordheim (FN) fitting curve for the NVCT shown in panel a. The linearity of the FN curve indicates free electron transport following the tunneling mechanism. (c) Drain current versus gate voltage characteristics of the NVCT for various drain voltages.

intensifies the local field in the proximity of the source tip compared to conventional single gate.10,11 As the NVCT is designed to emit electrons without heating, the electrostatic coupling efficiency between the gate and the source is critical. Referring to the structural evolution of CMOS devices, the long-standing single-gate planar transistor had evolved to a double-gate FinFET in order to increase the channel controllability, and now the gate-all-around FET is expected to take over the FinFET.19 Drawing the same analogy, the ultimate design for NVCT would also be the surround gate structure. Finite element simulations were carried out to estimate the electric field enhancement factor of the NVCT (Figure 2a and b).20 The simulation details including the computational domain, boundary conditions, and simulation parameters can be found in Section 4 of the SI. The maximum local field was extracted from the simulation results and normalized to the field value for the single gate for effective comparison (Figure 2c). The electric field map shows that simply adding an extra gate intensifies the effective field in the proximity of the source tip. The double-gated vacuum device was experimentally studied before,21 and the simulation here shows that it results in a local field enhancement of 60%. The increment in local field is sublinear with additional gates, and the simulation results suggest that the surround gate structure is the appropriate approach. In terms of geometry, the cylindrical surround gate shows a 7% higher field than the square-shaped quadruple gate. The cylindrical shape of the gate is readily achievable by thermal oxidation and subsequent annealing because the sharp corners of the silicon surface tend to become smooth to minimize the surface energy. Ultimately, the surround gate intensifies the electric field by a factor of 2.2 compared to the single gate. The vacuum gap of the NVCT is not visible from the scanning electron microscope (SEM) image because the gap is fully hidden by the gate (Figure 1e). Therefore, the existence of the gap and related information are indirectly inspected from a dummy sample by skipping the gate formation step (Figure S2) and measuring the drain current (Id) versus drain voltage (Vd). A control sample was coprocessed by omitting the nanowire width reduction process in order to prove the nanogap formation. Figure 3a compares the drain current characteristics at a gate voltage of 3 V for devices with and without the nanogap. The control sample without the gap is not a normal transistor because the entire channel of the nanowire is highly doped with the same concentration of the source and the drain electrodes; it is rather a current conducting resistor showing a

linear increase of drain current with the drain voltage. The high conductivity and Ohmic behavior as shown are anticipated if the channel is contiguous with the material (silicon). In contrast, the device with the gap shows exponential Id−Vd characteristics, which is different from that of the nanowire, thus offering proof for the existence of the gap. It is important to clarify whether the carrier transport of the present device follows the designed tunneling mechanism or any other parasitic transport mechanisms such as diffusion and drift. This requires examining the current−voltage characteristics to fit the respective models. The Fowler−Nordheim (FN) tunneling characteristics relating current I and voltage V are modeled as I = aV2 exp(−b/V) where a and b are constants (Section 2 of SI). This model can be recast as a linear equation: ln(I/V2) = ln(a) − b(1/V). Therefore, a device showing linearity in the ln(I/V2) versus 1/V plot signifies that FN tunneling is the dominant carrier transport mechanism (Figure 3b). However, a nonlinear or a two slope pattern is seen in the present FN plot, which may signify the presence of two possible emitting spots.22 The current in the lower electric field region could be from a local protrusion of the silicon or defective surface states, and then the current in the higher electric field region may be mainly from the sharp emitter tip. The FN curves with two slopes have been theoretically explained22 as well as experimentally observed from different field emission devices based on GaN and carbon nanotubes.23,24 In the gate-induced field emission mode, the gate voltage is scanned for various drain voltages, and the drain current versus gate voltage plot shows a typical transfer characteristic (Figure 3c). A positive gate voltage is able to extract electrons from the source even at a small drain voltage of 0.05 V. The excellent gate-to-source coupling here enables electron emission even at low drain voltages, and the turn-on gate voltage is 2 V. Though the gate voltage is efficient to extract the source electrons, the drain terminal collects the most current rather than the gate intercepting the current since the gate dielectric blocks such leakage. The gate leakage current is just of the order of pA, which is 106 times smaller than the drain current. As the drain voltage increases, the drain current increases accordingly and a drain current of 3 μA is attained at a gate voltage of 5 V. The statistical distribution of the Id−Vg characteristics from 40 measured devices is shown in Figure S3. The scaling law in local field model suggests that the narrow gap increases the electric field and thus the tunneling efficiency.25 As the vacuum gap of the NVCT is decreased from 200 to 50 nm, the turn on C

DOI: 10.1021/acs.nanolett.6b04363 Nano Lett. XXXX, XXX, XXX−XXX

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Figure 4. Electrical characteristics under various harsh environments. (a) Drain current versus gate voltage characteristics at room temperature and 200 °C. Turn-on voltage and drain current for various total doses of (b) proton radiation and (c) γ radiation.

emission current above the threshold voltage is indeed several orders of magnitude higher; this confirms the impact of the parasitic path is solely formation of the parasitic leakage route and that parasitic current is minimal and does not contribute to the field emission current. The performance of conventional semiconductor devices is susceptible in harsh environments. Electrons interact with atoms in a semiconductor channel through crystal-lattice scattering. Furthermore, exposure to high temperature and radiation environments ionizes the atoms and generates electron−hole pairs in the channel, which can cause unexpected errors or even catastrophic device failure in the case of conventional electronics.28 The temperature of a semiconductor chip can reach over 100 °C through Joule heating. A small amount of radioactive contaminant contained in chip package constantly releases ionizing radiation.29,30 Therefore, semiconductor chips have an intrinsic risk of failure due to these ionizing effects. Since all solid-state devices suffer from such noise and distortion, noise-aware design efforts with area overheads are necessary. Especially, the noise-aware design criteria are even more critical for harsh environment military and space applications. In contrast, vacuum devices do not suffer from such errors since scattering and ionization events are absent. At 200 °C, where the silicon based CMOS most likely loses its function, the NVCT shows nearly identical I−V characteristics at room and high temperatures (Figure 4a). At high temperatures, the drive current of the FETs tends to degrade due to mobility reduction from phonon scattering. In contrast, the drain current of the NVCT is found to increase slightly due to the addition of free electrons from thermionic emission. However, the measured drain leakage current and the subthreshold slope at the drain voltage of 2 V (Figure 4a) are 800 pA and 620 mV/dec at room temperature and 23 nA and 880 mV/dec at 200 °C, which are not consistent with the widely accepted benefit of high-temperature immunity of the field emission device. The increase in drain leakage and the subthreshold slope with temperature is far greater than our perception based on the inherent insensitivity of FN tunneling mechanism. However, this drain leakage current anomaly in the subthreshold regime was mainly through a parasitic path formed by the silicon bulk region underneath the gate. Such a parasitic path starts to contribute to the total current at elevated temperatures. As a result, the drift-diffusion mechanism due to the bulk route starts to impact the subthreshold characteristics of the device, which implies that the NVCT needs to be

voltage does not shift, but the drain current increases by 78% (Figure S4), implying the benefits of further device scaling. The drain current of 3 μA reported here is the highest drive current at the lowest drive voltages until now for vacuum devices with nanoscale dimensions. Table S1 (see SI) provides a comparison against previous studies for drive current, on−off ratio, and transconductance. The transconductance of the surround gate device here is 34 μS per emitter tip. This performance is not only better than other silicon based vacuum devices but also when compared to graphene vacuum transistors.26 Further performance improvement may be derived from further device scaling, work function engineering of silicon tips, and electrode materials with a better work function. The current flow is limited by the small size of the emitter tip even though a source pad of similar size as in conventional transistors is used here. Since the source pad can accommodate a large number of emitter tips, the use of an array of emitters can help to increase the drive current and transconductance. The clearest advantage for vacuum devices lies in their ability to operate under harsh environments without a performance loss, as will be shown later. The sub-5 V operation achieved above is relevant to gas ionization as there is always a small probability of free electrons colliding with gas molecules even under vacuum conditions. If this impact knocks a bounded electron of the gas molecule, then the ionized molecules can bombard onto the electrode which is known to be a major lifetime limiter in vacuum devices.27 The first ionization potential of most gas molecules is slightly higher than 10 eV as shown in Figure S5. Therefore, the device operating under 5 V will rarely acquire enough energy for ionization. Given the fact that parasitic paths through the silicon bulk region may exist, the possibility of such charge conduction through the parasitic route needs to be investigated in order to confirm that the observed data is solely or dominantly from the vacuum channel and not from any parasitic routes. To assess this, a layout having only the plain source and the drain without the field emitting tip was drawn and cofabricated as a control device along with the NVCT (Figure S6a). The pad size and the source and drain process are identical for both the control device and the NVCT. No gate effect in the control device is seen in Figure S6b as the current is nearly constant over the entire gate voltage scan. The drain leakage current level of the NVCT, as given in Figure 3c (the current at VG = 0 V), is similar to that of the control device seen in Figure S6b. The D

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fabricated on silicon on insulator wafers. Further details on this are provided in Section 5 of the SI. There are three major categories of radiation-induced damages: single event effect, total ionizing dose (TID), and displacement damage (DD).31 The single event effects caused by an energetic particle can take on many forms such as single event upset and single event latch up, which are soft-errors and nondestructive. The single event effects in CMOS are typically caused by direct ionization, i.e., if a high energy proton or heavy ion passing through the semiconductor material deposits sufficient charge, primarily in the depletion region, it can cause the device to malfunction. However, single event effects cannot even be defined in the case of the NVCT as no depletion region exists in the channel. Both the single event effects and the TID effects are from ionizing radiation. While the single event effects are the cause for instantaneous failure mechanism, the TID is a long-term radiation effect that can cause turn-on voltage shift and increase in device leakage. The TID damage in FETs primarily affects the insulator regions such as the gate oxide and field oxide layers. The ionized charges in these insulators tend to be trapped at either the interfaces or in the bulk region and these localized charges are cumulative. Whereas the channel region of the FET is surrounded by field oxide or gate oxide, the metallic gate fully surrounds the vacuum channel of the NVCT preventing any contact with the insulating material. In this sense, the total ionizing dose effects may be trivial here. Nevertheless, the impact was examined by exposure to γ radiation. Total dose levels of 1, 10, and 100 KRad cause no change in the turn-on voltage and the drain current (Figure 4b), which confirms that the NVCT is robust against ionizing radiation. The displacement damage is related to the displacement of atoms or defect generation in the lattice of the irradiated materials by energetic particles. If the energy transferred to the atom is high enough, the atom can be knocked free from its lattice site to an interstitial site. Therefore, the displacement damage is a more likely factor to degrade the vacuum device as it may alter some properties of the source and drain. Therefore, displacement damage test was carried out by exposing to proton radiation. Proton doses of 0.1, 0.3, 0.5, 1, and 5 Mrad do not result in noticeable shift in the turn-on voltage and the drain current (Figure 4c). Some traveling distance is necessary in order to transfer the momentum into the lattice to cause the cascade and clustered defects. The few tens of nanometer dimensions in the source and drain in the NVCT can be considered to be transparent to proton radiation. In other words, most of the particles can bypass the nanostructure without losing their energy. A nanoscale vacuum channel transistor configured with a cylindrical channel fully surrounded by the gate was fabricated on 8″ wafers using conventional silicon integrated circuit technology. The use of cylindrical gate-all-around structure together with a vacuum channel length of 50 nm, which is less than the mean-free-path of air in atmospheric pressure, results in sub-5 V operation and 3 μA drive current. The device is found to be robust against high temperature and ionizing radiation. The nanoscale vacuum transistor can be one of the candidates for electronics beyond the Moore’s law era in addition to applications in high frequency devices, THz electronics, radiation tolerant space electronic circuits, and deep space communications.

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ASSOCIATED CONTENT

* Supporting Information S

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.6b04363. Details on the fabrication process, fundamental FN tunneling mode, device characterization, radiation tests and simulations, and a comparison against previously published vacuum devices (PDF)

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]; phone: +1 650 604 3985. ORCID

Jin-Woo Han: 0000-0002-5118-1310 Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS The authors acknowledge Jonathan Pellish and Jean-Marie Lauenstein from NASA Goddard Space Flight Center, Yuri Griko of NASA Ames Research Center, and Paul Wakabayashi from the University of California, Davis Crocker Nuclear Laboratory for their help with the radiation measurements.

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REFERENCES

(1) Koomey, J. G.; Berard, S.; Sanchez, M.; Wong, H. Ann. Hist. Comput. 2011, 33, 46−54. (2) Gaertner, G. J. Vac. Sci. Technol., B: Nanotechnol. Microelectron.: Mater., Process., Meas., Phenom. 2012, 30, 060801. (3) Utsumi, T. IEEE Trans. Electron Devices 1991, 38, 2276−2283. (4) Baccarani, G.; Wordeman, M. R.; Dennard, R. H. IEEE Trans. Electron Devices 1984, 31, 452−462. (5) Driskill-Smith, A. A. G.; Hasko, D. G.; Ahmed, H. Appl. Phys. Lett. 1997, 71, 2845−2847. (6) Ieong, M.; Doris, B.; Kedzierski, J.; Rim, K.; Yang, M. Science 2004, 306, 2057−2060. (7) Spindt, C. A.; Holland, C. E.; Rosengreen, A.; Brodie, I. IEEE Trans. Electron Devices 1991, 38, 2355−2363. (8) Park, J. H.; Lee, H. I.; Tae, H. S.; Huh, J. S.; Lee, J.-H. IEEE Trans. Electron Devices 1997, 44, 1018−1021. (9) Park, S. S.; Park, D. I.; Hahm, S. H.; Lee, J. H.; Choi, H. C.; Lee, J. H. IEEE Trans. Electron Devices 1999, 46, 1283−1289. (10) Han, J. W.; Oh, J. S.; Meyyappan, M. Appl. Phys. Lett. 2012, 100, 213505−3. (11) Han, J. W.; Oh, J. S.; Meyyappan, M. IEEE Trans. Nanotechnol. 2014, 13, 464−468. (12) Pirio, G.; Legagneux, P.; Pribat, D.; Teo, K. B. K.; Chhowalla, M.; Amaratunga, G. A. J.; Milne, W. I. Nanotechnology 2002, 13, 1−4. (13) Gangloff, L.; Minoux, E.; Teo, K. B. K.; Vincent, P.; Semet, V. T.; Binh, V. T.; Yang, M. H.; Bu, I. Y. Y.; Lacerda, R. G.; Pirio, G.; Schnell, J. P.; Pribat, D.; Hasko, D. G.; Amaratunga, G. A. J.; Milne, W. I.; Legagneux, P. Nano Lett. 2004, 4, 1575−1579. (14) Lee, B. H.; Kang, M. H.; Ahn, D. C.; Park, J. Y.; Bang, T.; Jeon, S. B.; Hur, J.; Lee, D.; Choi, Y. K. Nano Lett. 2015, 15, 8056−8061. (15) Lee, B. H.; Hur, J.; Kang, M. H.; Bang, T.; Ahn, D. C.; Lee, D.; Kim, K. H.; Choi, Y. K. Nano Lett. 2016, 16, 1840−1847. (16) Jennings, S. G. J. Aerosol Sci. 1988, 19, 159−166. (17) Higuchi, T.; Maisenbacher, L.; Liehl, A.; Dombi, P.; Hommelhoff, P. Appl. Phys. Lett. 2015, 106, 051109−4. (18) Diamant, G.; Halahmi, E.; Kronik, L.; Levy, J.; Naaman, R.; Roulston, J. Appl. Phys. Lett. 2008, 92, 262903. (19) Ferry, D. K. Science 2008, 319, 579−580. (20) COMSOL Multiphasics, Version 3.3, Available: http://comsol. com. E

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(21) Pescini, L.; Tilke, A.; Blick, R. H.; Lorenz, H.; Kotthaus, J. P.; Eberhardt, W.; Kern, D. Adv. Mater. 2001, 13, 1780−1783. (22) de Assis, T. A.; Dall’Agnol, F. F.; Andrade, R. F. S. J. Phys. D: Appl. Phys. 2016, 49, 355301. (23) Evtukh, A.; Yilmazoglu, O.; Litovchenko, V.; Semenenko, M.; Kyriienko, O.; Hartnagel, H. L.; Pavlidis, D. J. Vac. Sci. Technol., B: Nanotechnol. Microelectron.: Mater., Process., Meas., Phenom. 2010, 28, C2A72−C2A76. (24) Journet, C.; Marchand, M.; Benoit, J. M.; Yakobson, B.; Purcell, S. T. MRS Online Proc. Libr. 2009, 1204, 1204−K01. (25) Binnig, G.; Rohrer, H.; Gerber, Ch.; Weibel, E. Appl. Phys. Lett. 1982, 40, 178−180. (26) Wu, G.; Wei, X.; Zhang, Z.; Chen, Q.; Peng, L. Adv. Funct. Mater. 2015, 25, 5972−5978. (27) Chang, T. H.; Hsieh, P. Y.; Kunuku, S.; Lou, S. C.; Manoharan, D.; Leou, K. C.; Lin, I. N.; Tai, N. H. ACS Appl. Mater. Interfaces 2015, 7, 27526−27538. (28) Dodd, P. E.; Shaneyfelt, M. R.; Schwank, J. R.; Felix, J. A. IEEE Trans. Nucl. Sci. 2010, 57, 1747−1763. (29) International Technology Roadmap for Semiconductor 2013, Available: http://public.itrs.net. (30) Baumann, R. C. IEEE Trans. Device Mater. Reliab. 2005, 5, 305− 316. (31) Schwank, J. R.; Shaneyfelt, M. R.; Dodd, P. E. IEEE Trans. Nucl. Sci. 2013, 60, 2074−2100.

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