Overestimation of Carrier Mobility in Organic Thin Film Transistors Due

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Overestimation of Carrier Mobility in Organic Thin Film Transistors Due to Unaccounted Fringe Currents Ke Pei, Ming Chen, Zhiwen Zhou, Hanying Li, and Paddy Kwok Leung Chan ACS Appl. Electron. Mater., Just Accepted Manuscript • DOI: 10.1021/acsaelm.8b00097 • Publication Date (Web): 19 Feb 2019 Downloaded from http://pubs.acs.org on February 23, 2019

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ACS Applied Electronic Materials

Overestimation of Carrier Mobility in Organic Thin Film Transistors Due to Unaccounted Fringe Currents Ke Pei†, Ming Chen†, Zhiwen Zhou†, Hanying Li‡, and Paddy Kwok Leung Chan*,† Pei, K.; Chen, M.; Zhou, Z.; Prof. Chan, P. K. L. †Department of Mechanical Engineering, The University of Hong Kong, Pokfulam Road, Hong Kong Li, H. ‡Department of Polymer Science and Engineering, Zhejiang University, Hangzhou 310027, P. R. China E-mail: [email protected]

ABSTRACT: Charge carrier mobility is one of the important parameters to measure and compare the behavior of different organic transistors. A high carrier mobility is essential for the organic transistors to operate at a high frequency. Recently, there have been discussions on the mobility overestimation due to gate bias dependent Schottky contacts which lead to severe nonlinearities in the current-voltage characteristics, i.e., the double-slope feature. In addition, an accurate evaluation of the carrier mobility from the transfer curves requires accurate parameters such as channel dimensions or dielectric capacitance. Many of the organic field-effect transistors (OFETs) reported in the literature employ unpatterned semiconductor active layers or gate/gate dielectrics where the effective channel dimensions significantly deviate from the values defined by the source-drain electrodes due to the fringe effect. To reveal the importance of the fringe effect on the mobility evaluation, here we perform a systematic investigation of OFETs with vacuum-deposited active layers in relation to the fringe effect, followed by the same analysis of solution-processed OFETs with tunable crystal morphology.

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By continuously narrowing down the active layer towards the actual channel region defined by the source-drain electrodes, we show the carrier mobilities are 110 % and 60 % overestimated in the vacuum deposited and solution-processed devices, respectively, even with ideal linearity in the transfer curves. Herein, we suggest a model to evaluate the degree of mobility overestimation in these two families of OFETs and provide the guidelines for the design of the device geometry and channel dimensions to minimize mobility overestimation induced by the fringe effect. In our solutionprocessed OFETs, we conclude that a large channel width to length ratio over 20 is essential to alleviate the fringe current outside the channel, while channel ratio greater than 40 is needed for the OFETs with vacuum-deposited semiconductor layers.

KEYWORDS: channel dimension, fringe effect, mobility overestimation, organic transistor, C-factor, good linearity

INTRODUCTION Organic field-effect transistors (OFETs) have attracted considerable attention in electronic device applications including flexible displays,1 sensors,2,3 health monitoring tag,4 radio frequency identification,5 and memories.3,6 To date, the applications and the corresponding circuits of these OFETs are still on a relatively small scale as the operating speed is limited. Charge carrier mobility (), describing how fast the charges can move under an applied electric field, is one of the most important parameters to evaluate the OFET performance or to benchmark the electrical properties of organic


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semiconductors. Enormous progress has been made to increase the value of  including developing emerging materials and utilizing novel fabrication techniques.7-9 Being in parallel with pursing high mobility semiconductor materials and device structure optimizations, the research communities recently raised concerns on erroneously reported high mobility devices, and a reliable approach to extract the mobility is highly desired.10-17 As the carrier mobility is an important feedback channel for the rational molecular design, the reporting of inflated mobility will retard the development of some materials or the organic transistor field. One important factor leading to mobility overestimation in the OFETs is the gated Schottky source-drain contacts which usually results in a pronounced double-slope feature in the transfer curves.10-15 In the current work, instead of the non-linear transfer curves, we are focusing on the mobility overestimation caused by problematic channel dimensions with unpatterned semiconductor layers even if it has ideal transfer characteristics. One may notice that even in the case of ideally linear transfer curves, the strongly gate field tunable depletion width at the organic semiconductor and metal junction in highly disordered organic semiconductors can also result in a mobility overestimation,13 which is beyond the scope of this work. By using these ill-designed electrode masks on unpatterned active layers, the OFETs can show a 110 % overestimation in the carrier mobility. Although it is usually being ignored, these findings clearly point out the importance of proper choice of electrode masks and the patterning of the organic semiconductors in the OFETs fabrication. We will suggest the



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guidelines in the design of device geometry and channel dimension for the more accurate and reliable mobility evaluation which we believe can benefit the OFETs field. In the standard expression of the drain current (IDS) in the OFETs, the apparent mobility (µapp) in the saturation (Eq. (1)) and linear regimes (Eq. (2)) are given as, W app , sat Ci (VGS  VTH ) 2 2L applicable at VGS  VTH  V DS I DS 

I DS 

(1)

 V2  W app ,lin Ci (VGS  VTH )VDS  DS  L 2  

applicable at VGS  VTH  V

(2)

DS

where VTH is the threshold voltage, VDS and VGS are the drain voltage and gate voltage respectively, Ci is the oxide areal capacitance. In Eq. (1) and (2), if peripheral channel as shown in the schematic drawing in Figure 2a exists, the channel width (W) and length (L), which are normally defined by the source-drain electrode, cannot reflect the actual channel dimension accurately. The equations for the IDS in the saturation and linear regimes should be modified into, I DS  I ch  I F 

W W true, sat Ci (VGS  VTH ) 2  sat true, sat Ci (VGS  VTH ) 2  2L 2 Lsat

(3)

and I DS  I ch  I F =

  V2  W V2  W true,lin Ci (VGS  VTH )VDS  DS   lin true,lin (VGS  VTH )VDS  DS  L 2  Llin 2   

(4)

where IF is the fringe current and µtrue is the true carrier mobility of the channel. W* and L* are the modified channel width and length contributed by the peripheral channels. Here we define the correction factor (C-factor) for the ill-designed source-drain 4 ACS Paragon Plus Environment

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electrodes as the ratio of W*/L* to the apparent channel dimension, W/L, i.e. C-factor = (W*/L*)/(W/L). In the ideal situation, the C-factor should be equal to zero. By direct comparison between Eq. (1) and Eq. (3) in the saturation regime, and Eq. (2) and Eq. (4) in the linear regime, we can derive the mobility overestimation as,

app / true 

(W * / L* )  1  C  factor  1 (W / L)

(5)

Table 1 summarizes some of the recent reports of the OFETs with the W/L at 10 or smaller which may have potential of suffering from fringe effect.18-30 In these literature, no information is provided about patterning of the semiconductor layers or the included optical pictures of the device under test also show no patterning. For those devices with a continuous film morphology, they may have the risk of mobility overestimation in general. We have also provided Table 2 to outline the devices with W/L smaller than ten which should have low risk of suffering from fringe effect due to the patterning of the semiconductor thin films or using naturally discontinuous morphology of the organic crystals.31-35 Different from the thermally evaporated organic thin films which can be patterned by the shadow masks, the direct patterning of solution-processed organic active layers is indubitably more challenging. Other than the high-resolution inkjet printing or gravure printing,36,37 post-deposition lithography patterning is the common technique for the large area crystal film for the practical fabrication of high density OFETs.33,38 In the large area solution-based methods like blade shearing and bar-coating,2,10,39,40 Si/SiO2 is the dominating substrate due to the low surface roughness and easily tunable



surface energy by the self-assembly monolayers (SAM).41 The morphology of the deposited crystals is governed by different factors including substrate surface energy, the binding energy of molecules, solvent evaporation rate, shearing speeds, etc. Different forms of crystals varying from needles, strips to continuous film have been demonstrated.10,31,42 The various forms of the organic crystals will induce different levels of C-factors in the mobility evaluation. Similarly, the C-factors of the thermally evaporated organic thin films would also be affected by the material dependent properties such as grain size or contact quality with metal electrodes. In the current work, the influence of fringe effect on mobility calculation in the OFETs with thermally evaporated semiconductors was first systematically studied. Following the same analysis, the different C-factors in the solution-processed OFETs will be also examined.

RESULTS AND DISCUSSION We

adopted

b]thiophene

vacuum-deposited (C10-DNTT),

(2,9-didecyl-dinaphtho[2,3-b:2′,3′-f]thieno[3,2-

N,N′-1H,1H-perfluorobutyldicyanoperylene-carboxydi-

imide (PDIF-CN2) and solution-processed 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) as the active layers of OFETs with different W/L ratios. All the devices are fabricated on the Si/SiO2 substrates. To ensure the mobility overestimation in the devices is not due to the gated Schottky contacts, we first evaluate the contact resistance of the device. The intrinsic channel mobility (µ0) and contact resistance (RC) can be extracted from the linear slope and y-intercept of the channel-width-normalized total resistance (Rt W) against the channel length (L) in the transmission line method 6 ACS Paragon Plus Environment

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(TLM), respectively. The OFETs based on C10-DNTT have shown high mobility, excellent ambient stability, and decent contact-injection with gold electrodes.43,44 The bottom gate top source-drain contacts configuration of the C10-DNTT OFET is shown in Figure 1a. The 40 nm thick C10-DNTT layer was deposited on the octadecyltrichlorosilane (OTS) treated Si/SiO2 substrates. During the semiconductor deposition, the substrate temperature was maintained at 80 oC and top gold source-drain electrodes were deposited under shadow mask with different channel lengths. The surface morphology was characterized by atomic force microscope (AFM) as shown in Figure 1b, some nanosprouts features are found in the continuous C10-DNTT film due to different crystallinity.3,44 Schottky barriers usually are present at the heterojunction between the organic semiconductors and metal electrodes, especially at the source injection region of the OFETs. If such interfacial contact resistance is dominating the transistor transfer characteristics, the measured current is basically modulated by the injection of charge carriers rather than their transport in the active channel. It will commonly induce the “kink” feature in the transfer curves when this contact resistance effect is largely modulated by gate bias near the threshold. Efficient charge carrier injection is crucial for high-performance OFETs.45-47 We utilized devices with channel lengths ranging from 100 µm to 500 µm with 50 µm as the interval in the TLM (Figure 1c). The corresponding transfer curves in the linear regime at each channel length were measured and plotted in Figure 1d, the variation of Rt·W with L can be expressed as,44

 RCW  RW t

L

(6)

0Ci VGS  VTH 7 ACS Paragon Plus Environment


The Rt·W decreases monotonically with decreasing the channel length. The slope of the linear fit yields the true carrier mobility without contact effect and the channel-widthnormalized contact resistance (RC W) is obtained from the intercept with the Y-axis by extrapolating the linear fit. Taking consideration of the fluctuation of the threshold voltages based on different channel length devices, at VGS – VTH = –75 V, we obtain µ0 = 8.09 cm2 V-1 s-1 and RC W = 298  cm (Figure 1e). The gate dependence of the channel resistances (Rch) significantly overwhelms that of RC reveals that the output current was modulated by the channel transport (Figure S1a). From the transfer curves in Figure 1d, we plotted the apparent linear mobility dependence (VDS = –5V) on VGS in Figure 1f. In the whole bias range, the Rch value is at least 3 times of the RC (Figure S1b), hence it confirms the device is operating at the classical transport of charge carrier mode. The devices are the suitable candidate for investigating the peripheral channels and the fringe effect induced by the ill-designed electrode dimensions. The origin of the peripheral channels is the accumulation of the charges in semiconductor layer outside the desired channel area induced by the electric field. Such charge accumulation is particularly strong for the unpatterned device operating under low frequency where a sheet of charges forms along the whole semiconductor/dielectric interface, regardless of top electrode size. As the transfer curves used for extraction of the carrier mobility are measured under static DC gate bias, a number of these accumulated charges outside the channel area will also contribute to the source-drain current through the peripheral channels if the channel area is not precisely defined by the source-drain electrodes. As a result, the extracted carrier mobility would be 8 ACS Paragon Plus Environment

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overestimated. This accumulation of charges under a negative gate bias at low frequency can also be confirmed by the C-V measurements shown in Figure S2. It shows the organic/dielectric films have the same overall capacitance and areal capacitance (normalized by the area of the organic semiconductor) regardless of the top electrode area. It confirms the charges are distributed uniformly at the semiconductor/dielectric interface while the structure is under charge accumulation at low frequency (≤ 100 Hz). Other than patterning the semiconductor layer, similarly, the fringe effect can also be eliminated by patterning the gate/gate insulator and the corresponding results are shown in Figure S3. To regulate the levels of the fringe effect in the OFETs, a probe with a tip diameter of 5 m is used to directly scratch/pattern the semiconductor film on a micrometer resolution XY translation stage (Figure 2a). As shown in the AFM image in Figure 2c, a sharp trench with a width of 8 µm and a height of 40 nm can be clearly identified in the C10-DNTT active layer, which indicates the semiconductor film was completely isolated after scratching. Starting from the outer region, we conduct multiple stepwise patterning on the semiconductor layer to define the channel area by continuously reducing the diffraction width (WD) as shown in Figure 2b. The corresponding I-V curve (Figure 2d and 2e) after each patterning is used to evaluate the apparent carrier mobility in the saturation and linear regime, respectively. The gap between each scratching is around 120 µm. The overestimation of the carrier mobility can be clearly observed by comparing the initial I-V characteristics curves with the last one. As the peripheral channel and fringe effect are suppressed while the effective 9 ACS Paragon Plus Environment


channel area is gradually restrained to the actual channel ratio (W/L) defined by the electrodes, the values of the apparent mobility (µapp) will also decrease to the actual value (µtrue). Although such fringe effect is commonly ignored, as shown in Figure 2h, the carrier mobilities are overestimated by more than a factor of two and decreases from 16.53 cm2V-1s-1 to 7.78 cm2V-1s-1 for the saturation regime and from14.78 cm2V-1s-1 to 6.85 cm2V-1s-1 for the linear regime in the device with a channel ratio of one. The

µapp/µtrue ratio obtained from the first and last I-V curves implies a maximum C-factor of 1.12 and 1.16 at the W/L = 1 in the saturation and linear regime respectively. It is also important to note that the slopes of the transfer curves in Figure 2d and 2e remain unchanged after the first few patterning of the semiconductor, and they start to decrease only when the scratching is getting close to the channel region. As shown in Figure 2f, the apparent mobility remained around µsat = 16.53 cm2V-1s-1 and µlin = 14.78 cm2V1s-1 after

the initial three scratches, and at an effective diffraction width (WD,eff, defined

in Figure 2b) of 1860 µm, the mobilities start to drop gradually to the true mobilities. As expected, although the accumulated carriers may cover a wide region at the semiconductor/dielectric interface, they only drift and contribute to the IDS when they are under a transverse electric field which is the reason why a pair of poorly designed electrodes would have a large WD,eff. The designed evaluation process of fringe effect can be explained by the schematic images in Figure 2b and Movie S1 (Supporting Information). In addition to the results of devices with the W/L = 1 as shown in Figure 2d and 2e, we also study the fringe effect in devices with other W/L ratios (W/L = 2, 4, 8, 20, 10 ACS Paragon Plus Environment

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40) in the same manner (see Supporting Information Figure S4). The WD,eff keeps monotonically decreasing with increasing W/L ratio, from 1860 µm in the W/L = 1 device to 285 µm in the W/L = 40 device (Figure 2g, detailed results can be found in Figure S5). Figure 2h plots the mobility overestimation as a function of the W/L ratio. After fitting the results to Eq. (5), we can determine the C-factor over the entire range of channel ratios and provide a range of C-factors to describe the extent of fringe effect on mobility overestimation, as indicated by the fitting results of the maximum and minimum values of the C-factor. The results show a maximum C-factor of 1.16 and 1.12 at W/L ≤ 4 and a significant decrease to its minimum value of 0.15 and 0.11 at W/L ≥ 20 in the linear and saturation regimes respectively, the fitted C-factors are listed Table 3. The relatively smaller C-factor value in the saturation regime may be related to the non-uniform distribution of electrical field caused by pinch-off in the channel and suppress the contribution to fringe current in the saturation regime. Since in the mobility extraction, the gate-source voltage in the transfer curves scan goes beyond the threshold voltage under both linear and saturation operations, where the charge accumulation is sufficient to induce saturation of capacitance as shown in Figure S2d to S2f. Therefore, the gate-source voltage dependence on the fringe effect is relatively minor and can be neglected. We also study how the side-width of the top source-drain electrode influences the fringe effect on mobility overestimation under the same W/L ratio of one (See Supporting Information Figure S7). It can be observed that doubling the side-width of the electrodes in W/L = 1 device results in a more severe fringe effect as the distribution 11 ACS Paragon Plus Environment


route for the fringe electric field becomes wider, and the C-factor can even reach 1.53 and 1.59 for µsat and µlin respectively. However, the side-width induced overestimation effect would be suppressed when the W/L ratio reaches eight (Figure S8), where the electric field is mostly confined to the channel region and increasing the side-width has no further contribution to the fringe current. A similar investigation on n-type OFETs based on vacuum-deposited PDIF-CN2 semiconductor is described in the Supporting Information (Figure S9 and S10). Different from the OFETs with vacuum-deposited semiconductor whose active layers can be easily patterned by shadow masks, patterning of solution-processed organic semiconductors usually requires pre-deposition treatment such as surface energy patterning by SAM,48 and elastomeric stamping49 or post-deposition lithography patterning.50 To date, the process of patterning the active layers in the solutionprocessed OFETs has not yet been standardized. Many of the reported studies do not take any measures to confine the semiconductor layer to the desired channel region defined by the metal electrodes, therefore the accuracy of the reported mobility values is still a big concern. The advantage of solution-based deposition techniques is their strong capability to tune the resulting film morphology and crystal size, thus the devices may lead to different levels of C-factor in the fringe effect study. Here, we use bladecoated TIPS-pentacene OFETs as an example to study the fringe effect on mobility overestimation. Compared with other solution-processing methods like dip-coating51 and spin coating,52 solution shearing in the evaporation region can provide better control of the film morphology, molecular packing and crystallinity by regulating 12 ACS Paragon Plus Environment

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shearing speed, substrate temperature, solvents, and solute concentration.10,41 Here the substrate temperature was fixed at 60 ℃ and the concentration was 8 mg mL-1 in mxylene.10 The influence of the shearing speed on the crystal morphology can be characterized by the polarized optical microscope (POM) and AFM images in the Figure 3a to 3e. A slow coating speed of 75 µm s-1 yields organic crystals with a continuous film and millimeter-scale crystal domains and only some tiny voids are present in the film (Figure 3a and 3b). In contrast, at a faster shearing speed of 350 µm s-1, the obtained film becomes discontinuous with micro-gaps along the shearing direction which separate the dendritic strips (Figure 3d and 3e). It can be observed that when the shearing speed increases from 75 to 350 µm s-1, the thickness of the deposited layers decreases from 40 to 11 nm (Figure 3c and 3f), and at the same time the surface coverage of TIPS-pentacene drops from 98 % down to 75 %. The field-effect mobilities parallel to the shearing directions are measured and compared, similar to the previously reported solution-shearing TIPS-pentacene OFET devices.42 The contact resistances of the TIPS-pentacene devices are also characterized and shown in Figure S11 and S12. In terms of devices with continuous film morphology, the mobility values extracted from both the saturation (Figure 3g) and linear (Figure 3h) regimes in the W/L= 1 device gradually decrease to the true mobilities (µsat= 0.78 cm2V-1s-1, µlin= 0.56 cm2V1s-1),

showing an overestimation of 62 % and 69 % for µsat and µlin respectively. The

WD,eff of 945 µm obtained in Figure 3i indicates the fringe current extend over 945 µm from the source-drain electrodes in the unpatterned devices. The smaller WD,eff compared with the C10-DNTT film is mainly due to the lower conductivity (mobility) 13 ACS Paragon Plus Environment


of the solution-processed TIPS-pentacene material. We also performed similar measurements on the devices to study the W/L ratio’s influence on the mobility overestimation (Figure S13 and Figure S14). Both the WD,eff and mobility overestimation monotonically decrease with increasing geometrical W/L ratio (Figure 3j and 3k). When the W/L reaches 20, the fringe effect becomes very weak with a WD,eff of only 30 µm and the mobility overestimation drops below 10 %. The C-factor values of the TIPS-pentacene devices also decrease from maximum values of 0.74 and 0.62 at W/L ≤ 4 to 0.05 and 0.02 at W/L ≥ 8 in the linear and saturation regime respectively (Table 3). On the contrary, in the discontinuous strip form TIPS-pentacene devices, all the transfer curves upon multiple scratching overlap well and show no inflation of the output current (see Figure 3l and 3m). The µsat and µlin maintained at 0.65 and 0.45 cm2V-1s-1 respectively. As plotted in Figure 3n, the devices in different W/L ratios show only 5 % inflations on the true mobility which are just falling into the margin of measurement error (Figure S15). This observation suggests that the strip form organic crystals can provide reliable carrier mobility without the effect of peripheral channels. The micro-gaps in the film block the fringe current and the as-fabricate film can be regarded as naturally patterned semiconductor layer. Another important observation is that the C-factor values of thermally evaporated thin film devices are higher, indicating a more severe fringe effect due to the better uniformity in polycrystalline thin film morphology, while solution-processed TIPS-pentacene film exhibits large angle grain boundaries, large degree of anisotropy in electrical properties53 and relatively large contact resistance, which may hinder the fringe carriers from contributing to the output 14 ACS Paragon Plus Environment

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current, therefore weaken the fringe effect on mobility overestimation. The contact resistance and fringe effect are actually two independent sources to cause miscalculation of mobility. In our devices, due to the long channel and moderate carrier mobility, the channel resistance would outweigh the contact resistance, therefore, the mobility overestimation would only originate from fringe effect. We have assessed critically how the unaligned devices can lead to over 110 % mobility overestimation due to fringe effect, even if the devices exhibit good linearity of electrical characteristics. The overestimation may not be as severe as double-slope linked one whose mobility can overestimate by a factor exceeding ten.11-13 Nonetheless, the systematical study of the fringe effect is still indispensable as more accurate mobility values are vigorously pursuing in the community to approach the targeted mobility values in order of 10 cm2 V-1s-1 for applications in commercial electronic circuits. To allow the interested readers to compare the true mobility values of all thin films reported in our work to those of others, we provide the thin film morphology by AFM and molecular packing by XRD (Figure S16 and Table S1), as the thin film mobility is highly linked with its solid state, such as grain size and crystallite orientations. Some representative and reliable mobility values of the studied materials reported by other groups were also listed in Table S2. Although the carrier mobility may also affect by other parameters, such as semiconductor material purity, metal contact quality and device testing condition, the reference mobility values are extracted from devices without gated Schottky contacts and fringe effect.



The mobility overestimation as a function of apparent mobility and W/L ratio are plotted in Figure 4a and 4b. Based on the results, the high mobility devices with low contact resistance will more likely lead to larger mobility overestimation. Additionally, the appearance of fringe effect in the transistor devices may not be easy to verify in the literature if the subtle clues, such as functional layer alignment, W/L ratio and real device images, are not explicitly provided. To gain the reliability of mobility measurements in all OFETs in regard to the fringe effect, here we propose several suggestions on device geometry and channel dimension design in the device fabrication procedures. 1. All information about the device geometry should be explicitly included in each publication. For example, functional layer alignment (each layer patterning or not), channel dimension (length and width), a photograph of the device corresponding to the reported mobility value. This would allow the interested readers to judge whether the devices suffer from fringe effect. 2. To avoid the fringe effect, patterning and alignment of each layer of the device is appreciated (Figure 4e). In case of widely used unpatterable Si/SiO2 substrate, the semiconductor layer must be well-patterned (Figure 4c). 3. Extra cautions are required when fabricating solution-processed OFETs. Postpatterning such as tip scratching or laser etching is needed. If not, using a patterned gate/gate insulator substrate can also get rid of the fringe effect (Figure 4d).


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4. If the semiconductor or the gate dielectric cannot be patterned, try to use W/L ratio as large as possible (≥ 40 for vacuum-deposited and ≥ 20 for solutionprocessed semiconductors) in the source-drain electrodes geometry (Figure 4f). 5. When W/L ratio is fixed, better choose a smaller side-width of source-drain electrodes to minimize the spreading route of fringe current (Figure 4g). 6. If the anisotropicity of the mobility is unknown, try to make the film to be discontinuous or naturally-patterned so that the fringe current can be blocked (Figure 4h). By following these suggestions, the fringe effect on mobility overestimation can be minimized. Last but not least, although in this study we use small molecule OFETs as examples to study the fringe effect, most of our discussion and observations are not constrained by materials and should be also applicable to other emerging semiconductors based FETs, including polymers, inorganic oxides, hybrid perovskites, two-dimensional transition metal dichalcogenides and other monolayer devices.

CONCLUSIONS In conclusion, we have systematically studied the fringe effect on mobility overestimation for the organic thin film transistors. The C-factor can reach 1.16 and 0.74 under the W/L ratio of one for the transistors with vacuum-deposited semiconductors and solution-processed semiconductors, respectively. The mobility overestimation becomes more severe as the side-width of the source-drain electrodes increases. When using large W/L ratio metal masks, the C-factor can be minimized to



0.1 (W/L ≥ 40 for vacuum-deposited W/L ≥ 20 for solution-processed semiconductors), which implies a compromising practice of adopting large W/L ratio source-drain masks for solution-processed OFETs to minimize the fringe effect where patterning the semiconductor layer is still challenging. We also provide practical guidelines for rational device geometry and channel dimension design so that common pitfalls of fringe effect in the device fabrication can be avoided. We believe the accurate evaluation of carrier mobility will benefit the research community and also the further developments of the organic electronic devices.

MATERIALS AND METHODS Materials. The solvents and SAMs were obtained from Sigma-Aldrich. Silicon substrates with 300 nm silicon oxide were from Nam Kang Hi-Tec. The C10-DNTT and TIPS-pentacene are bought from Lumtec (99%). PDIF-CN2 is purchased from Polyera Corporation under the trade name of ActivInk N1100. All materials were used directly without further purification. Fabrication of OFET Devices. All the devices were fabricated on Si/SiO2 substrate. The heavily p-doped Si wafer with 300 nm thermally grown SiO2 layer were employed as the gate and dielectric layer respectively. The wafer surface was sequentially cleaned by ultra-sonication in deionized (DI) water, acetone and isopropanol (IPA) for 5 minutes and then O2 plasma for another 15 minutes, followed by SAM treatment. For vacuum-deposited devices, the substrates were followed by 1 mM OTS in toluene treatment for 16 hours. The C10-DNTT (PDIF-CN2) semiconductor was thermally 18 ACS Paragon Plus Environment

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evaporated onto the substrate in the base pressure of 1.5×10-6 torr at 80 ℃ (100 ℃ for PDIF-CN2) substrate temperature at a 0.02 nm s-1 deposition rate. In terms of solutionprocessed TIPS-pentacene devices, phenyl trichlorosilane (PTS) treatment was applied to the SiO2 surface by exposing the substrate to vapor of the liquid precursor at 140 ℃ in a vacuum chamber for 1 hour. During the blade-coating of TIPS-pentacene process, the substrate temperature was maintained at 60 ℃, the gap between the blade and the substrate was fixed at around 200 µm. Then ~10 µL solution containing 8 mg/mL TIPSpentacene in m-xylene was injected into the gap, followed by pulling the substrate at a setting speed on the moving stage. Afterward, the crystal film can be deposited onto the substrate. After coating, the crystal film was stored in a N2-filled glove box for 12 hours to remove the residual solvents. The devices were completed by depositing 50 nm Au source-drain

electrode

on

both

vacuum-deposited

and

solution-processed

semiconductors through shadow masks in various W/L ratios. The active semiconductor was patterned by scratching with a probe tip on a XY translation stage. For MIS structure on Al/Al2O3 substrate, the Al2O3 dielectric was fabricated by anodization of thermally evaporated Al gate described in our previous work.3 OFET Devices Characterizations. The semiconductor layers were patterned by scratching with a probe tip (EVERBEING INT’L CORP. T20-50 Tungsten, 5 µm in diameter) on a XY translation stage. The transfer curves of the OFETs were measured in a glovebox by a Keithley 2636B source-meter controlled by a LabVIEW program. The field effect mobilities in both saturation and linear regimes were extracted by using the equations IDS = W/2L·Ci·µ·(VGS-VTH)2 and µ = dIDS/dVGS·L/(W·Ci·VDS) respectively. 19 ACS Paragon Plus Environment


We use VGS in the whole VGS > VTH regime to fit the slope for mobility extraction. The W and L values for each W/L are provided in the Supporting Information together with the corresponding photographs of the measured devices. The POM images were taken by a polarized microscope Nikon Eclipse LV100N. The topography and thickness of the thin films were measured by using a Bruker MultiMode 8 AFM system. The C-V measurement were conducted by an Agilent 4284A impedance analyzer, and the areal capacitances of SAM-treated SiO2 are obtained around 11 nF cm-2 at 100 Hz (Figure S17). The XRD analysis of the thin films were obtained by a Rigaku SmartLab 9 kW.

ASSOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publications website. Contact resistance and channel resistance versus gate voltage in C10-DNTT based transistors, C-V measurements on Si/SiO2 substrate and Al/Al2O3 substrate, transfer curves and diffraction width of thermally-evaporated C10-DNTT based transistors upon each patterning, finite element model simulation on the potential distribution and the current streamlines in unpatterned transistors, the side-width of the top source-drain electrodes influence on the fringe effect caused mobility overestimation, contact resistance measurement of n-type PDIF-CN2, transfer curves of thermally-evaporated PDIF-CN2 based transistors upon each patterning, contact resistance measurements of blade-coated continuous and discontinuous TIPSpentacene based transistors, transfer curves and diffraction width of the continuous and discontinuous TIPS-pentacene based transistors upon each patterning, the solid state characterizations of organic thin films studied in this work, areal capacitance measurement of the dielectrics, table of thin film microstructural characteristics, and table of representative and reliable mobility values of the corresponding material in literature. The designed evaluation process of fringe effect by scratching the unpatterned semiconductor layers. (Movie S1). AUTHOR INFORMATION


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Corresponding Author *Email: [email protected] (P.K.L.C.). ORCID Hanying Li: 0000-0002-5841-6805 Paddy Kwok Leung Chan: 0000-0002-3166-2192 Notes The authors declare no competing financial interest. ACKNOWLEDGMENTS We gratefully acknowledge the support from General Research Fund (GRF) under Grant No. HKU 17204517, 17200314 and 17264016, the National Natural Science Foundation of China (NSFC) and the Research Grants Council (RGC) of Hong Kong Joint Research Scheme under Grant No.N_HKU715/14.

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Figure 1. 80 ℃ thermal-deposited C10-DNTT transistor without gated Schottky contacts. (a) Device structure. (b) AFM image of the C10-DNTT film, the scale bar is 500 nm. (c) Optical image of the devices for transfer line method (TLM), the scale bar is 500 µm. (d) Linear transfer curves in TLM measurement, VDS = –5 V. (e) Device total resistance as a function of channel length at various gate bias levels. The error bars are computed by averaging 3 devices measurements. (f) Linear carrier mobility as a function of gate bias. An averaged linear mobility of 6.90 cm2 V-1 s-1 was extracted by

µ = dIDS/dVGS·L/(W·Ci·VDS) in the whole |VGS| > |VTH| regime. The channel-width is fixed at 500 µm.


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Figure 2. Fringe effect on mobility overestimation of the C10-DNTT transistor. (a) Patterning the semiconductor layer by a probe tip scratching and numerical simulation of the current streamlines in the device with realistic σ = 1000 S/m (on-state conductivity) and VDS = –80 V. (b) Schematic images of multiple scratching on the semiconductor layer for fringe effect study. The diffraction width (WD) was illustrated by red arrows. (c) AFM image of C10-DNTT film after scratching by a probe tip, the scale bar is 5 µm. (d) Saturation transfer curves and (e) linear transfer curves measured after each scratching of the semiconductor, at VDS = –80 V and VDS = –5 V respectively. (f) Apparent mobility as a function of WD. (g) WD as a function of W/L ratio. (h) Mobility overestimation as a function of W/L ratio, the black and red line are Eq. (5) fit of the

µsat and µlin overestimation respectively. The obtained fitting minimum and maximum



C-factors are listed in Table 3. The error bars are derived by averaging 4 devices measurements.


Page 32 of 40

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Figure 3. Fringe effect study on mobility overestimation of blade-coated TIPSpentacene transistor. (a) POM and (b) AFM image of 75 µm/s shear-speed blade-coated TIPS-pentacene with continuous film morphology, the scale bars are 100 µm and 10 µm respectively. (c) Height profile of the thin film, indicating the thickness of ~40 nm. (d) POM and (e) AFM image of 350 µm/s shear-speed blade-coated TIPS-pentacene 33 ACS Paragon Plus Environment


with discontinuous micro-strip morphology, the scale bars are 100 µm and 10 µm respectively. (f) Height profile of the thin film, indicating the thickness of ~11 nm. (d) Transfer curves of continuous TIPS-pentacene devices in (g) the saturation regime and (h) the linear regime measured after each scratching of the continuous film, at VDS = – 80 V and VDS = –5 V respectively. (i) Apparent mobility as a function of diffraction width (WD). (j) WD as a function of W/L ratio. (k) Mobility overestimation as a function of W/L ratio, the black and red line are Eq. (5) fit of the µsat and µlin overestimation respectively. The obtained fitting minimum and maximum C-factors are listed in Table 3. Transfer curves of discontinuous TIPS-pentacene devices in (l) the saturation regime and (m) the linear regime measured after each scratching of the discontinuous film, at VDS = –80 V and VDS = –5 V respectively. (n) Mobility overestimation as a function of W/L ratio (no overestimation caused by fringe effect). The error bars are derived by averaging 4 devices measurements.


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Figure 4. Mobility overestimation as a function of true mobility and device geometry and channel dimension design suggestions. (a) Linear mobility overestimation and (b) saturation mobility overestimation as a function of true mobility and channel ratio. (c) A device with patterned semiconductor layer on Si/SiO2 substrate. (d) A device with unpatterned patterned semiconductor layer on patterned gate/gate insulator substrate. (e) A device with all functional layers aligned. (f) A device with unpatterned semiconductor layer on Si/SiO2 substrate with W/L ≥ 40. (g) A device with narrower side-width electrodes based on (f). (h) A device with discontinuous morphology (stripes) semiconductor layer on Si/SiO2 substrate.



Page 36 of 40

Table 1. Summary of some reported OFETs with W/L ≤ 10 which may have potential of suffering from fringe effect.

Solution-

Organic

Deposition

Film

Semiconductor

method

morphology/Patterning

PDIF-CN2

Edge-casting

Continuous domains/

processing

W/L

µclaim

Ref.

cm2/Vs 2.5

1.3

18

0.2~0.8

0.6

19

10.0

2.18

20

10.0

10.4

21

5.0

45

22

10.0

1.41

23

Not provided PDIF-CN2

Edge-casting

Continuous domains/ Not provided

TIPS-pen

Fluidic

Continuous domains/

channel

Not provided

method C8-BTBT

PCDTPT

C6-DPA

Molecular

Continuous domains/

crystal seed

Not provided

Sandwich

Continuous film/

casting

Not provided

Space-

Continuous

confined self-

domains/No

assembly DPP-polymer

Spin-coating

Continuous film/No

6.7

0.29

24

Ph-BTBT-10

Spin-coating

Continuous film/

5 or 1

14.7

25

8.0

2.2

26

Microplate/No

3.6

31.9

27

Vacuum

Continuous film/

5.0

10.5

28

deposition

Not provided

Vacuum

Continuous film/

0.7

0.14

29

Not provided pDPPT2TT-

Spin-coating

Continuous film/

OD Vapor-

DPh-DBTTT

processing

Not provided Physical vapor transport

BTBT-T6

PBnDT-FTAZ


Page 37 of 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


DH4T

deposition

Not provided

Vacuum

Continuous film/

deposition

Not provided


1.5

0.23

30


Page 38 of 40

Table 2. Summary of some reported OFETs with W/L < 10 which have low risk of suffering from fringe effect.

Solution-

Organic

Deposition

Film

Semiconductor

method

morphology/Patterning

C8-BTBT

Solvent vapor

Microwire/

annealing

Not provided

Dip coating

Microribbon/

processing TIPS-TAP

W/L

µclaim

Ref.

cm2/Vs 0.2

3.0

31

5.5

11.1

32

1

12.1

33

3.3

2.0

34

1.3

1.1

35

Not provided C10-DNBDT-

Edge-casting

Continuous domains/

NW

Vapor-

C8-BTBT

processing Oligothiophene

Laser etching

Vacuum

Continuous

deposition

film/shadow mask

Vacuum

Continuous

deposition

film/scratching


Page 39 of 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Table 3. The fitting values of C-factors for the organic transistors. Organic semiconductor

Linear

Saturation

≤4

1.16 (max)

1.12 (max)

≥20

0.15 (min)

0.11 (min)

≤8

0.95 (max)

0.88 (max)

≥20

0.05 (min)

0.03 (min)

≤4

0.74 (max)

0.62 (max)

≥8

0.05 (min)

0.02 (min)

C-

R fac egime tor

W/L C10-DNTT PDIF-CN2 TIPS-pentacene a)

a)

Crystal with continuous film morphology



Table of Contents


Page 40 of 40

Overestimation of Carrier Mobility in Organic Thin Film Transistors Due

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