Patching of Lattice Defects in Two-Dimensional Diffusion Barriers

Subscriber access provided by NAGOYA UNIV

Letter

Patching of Lattice Defects in Two-Dimensional Diffusion Barriers Damon B Farmer, Priscilla Antunez, Marinus Hopstaken, Oki Gunawan, and Shu-Jen Han ACS Appl. Nano Mater., Just Accepted Manuscript • DOI: 10.1021/acsanm.8b00619 • Publication Date (Web): 20 Jun 2018 Downloaded from http://pubs.acs.org on June 20, 2018

Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.

is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.

Page 1 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Applied Nano Materials

Patching of Lattice Defects in Two-Dimensional Diffusion Barriers Damon B. Farmer*, Priscilla D. Antunez†, Marinus Hopstaken, Oki Gunawan, and Shu-Jen Han‡

IBM T.J. Watson Research Center, Yorktown Heights, NY, 10598, USA KEYWORDS: graphene, boron nitride, diffusion barrier, atomic layer deposition, kesterites, CZTSSe, RRAM, resistive switching

Two-dimensional crystals offer promise as diffusion barriers that can also facilitate electronic conduction through the barrier plane via tunneling. We present barriers in which crystal imperfections are patched, leaving the pristine regions of the crystal exposed and able to both prevent diffusion and allow electronic conduction. This is accomplished by atomic layer deposition, where nucleation of patch material is inhibited on the pristine crystal and promoted elsewhere. Demonstrations of the effectiveness of this technique are carried out in the contexts of sulfur diffusion control in photovoltaic kesterite devices, and oxygen diffusion control in oxide-based resistive switching devices.

ACS Paragon Plus Environment

1

ACS Applied Nano Materials 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 2 of 27

Diffusion barriers are a ubiquitous feature of microelectronic technology and absolutely crucial for realizing proper operation of the most fundamental electronic components.1,2,3 An area of recent investigation within this space is the application of two-dimensional (2D) crystals as diffusion barriers. Graphene, hexagonal boron nitride (BN), and molybdenum disulfide (MoS2) have all been actively studied for their ability to prevent diffusion and intermixing.4,5 These materials represent the lower limit for diffusion barrier scaling, and their utilization could fulfill requirements of the International Technology Roadmap for Semiconductors (http://www.itrs2.net), which anticipates the need for ultrathin diffusion barriers close to 1 nm. Due to the monolayer thickness of these crystals, these diffusion barriers have the added benefit of supporting electronic conduction through them via the tunneling process in addition to inherent conduction due to their particular band structures.6,7 The ability to have conduction through these crystal barriers allows for the controlled fabrication of electronic systems using materials that are otherwise miscible. The major issue associated with the application of 2D crystals as diffusion barriers is the presence of lattice imperfections that greatly hinder the barrier characteristics of the crystals.8,9 Vacancies, grain boundaries, and voids are all types of imperfections that are associated with breakdown of these barriers, and can originate during crystal growth or subsequent processing. Voids are typically formed during the physical transfer of the crystal, and their occurrence can hence be minimized by refining the handling process.10 Vacancies and grain boundaries, on the other hand, are inherently formed during crystal growth, and as such, are more difficult to totally eliminate.11,12 Layering stacks of 2D crystals has been used as an attempt to remedy this issue, which has resulted in enhanced robustness of the barrier.13 However, this strategy can only be


2

Page 3 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


implemented for conductive crystals like graphene in order to maintain conduction through the barrier as its thickness increases. What is needed is a method to patch imperfections in 2D crystals while leaving the pristine regions bare, retaining both the diffusion and electronic conduction characteristics of the barrier. Such a method is presented herein, where material deposited by atomic layer deposition (ALD) is used to patch imperfections in monolayer graphene and BN. The close-bonded configuration and corresponding relative chemical inertness of 2D crystals is widely known to inhibit ALD nucleation.14,15,16 Under pure ALD conditions, no nucleation occurs on the basal plane of clean, defect free 2D crystals. However, as outlined in previous studies, structural lattice imperfections like vacancies and grain boundaries do promote nucleation due to the presence of dangling bonds or surface groups at the defect sites.14,17,18 Most other material surfaces also promote nucletion, albeit with varying degrees of initial inhibition.19 It is therefore possible to use this deposition technique to uniformly and conformally coat imperfections in both 2D crystals and exposed surfaces of the supporting substrate beneath the crystal, leaving the crystal basal plane bare. If both the crystal and deposited material are resistant to diffusion in a given material system, then robust 2D diffusion barriers through which electronic conduction is supported can be realized. As one demonstration, these diffusion barriers are incorporated into the kesterite material, copper zinc tin sulfur selenide (Cu2ZnSn(Se,S)4), otherwise known as CZTSSe. CZTSSe films are deposited by solution-phase spin-on techniques,20 which allows the concentration of sulfur to be varied with multiple applications of the film. The nucleation inhibition provided by the 2D crystal is evident in Figure 1, where the crystals are transferred to the CZTSSe surface followed by 10 nm of aluminum oxide (Al2O3) ALD (Supporting Information). While ALD coating on


3


Page 4 of 27

the exposed CZTSSe surface is uniform, it is localized to point defects, grain boundaries, and voids on the crystals. CZTSSe is annealed to 600°C as part of the standard process to crystallize the material, which results in a root-mean-square (RMS) surface roughness of around 70 nm. Even with this large roughness, the conformal coating nature of ALD allows for complete Al2O3 coverage of exposed CZTSSe in crystal voids. Prior to ALD, the crystals are annealed to 400°C in situ in order to clean their surfaces of volatile absorbates and other residues. This greatly enhances the nucleation selectively of the subsequent ALD process. An additional layer of CZTSSe is applied to the top of the barrier to make a CZTSSe/2Dbarrier/CZTSSe sandwich structure. The concentration of sulfur in the two CZTSSe layers is engineered to be different, with the bottom layer composed of 7 % (molar percent) sulfur and the top layer having 15% (molar percent) sulfur (Fig. 2a). These concentrations result in band gaps of 1 eV for the 7% layer and 1.1 eV for the 15% layer, as extrapolated from external quantum efficiency (EQE) measurements (Supporting Information, Figure S1). In order to crystallize the top layer of CZTSSe, this structure is annealed to 600°C. Sulfur readily diffuses in the CZTSe matrix at a rate of 3 x 10-12 cm2/s at 300°C, a diffusivity that is greater than copper in silicon dioxide at the same temperature.21,22 The engineered sulfur concentration gradient combined with the 600°C process used to crystallize the top CZTSSe layer provides an appreciable driving force towards concentration equilibration of the mobile sulfur atoms. This equilibration is prevented by the presence of the diffusion barrier. Secondary ion mass spectrometry (SIMS) measurements of the sulfur depth profile in these samples shows that the concentration gradient is preserved as compared to samples without barriers (Fig. 2b and 2c). For both graphene-ALD and BN-ALD barriers, a sharp step in sulfur concentration exists at the barrier position, the location of which is determined by the onset of aluminum and oxygen signals from the Al2O3


4

Page 5 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


patch. Penetration of these signals into the bottom 7% sulfur layer reflects the conformal nature of the ALD coating penetrating into cracks within the CZTSSe surface. This underlies the importance of using ALD material as the patch considering that the 15% sulfur layer deposited onto the rough 7% sulfur layer similarly has the ability to penetrate into the cracks. These SIMS results illustrate the robustness of the diffusion barriers in material systems that are exposed to high temperatures, and undergo phase transitions and structural transformations during processing. Specifically, barrier integrity does not seem to suffer from the different thermal expansion coefficients of the ALD material and the 2D crystals over the investigated temperature range. Electronic conduction through the diffusion barrier depends on the electronic properties of both the 2D crystal and the patch material. Using insulating Al2O3 as the patch material causes a reduction in current when a graphene-ALD barrier is inserted between two gold electrodes (Fig. 3a and 3c). Low-field transport across the barrier is Ohmic, resulting in a linear current-voltage response and corresponding constant resistance. The high conductivity of graphene contributes a negligible amount of resistance to the stack, so this linearity allows for a direct extrapolation of the resistance contributed by the Al2O3 patches, which cause a 12% increase in resistance in this case, from 109 Ω to 122 Ω. This resistance increase corresponds to the density and size of Al2O3 patches, and is a direct reflection of the quality of 2D crystal employed as the barrier. It can therefore be mitigated by using crystal sheets with minimal structural imperfections. A 118% resistance increase is observed when BN is used instead of graphene, reflecting its insulating rather than semimetallic properties. However, transport through this barrier is also Ohmic, as expected in the low-field tunneling limit.23


5


Page 6 of 27

A resistance decrease occurs when the graphene-ALD barrier is inserted between two layers of CZTSSe with identical sulfur concentrations of 7% (Fig. 3b and 3d). This is a result of space-charge-limited conduction through the semiconducting CZTSSe stack, facilitated by a higher density of available states supplied by the graphene, which is set by its doping level.19 The current-voltage profile of this system is nonlinear due to Schottky emission being the dominant mechanism of charge injection into the CZTSSe. When the sulfur concentration of the top layer is changed to 15%, a pronounced reduction in current is observed for positive voltages, while current remains relatively unchanged for negative voltages. Increasing sulfur concentration in CZTSSe causes a valence band edge shift to higher binding energy, thus increasing the barrier height for charge injection at positive voltages (Fig. 3d insets).24 This unsymmetrical current reduction concurs with the SIMS results that the barrier layer is successfully preventing sulfur migration, preserving the engineered concentration gradient. CZTSSe is well-known as a light absorbing material that can be used in photovoltaics. One advantageous aspect of this material is the band gap tunability achieved by varying sulfur concentration, and the resulting possibility of creating graded band gap absorbers. However, the miscibility of sulfur negates the possibility of producing layered CZTSSe stacks with welldefined composition. This can be remedied by the incorporation of a patched 2D diffusion barrier. Figure 3e shows the unilluminated current-voltage characteristics of p-n junction photodiodes, fabricated using graded CZTSSe stacks of 15% and 7% sulfur concentration as the p-type layers and cadmium sulfide (CdS) as the n-type layer (Fig. 3b).25 As expected from the results shown in Figures 3c and 3d, incorporation of a graphene-ALD (BN-ALD) barrier results in more conductive (resistive) rectifying behavior at high fields compared to devices without diffusion barriers, while negligible conduction is attained when a continuous Al2O3 film is used.


6

Page 7 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


The devices with patched 2D barriers have similar extrapolated threshold voltages around 530 mV, while this value is 560 mV for devices without a barrier. This 30 mV difference indicates that the diffusion barriers are successfully functioning. Without a barrier, the sulfur concentration in both CZTSSe layers will equilibrate to 11%, corresponding to a band gap of 1.05 eV as outlined in Ref. 24. This results in a valence band edge shift at the CdS junction, increasing the barrier height by 50 meV and causing a threshold voltage increase. Discrepancy between the predicted 50 meV and measured threshold voltage difference of 30 mV is most likely due to incomplete redistribution of sulfur, leaving its concentration greater than 11% and corresponding band gap greater than 1.05 eV at the CdS interface. Photocurrent generated by these devices is shown in Figure 3f. The qualitative photoresponse profiles of graphene-ALD devices and devices without barriers are similar. Their difference is likely a result of graphene acting as a recombination center for photo-excited charge carriers, causing a reduction in the photocurrent. This is not the case in the BN-ALD devices, where short-circuit (0 V) photocurrent is enhanced. The photo-response profile of these devices is comparatively more stretched out, which is due to an increase in the series resistance from 33 mΩ/cm2 to 80 mΩ/cm2, as expected for insulating BN (Supporting Information, Figure S2). Devices fabricated with diffusion barriers exhibit an overall improvement in operation reliability, an attribute of the material control provided by the barriers. As seen in the error bars in Figure 3f, variation of the photocurrent is a factor of two larger for the devices without barriers. Reliability has been an issue in previous efforts to incorporate 2D crystals as diffusion barriers in photovoltaics, where initial device operation is unstable.26 This is likely the result of diffusion through imperfections in the crystal, which is prohibited here by the ALD patches. Enhancement of the short-circuit current observed when the BN-ALD barrier is used reflects the increased light


7


Page 8 of 27

absorption afforded by the graded CZTSSe stacks, and is a demonstration of the effectiveness of the barrier. The accompanying series resistance could be minimized by utilizing 2D crystals with band gaps between BN and CZTSSe so as to allow for enhanced transport through the barrier but also preventing the proposed carrier recombination observed when graphene is used. While graphene-based diffusion barriers cannot be used in photovoltaic devices, they could have utility as components in resistive switching devices.27 One of the most popular material systems for resistive switching is hafnium dioxide (HfO2), where oxygen diffusion in HfO2 is controlled by bias voltage and electrode reactivity, and the resulting conductive filament of oxygen vacancies is extended and retracted between the electrodes to form high and low resistance states.28 Poor stability and reliability in the form of retention loss and hard breakdown hinders the overall performance and applicability of these devices. However, device operation is dramatically improved with the incorporation of a graphene-ALD diffusion barrier within the HfO2 film (Fig. 4a). This is demonstrated in Figure 4b, which compares resistive switching devices with and without graphene-ALD barriers. Devices composed of the stack Ti/10 nm HfO2/TiN initially show the desired hysteretic behavior, where sweeping to increasingly positive voltages causes conversion from the high resistance state to the low resistance state. Reversibility back to the original high resistance state at negative voltages does not occur, though, and after several sweeps the hysteresis window has completely disappeared. This type of device failure, characterized by electrical shorting, is indicative of oxygen vacancy accumulation at the inert TiN electrode.29 In contrast, devices composed of the stack Ti/5 nm HfO2/graphene-ALD/5 nm HfO2/TiN exhibit reversible hysteretic behavior, with conversion back to the high resistance state upon application of a negative bias. It is noted that the same voltage range is used to both form the initial filament and switch the device.


8

Page 9 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Enhanced stability provided by the diffusion barrier suggests that its presence prevents vacancy accumulation at the TiN electrode. Multi-layer graphene has previously been used in resistive memory devices as the reactive electrode, where it was speculated that oxygen either reacted with or intercalated into the graphene film.30 Here, however, when the reactive Ti electrode is replaced by gold, the hysteretic behavior of the stack is lost (Fig. 4b). Therefore, the graphene appears to only act as an inert diffusion barrier, not as a vacancy reservoir or vacancy generation site. Access to the resistance states is allowed through the application of ±2 V across the device, and complete recovery to the high resistance state can be attained (Fig. 4c). Robust switching between resistance states is also observed, with the hysteresis window still present at positive voltages after 100 sweeping cycles (Fig. 4d). The voltage needed to convert between resistance states is fairly constant at positive voltages and more variable at negative voltages. Nonetheless, the hysteresis window at positive voltages is a consistent feature of device operation. These results demonstrate the ability of the graphene-ALD layer to be an effective diffusion barrier against oxygen migration and subsequent irreversible conductive filament formation in HfO2. Investigation of barrier incorporation in aggressively scaled resistive random-access memory (RRAM) devices is of consequent interest. The ability to patch imperfections in 2D crystals and then exploit the mechanical and electronic properties of the pristine crystal regions as diffusion barriers has been demonstrated here in multiple contexts. As the technology of 2D crystal systems continues to advance it will become increasingly necessary to address the unavoidable presence of crystal lattice imperfections, particularly as these materials are scaled up to technologically significant levels. It is therefore anticipated that this patching technique will find broader utility within future research and development involving low-dimensional materials.


9


Page 10 of 27


10

Page 11 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 1. Images of graphene, BN, and CZTSSe surfaces after 10 nm of Al2O3 ALD (a-e: SEM, f: AFM). (a) The interface between graphene and CZTSSe shows the sparsely-coated graphene region appearing darker than the uniformly coated CZTSSe. Large voids in the graphene can be seen in the upper part of the image (150 µm scale bar). (b) For graphene on CZTSSe, Al2O3 nucleates only on voids, grain boundaries, and localized points. (c) Non-uniform nucleation behavior is also observed for BN on CZTSSe, whereas (d) ALD nucleation directly on CZTSSe is uniform. Red and blue arrows indicate respective examples of point defect and grain boundary nucleation sites on the 2D crystals. (e) Nucleation is much more uniform on graphene without an in situ 400°C anneal prior to ALD (b-e: 800 nm scale bar). (f) The RMS roughness of the CZTSSe surface is 70 nm.


11


Page 12 of 27


12

Page 13 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 2. Engineering the sulfur concentration in CZTSSe using patched 2D diffusion barriers. (a) Fabrication scheme of the samples used for SIMS analysis. Thicknesses of the CZTSSe layers are 1 µm. (b) SIMS depth profiles comparing samples with no diffusion barrier, an ALDonly diffusion barrier of 10 nm Al2O3, and a graphene-ALD barrier. Both the ALD and graphene-ALD barriers succeed in blocking sulfur diffusion between CZTSSe layers, as evidenced by a steep slope in the sulfur concentration at the interface between layers. The corresponding slope of sulfur concentration when no diffusion barrier is used is comparatively small, where it is observed to decrease in the 15% CZTSSe layer and increase in the 7% CZTSSe, a clear indication of diffusion across the layers. This is also observed when 2D crystals are used without ALD patching due to a high concentration of voids in the crystals. (c) Similar diffusion behavior is seen when a BN-ALD barrier is employed. Here, sulfur concentration for the ALD-only barrier case is offset in depth because the sampled region is located near the sample edge, where the CZTSSe layers are moderately thicker. Approximately one week elapsed between fabrication of these samples and the SIMS measurements.


13


Page 14 of 27


14

Page 15 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 3. Electronic characterization of the diffusion barriers and their effect on photovoltaic device operation. (a,b) Fabrication schemes of the devices: I. barriers sandwiched between gold electrodes, II. barriers sandwiched between CZTSSe layers, and III. barriers incorporated in a photodiode. (c) Barriers sandwiched between two gold electrodes reveal their resistive contributions. (d) Conduction through two layers of CZTSSe is enhanced by the presence of a graphene-ALD barrier between the two layers. Different sulfur concentrations used in the two layers causes the current profile to become asymmetric, as charge injection under positive bias is reduced. (e) Rectifying characteristics of unilluminated photovoltaic devices with and without diffusion barriers between the CZTSSe layers. Extrapolated threshold voltages (dashed lines) for devices with graphene-ALD and BN-ALD barriers are similar due to their ability to prevent sulfur diffusion and maintain the graded absorber structure. (f) The generated photocurrent of these devices under 35 mW/cm2 of white light irradiation shows that the short-circuit current is enhanced by the presence of the BN-ALD barrier and degraded by the presence of the grapheneALD barrier. Twenty devices of each type were measured in order to ascertain the reliability of device behavior. Spreading of the current through ZnO/ITO and CZTSSe causes the actual area of injected current to be greater than the area of the contact pads.


15


Page 16 of 27


16

Page 17 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 4. Effect of graphene-ALD barrier incorporation on HfO2-based resistive switching devices (10 nm Al2O3 deposited on graphene). (a) Fabrication scheme of the devices with patched diffusion barriers. (b) Devices with barriers show robust hysteretic behavior, while those without barriers become Ohmic after several voltage sweeps. Devices with gold instead of titanium electrodes do not show evidence of resistive switching. (c) The high and low resistance states can be achieved with application of ±2 V. Once programed, the state is retained, as revealed by sweeping with a small voltage. Ten voltage sweeps are performed and plotted for each resistance state shown: initial, after +2 V, and after -2 V. Inset: The same data for the initial state and the state after -2 V on a linear scale shows that the sets of curves overlap tightly. (d) Current hysteresis still exists at positive voltages after 100 programming sweeps.


17


Page 18 of 27

ASSOCIATED CONTENT Supporting Information Measured external quantum efficiency data, measured and modeled photovoltaic data of CZTSSe graded devices, detailed fabrication procedures of all devices, the ALD procedure, and the 2D crystal processing details are included. AUTHOR INFORMATION Corresponding Author *Email: [email protected] Present Addresses †

Argonne National Laboratory, Argonne, IL, 60439, USA

‡

HFC Semiconductor Corp., Fishkill, NY, 12524, USA

Author Contributions D.B.F, P.D.A, and S.-J.H conceived the ideas and designed the experiments. D.B.F. and P.D.A. fabricated and tested the CZTSSe devices. D.B.F. fabricated and tested the HfO2 devices. P.D.A. measured EQE of the CZTSSe films. M.H. performed the SIMS measurements. O.G. modeled the photovoltaic data. D.B.F. and P.D.A. analyzed and interpreted the data. D.B.F. wrote the manuscript with comments from all authors. Funding Sources This work was supported by the Research Division of IBM. Notes The authors declare no competing financial interests.


18

Page 19 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


ACKNOWLEDGMENTS We are grateful to Andrei Fustochenko at T.J. Watson Research Center Central Scientific Services for electron-beam evaporation assistance and Jim Bucchignano for electron-beam lithography assistance.


19


Page 20 of 27

REFERENCES

1

Shacham-Diamand, Y.; Dedhia, A.; Hoffstetter, D.; Oldham, W.G. Copper Transport in Thermal SiO2. J. Electrochem. Soc. 1993, 140, 2427-2432. 2

Ban, I.; Ozturk, M.C.; Demirlioglu, E.K. Suppression of Oxidation-Enhanced Boron Diffusion in Silicon by Carbon Implantation and Characterization of MOSFET’s with Carbon-Implanted Channels. IEEE Trans. Electron Devices 1997, 44, 1544-1551. 3

Yoon, D.-S.; Baik, H.K.; Lee, S.-M.; Lee, S.-I. Barrier Properties of Ta-RuO2 Diffusion Barrier for Dynamic Random Access Memory Capacitor Bottom Electrodes. J. Vac. Sci. Technol. B 1999, 17, 1470-1476. 4

Morrow, W.K.; Pearton, S.J.; Ren, F. Review of Graphene as a Solid State Diffusion Barrier, Small 2016, 12, 120-134. 5

Lo, C.-L; Catalano, M.; Smithe, K.K.H.; Wang, L.; Zhang, S.; Pop, E.; Kim, M.J.; Chen, Z. Studies of Two-Dimensional h-BN and MoS2 for Potential Diffusion Barrier Application in Copper Interconnect Technology, npj 2D Materials and Applications 2017, 1, 42. 6

Britnell, L.; Gorbachev, R.V.; Jalil, R.; Belle, B.D.; Schedin, F.; Mishchenko, A.; Georgiou, T.; Katnelson, M.I.; Eaves, L.; Morozov, S.V.; Peres, N.M.R.; Leist, J.; Geim, A.K.; Novoselov, K.S.; Ponomarenko, L.A. Field-Effect Tunneling Transistor Based on Vertical Graphene Heterostructures, Science 2012, 335, 947-950. 7

Lee, G.-H.; Yu, Y.-J.; Lee, C.; Dean, C.; Shepard, K.L.; Kim, P.; Hone, J. Electron Tunneling through Atomically Flat and Ultrathin Hexagonal Boron Nitride, Appl. Phys. Lett. 2011, 99, 243114. 8

Banhart, F.; Kotakoski, J.; Krasheninnikov, A.V. Structural Defects in Graphene, ACS Nano 2011, 5, 26-41.

9

Wong, D.; Velasco Jr., J.; Ju, L.; Lee, J.; Kahn, S.; Tsai, H.-Z.; Germany, C.; Taniguchi, T.; Watanabe, K.; Zettl, A.; Wang, F.; Crommie, M.F. Characterization and Manipulation of Individual Defects in Insulating Hexagonal Boron Nitride using Scanning Tunneling Microscopy Nature Nanotechnol. 2015, 10, 949-953. 10

Liang, X.; Sperling, B.A.; Calizo, I.; Cheng, G.; Hacker, C.A.; Zhang, Q.; Obeng, Y.; Yan, K.; Peng, H.; Li, Q.; Zhu, X.; Yuan, H.; Walker, A.R.H.; Liu, Z.; Peng, L.; Richter, C.A. Toward Clean and Crackless Transfer of Graphene, ACS Nano 2011, 5, 9144-9153.

11

Biro, L.P.; Lambin, P. Grain Boundaries in Graphene Grown by Chemical Vapor Deposition, New J. Phys. 2013, 15, 035024.


20

Page 21 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


12

Liu, Y.; Zou, X.; Yakobson, B.I. Dislocations and Grain Boundaries in Two-Dimensional Boron Nitride, ACS Nano 2012, 6, 7053-7058.

13

Li, L.; Chen, X.; Wang, C.-H.; Cao, J.; Lee, S.; Tang, A.; Ahn, C.; Roy, S.S.; Arnold, M.S.; Wong, H.-S.P. Vertical and Lateral Copper Transport through Graphene Layers, ACS Nano 2015, 9, 8361-8367. 14

Wang, X.; Tabakman, S.M.; Dai, H. Atomic Layer Deposition of Metal Oxides on Pristine and Functionalized Graphene, JACS 2008, 130, 8152-8153. 15

Liu, H.; Xu, K.; Zhang, X.; Ye, P.D. The Integration of High-k Dielectric on TwoDimensional Crystals by Atomic Layer Deposition, Appl. Phys. Lett. 2012, 100, 152115. 16

Zhang, H.; Chiappe, D.; Meersschaut, J.; Conard, T.; Franquet, A.; Nuytten, T.; Mannarino, M.; Radu, I.; Vandervorst, W.; Delabie, A. Nucleation and Growth Mechanisms of Al2O3 Atomic Layer Deposition on Synthetic Polycrystalline MoS2, J. Chem. Phys. 2017, 146, 052810. 17

Kim, M.; Kim, K.-J.; Lee, S.-J.; Kim, H.-M.; Cho, S.-Y.; Kim, M.-S.; Kim, S.-H.; Kim, K.-B. Highly Stable and Effective Doping of Graphene by Selective Atomic Layer deposition of Ruthenium, ACS Appl. Mater. Interfaces 2017, 9, 701-109. 18

Kim, K.; Lee, H.-B.-R.; Johnson, R.W.; Tanskanen, J.T.; Liu, N.; Kim, M.-G.; Pand, C.; Ahn, C.; Bent, S.F.; Bao, Z. Selective Metal Deposition at Graphene Line Defects by Atomic Layer Deposition, Nat. Commun. 2014, 5:4781.

19

Farmer, D.B.; Gordon, R.G. High Density Ru Nanocrystal Deposition for Nonvolatile Memory Applications, J. Appl. Phys. 2007, 101, 124503. 20

Barkhouse, D.A.R.; Gunawan, O.; Gokmen, T.; Todorov, T.K.; Mitzi, D.B. Device Characteristics of a 10.1% Hydrazine‐Processed Cu2ZnSn(Se,S)4 Solar Cell, Prog. Photovolt. Res. Appl. 2012, 20, 6–11. 21

Harvey, S.P.; Repins, I.; Teeter, G. Defect Chemistry and Chalcogen Diffusion in Thin-Film Cu2ZnSnSe4 Materials, J. Appl. Phys. 2015, 117, 074902. 22

McBrayer, J.D.; Swanson, R.M.; Sigmon, T.W. Diffusion of Metals in Silicon Dioxide J. Electrochem. Soc. 1986, 133, 1242-1246. 23

Simmons, J.G. Generalized Formula for the Electric Tunnel Effect between Similar Electrodes Separated by a Thin Insulating Film, J. Appl. Phys. 1963, 34, 1793-1803.

24

Haight, R.; Barkhouse, A.; Gunawan, O.; Shin, B.; Copel, M.; Hopstaken, M.; Mitzi, D.B. Band Alignment at the Cu2ZnSn(SxSe1-x)4/CdS Interface, Appl. Phys. Lett. 2011, 98, 253502.


21


Page 22 of 27

25

Antunez, P.D.; Bishop, D.M.; Luo, Y.; Haight, R. Efficient Kesterite solar Cells with High Open-Circuit Voltage for Applications in Powering Distributed Devices, Nat. Energy 2017, 2, 884-890. 26

Ergen, O.; Gilbert, S.M.; Pham, T.; Turner, S.J.; Tan, M.T.Z.; Worsley, M.A.; Zettl, A. Graded Bandgap Perovskite Solar Cells, Nat. Mater. 2017, 16, 522-526. 27

Ielmini, D. Resistive Switching Memories Based on Metal Oxides: Mechanisms, Reliability and Scaling, Semicond. Sci. Technol. 2016, 31, 063002. 28

Traore, B.; Blaise, P.; Vianello, E.; Perniola, L.; De Salvo, B.; Nishi, Y. HfO2-Based RRAM: Electrode Effects, Ti/HfO2 Interface, Charge Injection, and Oxygen (O) Defects Diffusion Through Experiment and Ab Initio Calculations, IEEE Trans. on Electron Devices 2016, 63, 360-368.

29

Lohn, A.J.; Mickel, P.R.; Marinella, M.J. Mechanism of Electrical Shorting Failure Mode in Resistive Switching, J. Appl. Phys. 2014, 116, 034506.

30

Mannequin, C.; Delamoreanu, A.; Latu-Romain, L.; Jousseaume, V.; Grampeix, H.; David, S.; Rabot, C.; Zenasni, A.; Vallee, C.; Gonon, P. Graphene-HfO2-Based Resistive RAM Memories, Microelectron. Eng. 2016, 161, 82-86.


22

Page 23 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


TABLE OF CONTENTS GRAPHIC


23


Figure 1. Images of graphene, BN, and CZTSSe surfaces after 10 nm of Al2O3 ALD (a-e: SEM, f: AFM). (a) The interface between graphene and CZTSSe shows the sparsely-coated graphene region appearing darker than the uniformly coated CZTSSe. Large voids in the graphene can be seen in the upper part of the image (150 µm scale bar). (b) For graphene on CZTSSe, Al2O3 nucleates only on voids, grain boundaries, and localized points. (c) Non-uniform nucleation behavior is also observed for BN on CZTSSe, whereas (d) ALD nucleation directly on CZTSSe is uniform. Red and blue arrows indicate respective examples of point defect and grain boundary nucleation sites on the 2D crystals. (e) Nucleation is much more uniform on graphene without an in situ 400°C anneal prior to ALD (b-e: 800 nm scale bar). (f) The RMS roughness of the CZTSSe surface is 70 nm. 177x83mm (300 x 300 DPI)


Page 24 of 27

Page 25 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 2. Engineering the sulfur concentration in CZTSSe using patched 2D diffusion barriers. (a) Fabrication scheme of the samples used for SIMS analysis. Thicknesses of the CZTSSe layers are 1 µm. (b) SIMS depth profiles comparing samples with no diffusion barrier, an ALD-only diffusion barrier of 10 nm Al2O3, and a graphene-ALD barrier. Both the ALD and graphene-ALD barriers succeed in blocking sulfur diffusion between CZTSSe layers, as evidenced by a steep slope in the sulfur concentration at the interface between layers. The corresponding slope of sulfur concentration when no diffusion barrier is used is comparatively small, where it is observed to decrease in the 15% CZTSSe layer and increase in the 7% CZTSSe, a clear indication of diffusion across the layers. This is also observed when 2D crystals are used without ALD patching due to a high concentration of voids in the crystals. (c) Similar diffusion behavior is seen when a BN-ALD barrier is employed. Here, sulfur concentration for the ALD-only barrier case is offset in depth because the sampled region is located near the sample edge, where the CZTSSe layers are moderately thicker. Approximately one week elapsed between fabrication of these samples and the SIMS measurements.



82x203mm (300 x 300 DPI)


Page 26 of 27

Page 27 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 3. Electronic characterization of the diffusion barriers and their effect on photovoltaic device operation. (a,b) Fabrication schemes of the devices: I. barriers sandwiched between gold electrodes, II. barriers sandwiched between CZTSSe layers, and III. barriers incorporated in a photodiode. (c) Barriers sandwiched between two gold electrodes reveal their resistive contributions. (d) Conduction through two layers of CZTSSe is enhanced by the presence of a graphene-ALD barrier between the two layers. Different sulfur concentrations used in the two layers causes the current profile to become asymmetric, as charge injection under positive bias is reduced. (e) Rectifying characteristics of unilluminated photovoltaic devices with and without diffusion barriers between the CZTSSe layers. Extrapolated threshold voltages (dashed lines) for devices with graphene-ALD and BN-ALD barriers are similar due to their ability to prevent sulfur diffusion and maintain the graded absorber structure. (f) The generated photocurrent of these devices under 35 mW/cm2 of white light irradiation shows that the short-circuit current is enhanced by the presence of the BN-ALD barrier and degraded by the presence of the graphene-ALD barrier. Twenty devices of each type were measured in order to ascertain the reliability of device behavior. Spreading of the current



through ZnO/ITO and CZTSSe causes the actual area of injected current to be greater than the area of the contact pads. 177x228mm (300 x 300 DPI)


Page 28 of 27

Page 29 of 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Figure 4. Effect of graphene-ALD barrier incorporation on HfO2-based resistive switching devices (10 nm Al2O3 deposited on graphene). (a) Fabrication scheme of the devices with patched diffusion barriers. (b) Devices with barriers show robust hysteretic behavior, while those without barriers become Ohmic after several voltage sweeps. Devices with gold instead of titanium electrodes do not show evidence of resistive switching. (c) The high and low resistance states can be achieved with application of ±2 V. Once programed, the state is retained, as revealed by sweeping with a small voltage. Ten voltage sweeps are performed and plotted for each resistance state shown: initial, after +2 V, and after -2 V. Inset: The same data for the initial state and the state after -2 V on a linear scale shows that the sets of curves overlap tightly. (d) Current hysteresis still exists at positive voltages after 100 programming sweeps. 177x147mm (300 x 300 DPI)


Patching of Lattice Defects in Two-Dimensional Diffusion Barriers

Recommend Documents