Performance Investigation of Multilayer MoS2 Thin-Film Transistors

Feb 27, 2017 - Additionally, to overcome the limitations of the conventional fabrication method, we employed a novel approach known as optically induc...
4 downloads 10 Views 8MB Size
Download PDF
Research Article www.acsami.org

Performance Investigation of Multilayer MoS2 Thin-Film Transistors Fabricated via Mask-free Optically Induced Electrodeposition Meng Li,†,‡ Na Liu,§ Pan Li,†,‡ Jialin Shi,†,‡ Guangyong Li,†,∥ Ning Xi,†,⊥ Yuechao Wang,† and Lianqing Liu*,† †

State Key Laboratory of Robotics, Shenyang Institute of Automation, Chinese Academy of Sciences, Shenyang 110016, China University of the Chinese Academy of Sciences, Beijing 100049, China § School of Mechatronics Engineering and Automation, Shanghai University, Shanghai 200072, China ∥ University of Pittsburgh, Pittsburgh, Pennsylvania 15260, United States ⊥ Emerging Technologies Institute, Department of Industrial & Manufacturing Systems Engineering, University of Hong Kong, Pokfulam, Hong Kong, China ‡

S Supporting Information *

ABSTRACT: Transition metal dichalcogenides, particularly MoS2, have recently received enormous interest in explorations of the physics and technology of nanodevice applications because of their excellent optical and electronic properties. Although monolayer MoS2 has been extensively investigated for various possible applications, its difficulty of fabrication renders it less appealing than multilayer MoS2. Moreover, multilayer MoS2, with its inherent high electronic/photonic state densities, has higher output driving capabilities and can better satisfy the ever-increasing demand for versatile devices. Here, we present multilayer MoS2 back-gate thin-film transistors (TFTs) that can achieve a relatively low subthreshold swing of 0.75 V/decade and a high mobility of 41 cm2·V−1·s−1, which exceeds the typical mobility value of state-of-the-art amorphous silicon-based TFTs by a factor of 80. Ag and Au electrode-based MoS2 TFTs were fabricated by a convenient and rapid process. Then we performed a detailed analysis of the impacts of metal contacts and MoS2 film thickness on electronic performance. Our findings show that smoother metal contacts exhibit better electronic characteristics and that MoS2 film thickness should be controlled within a reasonable range of 30−40 nm to obtain the best mobility values, thereby providing valuable insights regarding performance enhancement for MoS2 TFTs. Additionally, to overcome the limitations of the conventional fabrication method, we employed a novel approach known as optically induced electrodeposition (OIE), which allows the flexible and precise patterning of metal films and enables rapid and mask-free device fabrication, for TFT fabrication. KEYWORDS: multilayer MoS2, thin-film transistors, metal-contact surface, thickness of MoS2 film, mask-free fabrication

1. INTRODUCTION The richness of the electrical, optical, and mechanical properties of two-dimensional (2D) materials has stimulated tremendous scientific enthusiasm and industrial development. Among these 2D materials, graphene, by virtue of its remarkable characteristics, has emerged as a subject of intense research since its first successful exfoliation using Scotch tape in 2004.1,2 Although graphene has generated a substantial amount of interest in research on 2D materials, its gapless nature remains a major obstacle, hindering its application in logical circuits.3 As a result, an increasing amount of attention has been diverted to other potential 2D materials, such as atomically layered transition metal dichalcogenides (TMDCs), with physical and chemical properties that are complementary to those of graphene. In particular, molybdenum disulfide (MoS2), one of the most stable TMDCs, is a layered semiconductor © 2017 American Chemical Society

with weak interplanar van der Waals interactions that undergoes a direct-to-indirect and wide-to-narrow band-gap transition as its structure changes from a single layer to a bulk crystal. More recently, many studies on MoS2 have fully illustrated its enormous potential for use in the fabrication of electronic components, field-effect transistors (FETs), gas or pressure sensors,4,5 optical detectors,6 and capacitors.7 Depending on the number of layers of the applied MoS2 films, the MoS2 devices mentioned above generally fall into two categories: single-layer (SL) and multilayer (ML) MoS2 devices. Special emphasis has been placed on monolayer MoS2 devices because of a unique property of SL MoS2: its Received: December 1, 2016 Accepted: February 20, 2017 Published: February 27, 2017 8361

DOI: 10.1021/acsami.6b15419 ACS Appl. Mater. Interfaces 2017, 9, 8361−8370

Research Article

ACS Applied Materials & Interfaces

locations. Thus, conventional mask fabrication is avoided. Moreover, the customized metal electrodes are rapidly produced in a subsequent electrochemical reaction within a few seconds, and the entire production process is performed under ambient experimental conditions. Previous reports have demonstrated that the metal-to-MoS2 interface and the MoS2 film thickness play significant roles in determining device performance.23 Regarding electrode materials, Au is the most commonly chosen material and is widely adopted for metal electrodes because of its chemical stability and the good contact it can achieve with two-dimensional materials.24,25 However, according to a recent report,26 Ag, which exhibits a smooth surface and excellent wettability on MoS2, has also been proven to form good metal contacts and may help to boost the electronic performance of MoS2 devices. Although considerable work has been done to study both types of metal contacts, produced by fabrication techniques based on thermal evaporation or electron beam evaporation,27,28 research on Au or Ag electrodes produced via OIE is still lacking. In addition, although the dependence of the extracted mobility on MoS2 film thickness on an SiO2 or poly(methyl methacrylate) (PMMA) substrate has been investigated,29 to the best of our knowledge, no observations of this phenomenon have been reported for MoS2 on an amorphous hydrogenated silicon (aSi:H)/indium tin oxide (ITO) substrate. In this study, Au and Ag electrode-based multilayer MoS2 TFTs were fabricated with the aid of the OIE technique. Multilayer MoS2 films of various thicknesses were obtained via mechanical exfoliation, carefully deposited on an a-Si:H-based substrate, and selected after morphological measurements via atomic force microscopy (AFM). Subsequently, the growth of electrodes with customized shapes on the target MoS2 films was completed within a few seconds via OIE. Then, TFTs with metal contacts of different roughnesses were fabricated for comparison. For the first time, we observed the variation of mobility with MoS2 film thickness on an a-Si:H/ITO substrate. The produced MoS2-based TFTs were able to achieve an on− off current ratio of 104, a subthreshold swing of 0.75 V/decade, and a mobility of 41 cm2·V−1·s−1, which far exceed the electrical performance characteristics of traditional a-Si devices (with mobility values of 0.5−1 cm2·V−1·s−1).30

direct band gap of 1.8 eV. For example, monolayer MoS2 is a promising material for optoelectronic applications that require high photoresponsivity8 and strong photoluminescence.9 In addition, sensors based on monolayer MoS2 show more rapid and sensitive responses than those based on multilayer MoS2 sheets.10 Despite these merits, ML MoS2 electronic devices are more attractive than their SL counterparts in many respects. Preparation of SL MoS2, either via the mechanical peeling-off method or the chemical vapor deposition (CVD) growth technique, is much more complicated than that of ML MoS2, thus increasing the cost of SL MoS2. Furthermore, from the physical property perspective, ML MoS2 is expected to produce a higher driving current than SL MoS2 because it has 3 times the number of density states11 and because of the interlayer screening effect.12 Another advantage of ML MoS2 is that its indirect band gap varies only slightly with the number of layers, resulting in reasonably stable electrical properties. FETs are among the most fundamental and essential components for the fabrication of electronic devices, serving as the building blocks for modern integrated circuits. The performance of FETs strongly influences or even predominantly determines the behavior of the entire circuit. Thin-film transistors (TFTs) are a special type of FET. Although the development of TFTs matured later than that of silicon-based technology, TFTs have drastically grown into a burgeoning industry with the spread of various display applications, such as liquid-crystal displays (LCDs) and light-emitting diodes (LEDs), which are the most prevalent uses of TFTs. To achieve desirable performance in terms of high on−off current ratio, high carrier mobility, and good mechanical flexibility, 2D materials are the natural choice for TFTs because of their inherent electrostatic integrity and enormous potential for tunability in their properties.13 Many MoS2-based TFTs have been reported in various publications, which have demonstrated TFTs with excellent mechanical flexibility that can withstand a 0.75 mm bending radius,14 enhancement of optical transparency by laser annealing,15 and highly increased mobility achieved by addition of sol−gel ZrO2 as a high-k dielectric layer.16 Although tremendous advances have been achieved in TFTs fabricated from MoS2, there is still room for further improvement to satisfy the stringent requirements for future robust circuits, especially with regard to fabrication techniques and performance enhancement. To date, the most common approach to nanodevice processing is a combination of mechanical exfoliation of MoS 2 with resist-based electron-beam lithography (EBL).17−19 Other routes for the fabrication of more functional devices with well-defined MoS2 films or electrodes via nanoimprint lithography, laser patterning, or photolithography have also been reported.20−22 Although these techniques work well with diverse materials and/or can be used to achieve highresolution patterning, the low efficiency of the manufacturing process, the use of expensive equipment, and the timeconsuming nature of lithography processing for mask production severely impede their widespread application. As an alternative, the optically induced electrodeposition (OIE) technique, which was developed from the conventional dielectrophoresis (DEP) method, can afford precise control over the relative positioning of MoS2 and electrodes, thereby ensuring their effective connection. Furthermore, metal electrodes with arbitrary shapes can be directly produced by use of a computer, which conveniently allows researchers to freely design electrodes with custom shapes, dimensions, and

2. EXPERIMENTAL SECTION 2.1. Experimental System for Application of the OIE Technique. The OIE chip consisted of two parallel-plate electrodes. The upper planar electrode consisted of transparent glass coated with a conductive 120 nm thick layer of indium tin oxide (ITO). The lower planar electrode, serving as the substrate, consisted of predeposited 120 nm thick ITO and 1 μm thick a-Si:H, which were fabricated through plasma-enhanced chemical vapor deposition processing. The two parallel electrodes were vertically separated by a microfluidic chamber, approximately 50 μm in height, filled with a solution of metal ions, either silver nitrate (AgNO3) or hypochlorite gold (AuHCl4). A signal generator (Agilent 33522A) that generated an alternating voltage was applied between the two parallel electrodes. The pattern shapes of the electrodes were first designed by use of commercial personal computer software (Flash 11, Adobe) and were then transferred and projected onto specified locations with the aid of a digital LCD projector (Sony VPL-F400X) through a condenser objective (Nikon 50×/0.55). To achieve better visualization and realtime control of the device assembly, an imaging module consisting of a personal computer with an image acquisition card, a charge-coupled device (CCD; DaHeng Image DH-SV1411FC), and a microscope (OPTEM Zoom 160) was utilized to monitor the fabrication process. During fabrication, the OIE chip was fixed on a three-dimensional 8362

DOI: 10.1021/acsami.6b15419 ACS Appl. Mater. Interfaces 2017, 9, 8361−8370

Research Article

ACS Applied Materials & Interfaces

Figure 1. OIE system and experimental procedure. (a) Schematic illustration of OIE platform. (Inset) Structure of OIE chip where electrochemical reactions occur. (b) Fabrication process for MoS2 TFTs via OIE technique. (i) Mechanical exfoliation of ML MoS2 and transference onto a-Si:H/ ITO substrate. (ii) Injection of AgNO3 or AuCl4 solution onto OIE chip. (iii) Growth of metal electrodes on preselected MoS2 film. (iv) Crosssectional view of structure of ML MoS2 TFTs.

Figure 2. Top-view optical microscopic images of fabricated MoS2 TFTs. (a−f) MoS2 TFTs fabricated with different solution concentrations within 20 s deposition time. The green optical patterns are the predesigned shapes of the electrodes. Subsequent electrode growth in the rectangle-enclosed region in panel b is shown in the upper right-hand corner, as indicated by the blue arrow. (i−iii) Magnified views of the circle-enclosed regions in panel f, as indicated by the red arrow. micromovement platform, which allowed the OIE chip to freely move in three-dimensional space. Although the fabrication area was limited to 800 μm in diameter, a larger fabrication area could be reached through moving the platform to change the fabrication position. By use of this system, the fabrication processing precision could theoretically reach the half-wavelength diffraction limit for visible light. 2.2. Preparation and Characterization of Multilayer MoS2 films. The mechanical cleavage method has been shown to be highly reliable in enabling the preparation of MoS2 films from bulk, yielding films with a thickness of a few micrometers or even on the atomic scale. In our experiment, multilayer MoS2 films were mechanically exfoliated (via repeated peeling) from commercially available crystals of molybdenite (SPI Supply) by the Scotch-tape cleavage technique and were subsequently deposited on a-Si:H/ITO substrates. Tappingmode AFM (Dimension ICON with NanoScope V controller, Bruker) was employed to perform measurements of surface topography and thickness. 2.3. Growth of Electrodes. After preparation of MoS2 films and the OIE chip required for the experiment, electrodes were fabricated by the OIE technique. Approximately 100 mL of AgNO3 or AuHCl4 solution was injected onto the OIE chip along the gap between the two parallel electrodes. Then the predesigned electrode images were

projected onto the surface of the photoconductive a-Si:H/ITO substrate by use of the digital equipment. By application of alternating voltage with appropriate amplitude and frequency, Ag or Au electrodes were fabricated. Because of the constraints concerning image resolution and the precision of the experimental equipment, the minimum dimension of the electrodes was approximately 2.7 μm. For preparation of MoS2 TFTs with Ag electrodes, we selected alternating peak-to-peak voltage (Vpp) = 10 V with 50 kHz frequency and 100 mM silver nitrate solution. These experimental conditions yielded Ag electrode-based MoS2 TFTs of the best quality. The minimum roughness of the successfully fabricated Ag electrodes was 22.9 nm. For preparation of MoS2 TFTs with Au electrodes, the parameters were alternating Vpp of 20 V with 20 kHz frequency and 20 mM AuHCl4 solution. The deposition times for the Ag and Au electrodes were approximately 20 and 90 s, respectively. The minimum roughness of the obtained Au electrodes was 66.4 nm.

3. RESULTS AND DISCUSSION 3.1. Fabrication of MoS2 Thin-Film Transistors. All MoS2 TFTs were fabricated by use of the OIE system shown in Figure 1a. The OIE chip, the most essential part of the entire 8363

DOI: 10.1021/acsami.6b15419 ACS Appl. Mater. Interfaces 2017, 9, 8361−8370

Research Article

ACS Applied Materials & Interfaces

Figure 3. SEM and AFM images of MoS2 TFTs with Ag and Au electrodes. (a, d) SEM images of the structures of MoS2 TFTs with Ag and Au electrodes. (b, e) Magnified views of the red square-enclosed regions in panels a and d. (c, f) Corresponding surface profiles for x−x′ and y−y′ positions of MoS2 channels on Ag and Au electrode-based MoS2 TFTs, with thicknesses of 31.7 and 13.3 nm, respectively, as measured via AFM. (g, h) Topographic images of the surfaces of Ag and Au electrodes, obtained via SEM and AFM.

parts of the green optical patterns were slowly filled with the reduced metal elements, as shown in Figure 2a−c, particularly at 10 mM, for which the hollow part remained nearly unchanged after 20 s. Moreover, as indicated by the blue arrow, the edges and shape of the electrodes formed at lower solution concentrations were seen to be more blurred and irregular than those of the electrodes fabricated at higher concentrations. At higher solution concentrations (50−200 mM), as shown in Figure 2d−f, the filling rate was much faster, and the hollow parts of the green optical patterns were rapidly filled with the reduced metal elements. However, an excessively high solution concentration, such as 200 mM, is not desirable. As shown in Figure 2i−iii, small tails or dendritelike structure were observed on the electrodes at 200 mM; these should be avoided because of their detrimental effect on electrode roughness. In addition to preparation rate, surface roughness and thickness are also critical for electrode growth. Generally, electrodes should have sufficient thickness to ensure a normal connection between the electrodes and the semiconductor material. Typically, the thickness of the electrodes was in the range of approximately 1−2 μm. Meanwhile, the roughness of the electrodes determines the interfacial quality and can have a pronounced impact on the electrical performance of the device. A detailed discussion of parameter selection can be found in Supporting Information (see Figures S3−S6). The obtained MoS2 TFTs with Ag and Au electrodes are shown in Figure 3a,d. Scanning electron microscopic (SEM) images reveal that the Ag electrodes formed denser and smoother metal surfaces than did the Au electrodes. As can be

OIE technique, had a sandwich structure, consisting of a microfluidic chamber between two parallel-plate electrodes, as shown in the inset of Figure 1a (photographic images of the OIE chip and the experimental setup can be seen in Figure S1 in Supporting Information). Figure 1b shows a schematic illustration of the fabrication process for MoS2 TFTs. After the ML MoS2 film was deposited on the a-Si:H/ITO substrate, an alternating electric field with a specific frequency was applied throughout the entire chamber, and the electrochemical reactions described by eqs 1 and 2 proceeded on the substrate. The operational principle of OIE and the underlying mechanism of this technique have been introduced in the literature 31 and are described in detail in Supporting Information (see Figure S2). Ag + + e− → Ag

(1)

Au 3 + + 3e− → Au

(2)

Prior to fabrication of MoS2 TFTs via OIE, the experimental parameters should be carefully selected to ensure the success of the experiment. Solution concentration, deposition time, voltage amplitude, and frequency are all essential factors affecting electrode fabrication and will greatly influence the electrode preparation rate, surface roughness, and thickness. For example, we fabricated several MoS2 TFTs using different solution concentrations within a 20 s deposition time and compared the formation of these TFTs, as shown in Figure 2. It can be seen from Figure 2a−f that the preparation rate of the metal electrodes is closely related to the solution concentration. At lower solution concentrations (10−30 mM), the hollow 8364

DOI: 10.1021/acsami.6b15419 ACS Appl. Mater. Interfaces 2017, 9, 8361−8370

Research Article

ACS Applied Materials & Interfaces

Figure 4. Representative electrical characteristics of Ag and Au electrode-based TFTs. (a) Transfer curves of Ag electrode-based MoS2 TFT at Vds = 3.5 and 0.5 V. (Inset) Same curves on a linear scale. (b) Output curves of the same Ag-electrode-based MoS2 TFT for Vds = 0−4 V, with Vgs ranging from −6 to 9 V. (c) Transfer curves of Au electrode-based MoS2 TFT at Vds = 5 and 0.5 V. (Inset) Same curves on a linear scale. (d) Output curves of the same Au electrode-based MoS2 TFT for Vds = 0−5 V, with Vgs ranging from −10 to 10 V. Solid black and blue lines in panels a and c were used to extract the SS values for Ag- and Au-based TFTs, respectively. Dashed black and blue lines in panels a and c indicate slopes of the Ids0.5−Vgs curves.

seen from Figure 3b,c,e−h, thicknesses of the MoS2 films and surface morphologies of the Ag and Au electrodes were also measured via AFM, indicating that the thicknesses of the MoS2 films were 31.7 and 13.3 nm and the surface roughnesses of the Ag and Au electrodes were 32.5 and 71.5 nm, respectively. 3.2. Electrical Characteristics of Ag and Au Electrodebased MoS2 Thin-Film Transistors. In an effort to evaluate the electronic properties of the fabricated MoS2 TFTs with Ag and Au electrodes, current and voltage measurements were conducted at room temperature under ambient conditions by use of a semiconductor parameter analyzer (Agilent 4155C). Here, the lower planar ITO glass electrode, a-Si:H substrate, and patterned silver electrodes functioned as the back gate, dielectric layer, and source and drain electrodes, respectively. Channel width (W) and length (L) for the Ag electrode-based TFTs were 4 and 6.4 μm, respectively, and for the Au electrode-based TFTs they were 8.7 and 15.2 μm, respectively. From the transfer and output characteristics of MoS2 TFTs presented in Figure 4, both types of MoS2 TFTs, based on either Ag or Au electrodes, exhibited n-type characteristics. Generally, MoS2-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are more likely to show n-type behaviors because of the charge neutrality level of MoS2, which is located below the conduction band. From the transfer curves shown in Figure 4a,c, it can be deduced that the on−off current ratios for the Ag and Auelectrode-based TFTs were 104 and 103, respectively. Then

we can extract the subthreshold swing (SS), which is an important parameter in determining the switching speed of a device and should be minimized. SS can be evaluated by use of eq 3: SS = dVg /[d(log Id)]

(3)

SS values for the Ag and Au electrodes are calculated to be 0.92 V/decade at a drain-source voltage of Vds = 3.5 and 1.47 V/ decade at Vds = 5 V. Thus, the SS for Ag electrode-based MoS2 TFTs was better than that for their Au counterparts. Although the SS values for the Ag electrodes were slightly lower than the reported value of >1 V/decade27 obtained for back-gate MoS2 FETs on bare SiO2, the SS values observed for our devices are still much larger than the ideal SS for MoS2 TFTs (∼60 mV/ decade). The large SS of our devices can be attributed to multiple factors, such as the relatively low dielectric constant and high thickness (∼1 μm) of the a-Si:H, the inferior interlayer state between sample and substrate, and the large Schottky barrier at the source-to-channel interface.7 We now consider the mobility characteristics of our devices. Typically, the mobilities at low- and high-field voltages can be extracted from the expressions μ low =

dIds L WCoxVds dVgs

and 8365

DOI: 10.1021/acsami.6b15419 ACS Appl. Mater. Interfaces 2017, 9, 8361−8370

Research Article

ACS Applied Materials & Interfaces

Figure 5. Topographies of Ag electrodes and representative electrical characteristics of the corresponding Ag electrode-based MoS2 TFTs. (a, d, g) Topographic images of Ag electrodes with roughnesses of (a) 30.6 nm, (d) 75.7 nm, and (g) 134 nm. (b, e, h) Transfer curves of Ag electrode-based MoS2 TFTs with different electrode roughnesses at Vds = 5 and 0.5 V (logarithmic scale on the left y-axis and linear scale on the right y-axis). (c, f, i) Output curves of Ag electrode-based MoS2 TFTs for Vds = 0−5 V, with Vgs ranging from −10 to 10 V.

μ high =

2LIds

extract the mobility while eliminating the influence of contact resistance (RC), yielding eq 4:

2

WCox(Vgs − Vth)

, respectively. For an Ag electrode-based MoS2 TFT, μlow and μhigh correspond to Vds values of 0.5 and 3.5 V, respectively. Cox is capacitance of the dielectric film; W and L are channel width and length, respectively; differential conductance can be extracted from the linear region at Vds = 3.5 V; and Vth is estimated to be −4.7 V, as shown by the dotted black line in Figure 4a. For a-Si:H, εr = 11.9 and ε0 = 8.85 × 10−12; thus, Cox = 9.7 × 10−6 F·m−2. The values of μlow and μhigh can thus be determined to be 27.2 and 32.7 cm2·V−1·s−1, respectively. Notably, the TFT output curves shown in Figure 4b primarily exhibit linear behavior. Therefore, it is more accurate to choose μlow to represent the mobility of the device. Notably, the disparity between the two mobility values is commonly ascribed to the existence of a Schottky barrier between electrodes and MoS2. Thus, the contact resistance between electrodes and active layer should be considered because it will dominate the potential difference between source and drain at high gate voltage (Vgs). However, this critical factor is ignored in the original calculation. To address this problem, we employ the method described in a previous publication32 to more properly

μ=

Ids W C (V L ox gs

− Vth − IdsR C)(Vds − 2IdsR C)

(4)

where RC has been found to be ∼7.5 kΩ, as calculated in Supporting Information. The potential drops caused by contact resistance are subtracted from eq 4. The peak mobility obtained by this method is ∼41 cm2·V−1·s−1, which is higher than the mobility of previously reported MoS2 TFTs;14,15 detailed calculations can be found in Supporting Information (Figure S7) . Transfer and output curves for a MoS2 TFT with Au electrodes are depicted in Figure 4c,d. The mobility of the Au electrode-based MoS2 TFT can be calculated in a manner similar to that described above. The extracted μlow and μhigh values are 4.63 and 2.64 cm2·V−1·s−1, respectively. Then, the contact resistance between Au electrodes and MoS2 film is found to be ∼3.19 MΩ, which is much larger than that in the Ag-based device. After contact resistance is subtracted, the peak mobility of the Au electrode-based MoS2 TFT is found to be approximately 8.78 cm2·V−1·s−1. 8366

DOI: 10.1021/acsami.6b15419 ACS Appl. Mater. Interfaces 2017, 9, 8361−8370

Research Article

ACS Applied Materials & Interfaces

Figure 6. (a) Resistor network model for ML MoS2 back-gated transistors. (b, c) Simulated effective mobility as a function of the MoS2 film thickness for various model parameters. (d) Comparison between experimental mobilities extracted for various film thicknesses and simulated results for various contact resistances (RC).

which is provided by an external electrical power source. Thus, a higher voltage is necessary to fabricate Au electrodes. However, an excessively high electric voltage will directly cause damage to the surface of the a-Si:H substrate, thereby leading to failure of the experiment. Even when an appropriate threshold voltage was chosen by chance, most of the obtained Au-MoS2 TFTs did not exhibit transistor characteristics. This phenomenon might be attributed to the longer fabrication time of these devices. To obtain electrodes of the same thickness, Au electrodes usually require 4−5 times the deposition time required for Ag electrodes to complete their growth. This slower electrode growth will lead to a looser electrode structure, which appears to severely affect normal functioning of the resultant device by producing more disconnection points on the electrodes. For this reason, only Ag electrode-based MoS2 TFTs with various surface roughnesses were investigated. Figure 5 presents electronic characteristics of MoS2 TFTs with Ag electrodes with roughnesses of 30.6, 75.7, and 134 nm. As shown in Figure 5b,e,h, the transfer curves were measured at fixed Vds values (0 and 0.5 V) while Vgs was scanned from −10 to 10 V. It is evident that the curves for electrodes with smoother surfaces exhibit sharper subthreshold slopes and narrower subthreshold regions. Furthermore, magnitudes of the on-state current for the various roughnesses vary significantly. According to previous reports,33,34 a larger SS value may originate from the effect of tunneling through the Schottky barrier, and a higher on-state current density, which reflects more effective carrier injection, is also closely related to the

According to the calculated results, the Ag electrode-based TFT in Figure 3a exhibited better electronic performance than did the Au electrode-based TFT in Figure 3d. Generally, the electronic performance of a device is strongly dependent on roughness of the substrate, properties of the semiconductor material and metal contacts, and insulation layer, among other factors. Here, Ag and Au electrode-based MoS2 TFTs were all deposited on a-Si:H substrates produced by the same manufacturer, and device fabrication was conducted under the same experimental temperature and humidity conditions. Thus, these external influence factors can be safely ruled out. Other possible causes of the difference in performance between Ag and Au electrode-based TFTs include metal contacts and thickness of the MoS2 film; these will be discussed separately. 3.3. Impact of Metal Contacts. The lower work function of Ag of 4.26 eV (Au, 5.4 eV) will naturally generate a narrower energy gap between electrodes and semiconductor layer, thereby leading to efficient carrier injection and improved electrical performance. Moreover, the surface roughness analysis presented in Figure 3b,c,e−h reveals that a smoother interface was formed between Ag and MoS2 (RMS 37.8 nm) than that between Au and MoS2 (RMS 71.5 nm). For comparison, Ag and Au electrodes on MoS2 with various surface roughnesses should be produced. Unfortunately, attempts to do so failed because of the difficulty of fabricating Au electrodes on MoS2. The entire OIE process for Au electrodes is extremely difficult to control, and very few Au electrode-based TFTs were obtained. As described in eq 2, the reduction of Au atoms requires a higher activation energy, 8367

DOI: 10.1021/acsami.6b15419 ACS Appl. Mater. Interfaces 2017, 9, 8361−8370

Research Article

ACS Applied Materials & Interfaces

Information), which clearly revealed a nonmonotonic dependence on MoS2 film thickness. To understand the underlying mechanism of this dependence, we employed a resistance network of the type introduced in ref 36 to describe the backgate transistor geometry of our devices, as shown in Figure 6a. Several relevant parameters, such as Schottky barrier resistance (regarded as the contact resistance between metal and MoS2 for convenience), Thomas−Fermi screening charge length (λ), and interlayer resistance of MoS2 (RC), were necessary to simulate the dependence of mobility on film thickness. The mobility range was defined as 0.1−80 cm2·V−1·s−1, considering the relatively low mobility of MoS2 TFTs. According to Thomas− Fermi screening theory,37,38 electric field screening will induce a charge on each layer of the MoS2 film; the strength of this screening is determined by the Thomas−Fermi screening charge length λ, which represents the capability of transferring charge carriers from the bottom layer (the layer adhered to the a-Si:H/ITO substrate, where the MoS2 thickness is zero) to the upper layers.39 A larger value of λ results in more extensive charge transfer and the injection of more carriers into the upper layers. Consequently, the layers closer to the bottom will experience a larger mobility decrease due to carrier loss. As plotted in Figure 6b, the case of λ = 9 nm obviously shows a larger-scale mobility decrease than does the case of λ = 2 nm. When the interlayer resistance Rint is considered, however, the previously mentioned injection of carriers into the upper layers is markedly hindered. As is vividly illustrated in Figure 6c, the mobility of the layers closer to the bottom is not severely affected, but the mobility of the upper layers clearly declines as the value of Rint increases. Similarly, RC, the resistance between metal electrodes and MoS2 film, will also enhance the decrease in mobility. From the simulation results shown in Figure 6c, it is seen that Au electrode-based MoS2 TFTs, with their larger metal contact resistance, will have a much lower mobility than Ag electrode-based MoS2 TFTs. On the basis of the model established above, we adopted values of λ = 9 nm and Rint = 1.6 kΩ to fit the experimental data. As seen from the comparison shown in Figure 6d, the experimental results generally exhibit a nonmonotonic dependence of mobility on MoS2 thickness, which is consistent with the simulation results. However, a large discrepancy between simulated and experimentally measured mobility values is observed. For TFTs, good metal contacts and a high-quality interface between insulator and semiconductor material are the two critical factors for improving electronic performance.40,41 Although metal contact resistance was included in the simulation, interfacial quality was not considered. Hence, it is necessary to further analyze the impact of interfacial quality. For our devices, an a-Si:H film functions as the dielectric layer, with a roughness of 3.5 nm (Figure S8 in Supporting Information). By use of eq 5,42 interfacial quality can be evaluated by calculating the interfacial trap density (Dit):

Schottky barrier. Thus, we analyze the Schottky barrier from the perspectives of SS and on-state current. On the basis of eq 3, SS values were extracted from the Ids− Vgs curves corresponding to Vds = 5 V. SS values for the three different electrode roughnesses, in order of increasing roughness, were 0.906, 2.43, and 4.125 V/decade. According to a previous publication,23 the relationship between the Schottky barrier and Vgs can be described by ΦB + ΦB0 = γ|Vgs − VFB| when the gate voltage Vgs is sufficiently negative (Vgs < VFB). ΦB and ΦB0 are the effective and true Schottky barrier heights, respectively, and VFB is the termination point of the linear relationship between ΦB and Vgs (when Vgs > VFB, the relationship will deviate from linearity, and the value of ΦB will dramatically decrease, no longer showing any relationship to γ). The factor γ can be extracted from the equation SS = γkBT ln 10, where kB is the Boltzmann constant and T is temperature. Thus, for a given Vgs, a larger γ will lead to a greater Schottky barrier because of the positive proportional relationship. More specifically, a rougher metal contact with greater SS will possess a larger value of ΦB. Drain currents were measured while Vds was increased from 0 to 5 V and Vgs was varied from −10 to 10 V in steps of 5 V. As is clearly shown by the transfer and output curves of Figure 5, Ids decreased by 1−2 orders of magnitude as the roughness of the electrodes changed. We adopt the following equation35 ⎛ −qΦB ⎞⎡ ⎛ −qVds ⎞⎤ Ids = A*T 2 exp⎜ ⎟⎢1 − exp⎜ ⎟⎥ ⎝ kBT ⎠⎢⎣ ⎝ kBT ⎠⎥⎦

to describe the relationship between Ids and ΦB, where A* is Richardson’s constant. When qVds ≫ kBT, the relationship can be simplified to ⎛ −qΦB ⎞ Ids = A*T 2 exp⎜ ⎟ ⎝ kBT ⎠

. If the temperature is kept constant, the on-state current Ids varies inversely with ΦB. Thus, a rougher metal contact with a lower on-state current magnitude has a larger value of ΦB. A simple analysis of the relationship between roughness and Schottky barrier implies the existence of a larger Schottky barrier at a rougher metal−MoS2 interface. We speculate that chemical reactivity may more easily occur on a rougher surface, such as the adsorption of oxygen and hydrogen molecules; the exact reasons for and values of the Schottky barrier remain to be further explored in the future. Based on the analysis presented above, the metal−MoS2 contacts play a critical role in the electronic performance of our devices. For this reason, the electrode roughness of subsequently produced Ag electrodebased MoS2 TFTs was controlled to lie within the range 30−35 nm by selecting appropriate deposition times and solution concentrations (as discussed in Supporting Information). 3.4. Impact of MoS2 Film Thickness. To analyze the impact of MoS2 film thickness, several MoS2 TFTs with varying film thicknesses were fabricated. For the reasons discussed above, these MoS2 TFTs were all based on Ag electrodes because of the fabrication difficulty and inferior electronic performance of Au electrodes. The experiments were conducted under identical conditions to minimize the impact of external factors on the metal electrodes. By use of the mobility-extraction method introduced above, the mobilities for MoS2 TFTs with film thicknesses of 10−60 nm were obtained (further details are provided in Table S1 in Supporting

Dit =

⎞ Cox ⎛ qSS ⎜ − 1⎟ ⎝ ⎠ q kT ln 10

(5)

where q is electron charge and T is temperature. For MoS2 TFTs with Ag and Au electrodes, the calculated values of SS are 0.92 and 1.47 V/decade, respectively. Thus, Dit for Ag and Au electrodes is found to be 8.44 × 10¬14 and 13.8 × 10¬14 cm−2· eV−1, respectively; these values are much higher than those for MoS2/Y2O3/HfO2 and MoS2/ZrO2 stacks, by 1−2 orders of magnitude.16,42 Inferior interfacial quality resulting from 8368

DOI: 10.1021/acsami.6b15419 ACS Appl. Mater. Interfaces 2017, 9, 8361−8370

ACS Applied Materials & Interfaces

■

excessively rough surfaces of the a-Si:H films was thus responsible for degraded mobility of the devices and the enormous discrepancy between simulated and experimental results. The best mobility values for Ag electrode-based TFTs were obtained for those with MoS2 film thicknesses of 30−40 nm, as shown in Figure 6d and Table S1 in Supporting Information. The dependence of mobility on film thickness may be attributed to the fact that additional MoS2 layers can act as capping layers and contribute to resisting long-range disorder, thereby enhancing the device mobility, as described in ref 31. An excessive number of MoS2 layers, however, will have an adverse effect on carrier injection and lead to a decrease in mobility, according to the established model. Therefore, selection of an appropriate thickness for the MoS2 film will help to enhance electronic performance. According to the experimental results, MoS2 TFTs with Ag or Au electrodes fabricated by the OIE technique exhibit transistor characteristics, demonstrating the effectiveness of the OIE technique. Many factors contribute to the superior electronic performance of MoS2 TFTs compared with other TFTs. For instance, OIE-based electrode fabrication is naturally an in situ process of reduction, deposition, and crystal growth. It allows the physical connectivity of metal atoms to be preserved to the greatest possible extent. Moreover, the good quality of the metal−semiconductor interface is inferred from our calculations of contact resistance, which takes values of approximately 7−13 kΩ for our devices, lower than those for some transistors obtained via other techniques.43,44 Additionally, nanofilms obtained via mechanical exfoliation are relatively flat and of higher quality compared with their CVD-grown counterparts. All these factors contributed to the higher mobility of our devices compared with other TFTs. Overall, the electronic performance of our TFTs is still much weaker than those of many MoS2 TFTs, which are greatly enhanced by deposition of a high-k insulator, such as HfO2 or Al2O3,45 and by application of an annealing process.46,47 In addition, the minimum dimension of the electrodes was limited to 2.7 μm because of constraints related to image resolution and the precision of the experimental equipment. Further research will be required to improve upon these aspects of the TFT fabrication procedure presented here.

Research Article

ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.6b15419. Additional text and equations, nine figures, and one table describing experimental setup of OIE technique and underlying mechanism, parametric study on OIE fabrication process, calculations about contact resistance and mobility extraction of MoS2 TFT, properties of aSi:H, cycle stability of MoS2 TFT, and statistical information on additionally fabricated MoS2 TFTs (PDF)

■

AUTHOR INFORMATION

Corresponding Author

*E-mail [email protected]. ORCID

Meng Li: 0000-0002-9136-2458 Author Contributions

M.L. and N.L. contributed equally. The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. Notes

The authors declare no competing financial interest.

■

ACKNOWLEDGMENTS This study was partially supported by the NSFC/RGC Joint Research Scheme (Project 51461165501, Project CityU132/ 14), National Natural Science Foundation of China (Project 61522312), and the CAS FEA International Partnership Program for Creative Research Teams.

■

REFERENCES

(1) Novoselov, K. S.; Geim, A. K.; Morozov, S. V.; Jiang, D.; Katsnelson, M. I.; Grigorieva, I. V.; Dubonos, S. V.; Firsov, A. A. Twodimensional Gas of Massless Dirac Fermions in Graphene. Nature 2005, 438, 197−200. (2) Geim, A. K.; Novoselov, K. S. The Rise of Graphene. Nat. Mater. 2007, 6, 183−191. (3) Schwierz, F. Graphene Transistors. Nat. Nanotechnol. 2010, 5, 487−496. (4) Tong, Y.; Lin, Z.; Thong, J. T. L.; Chan, D. S. H.; Zhu, C. MoS2 Oxygen Sensor with Gate Voltage Stress Induced Performance Enhancement. Appl. Phys. Lett. 2015, 107, No. 123105. (5) Yu, F.; Liu, Q.; Gan, X.; Hu, M.; Zhang, T.; Li, C.; Kang, F.; Terrones, M.; Lv, R. Ultrasensitive Pressure Detection of Few-Layer MoS2. Adv. Mater. 2017, 29, No. 1603266. (6) Tsai, D.-S.; Liu, K.-K.; Lien, D.-H.; Tsai, M.-L.; Kang, C.-F.; Lin, C.-A.; Li, L.-J.; He, J.-H. Few-Layer MoS2 with High Broadband Photogain and Fast Optical Switching for Use in Harsh Environments. ACS Nano 2013, 7, 3905−3911. (7) Cao, L.; Yang, S.; Gao, W.; Liu, Z.; Gong, Y.; Ma, L.; Shi, G.; Lei, S.; Zhang, Y.; Zhang, S.; Vajtai, R.; Ajayan, P. M. Direct LaserPatterned Micro-supercapacitors from Paintable MoS2 films. Small 2013, 9, 2905−2910. (8) Lopez-Sanchez, O.; Lembke, D.; Kayci, M.; Radenovic, A.; Kis, A. Ultrasensitive Photodetectors Based on Monolayer MoS2. Nat. Nanotechnol. 2013, 8, 497−501. (9) Yin, Z.; Li, H.; Li, H.; Jiang, L.; Shi, Y.; Sun, Y.; Lu, G.; Zhang, Q.; Chen, X.; Zhang, H. Single-layer MoS2 phototransistors. ACS Nano 2012, 6, 74−80. (10) Li, H.; Yin, Z.; He, Q.; Li, H.; Huang, X.; Lu, G.; Fam, D. W. H.; Tok, A. I. Y.; Zhang, Q.; Zhang, H. Fabrication of Sngle- and

4. CONCLUSION In summary, ML MoS2 TFTs with Au and Ag electrodes can be fabricated by OIE. The superior electronic characteristics of Agbased devices compared with those of Au-based devices illustrate the advantages of Ag−MoS2 contacts. Our findings show that the roughness of metal electrodes produced via OIE significantly influences electronic performance of the resulting MoS2 TFTs. By fabricating Ag−MoS2 TFTs with various flake thicknesses, we observed a nonmonotonic trend in mobility that was closely related to the thickness of MoS2 films. TFTs with MoS2 film thicknesses of 30−40 nm exhibited the best performance, which was far superior to that of conventional amorphous silicon-based TFTs. Unlike the conventional technique, no lithography procedures are required in any step of the fabrication process. Moreover, the presented technique serves as a step toward realizing larger-scale, more complex integrated circuits by using a convenient, flexible, and low-cost technology that can be widely generalized for device fabrication using other emerging two-dimensional materials. 8369

DOI: 10.1021/acsami.6b15419 ACS Appl. Mater. Interfaces 2017, 9, 8361−8370

Research Article

ACS Applied Materials & Interfaces

(28) Liu, W.; Kang, J.; Sarkar, D.; Khatami, Y.; Jena, D.; Banerjee, K. Role of Metal Contacts in Designing High-Performance Monolayer NType WSe2 Field Effect Transistors. Nano Lett. 2013, 13, 1983−1990. (29) Bao, W.; Cai, X.; Kim, D.; Sridhara, K.; Fuhrer, M. S. High Mobility Ambipolar MoS2 Field-Effect Transistors: Substrate and Dielectric Effects. Appl. Phys. Lett. 2013, 102, No. 042104. (30) Street, R. A. Thin-Film Transistors. Adv. Mater. 2009, 21, 2007− 2022. (31) Liu, N.; Wang, F.; Liu, L.; Yu, H.; Xie, S.; Wang, J.; Wang, Y.; Lee, G.-B.; Li, W. J. Rapidly Patterning Micro/Nano Devices by Directly Assembling Ions and Nanomaterials. Sci. Rep. 2016, 6, No. 32106. (32) Roy, T.; Tosun, M.; Kang, J. S.; Sachid, A. B.; Desai, S. B.; Hettick, M.; Hu, C. C.; Javey, A. Field-Effect Transistors Built from All Two-Dimensional Material Components. ACS Nano 2014, 8, 6259− 6264. (33) Kwon, H.-J.; Jang, J.; Kim, S.; Subramanian, V.; Grigoropoulos, C. P. Electrical Characteristics of Multilayer MoS2 Transistors at Real Operating Temperatures with Different Ambient Conditions. Appl. Phys. Lett. 2014, 105, No. 152105. (34) Feng, B.; Huang, S.; Wang, J.; Pan, D.; Zhao, J.; Xu, H. Q. Schottky Barrier Heights at the Interfaces between Pure-Phase InAs Nanowires and Metal Contacts. J. Appl. Phys. 2016, 119, No. 054304. (35) Razavieh, A.; Mohseni, P. K.; Jung, K.; Mehrotra, S.; Das, S.; Suslov, S.; Li, X.; Klimeck, G.; Janes, D. B.; Appenzeller, J. Effect of Diameter Variation on Electrical Characteristics of Schottky Barrier Indium Arsenide Nanowire Field-Effect Transistors. ACS Nano 2014, 8, 6281−6287. (36) Sui, Y.; Appenzeller, J. Screening and Interlayer Coupling in Multilayer Graphene Field-Effect Transistors. Nano Lett. 2009, 9, 2973−2977. (37) Hwang, E. H.; Das Sarma, S. Dielectric Function, Screening, and Plasmons in Two-Dimensional Graphene. Phys. Rev. B: Condens. Matter Mater. Phys. 2007, 75, No. 205418. (38) Katsnelson, M. I. Nonlinear Screening of Charge Impurities in Graphene. Phys. Rev. B: Condens. Matter Mater. Phys. 2006, 74, No. 201401. (39) Das, S.; Appenzeller, J. Screening and Interlayer Coupling in Multilayer MoS2. Phys. Status Solidi RRL 2013, 7, 268−273. (40) Kwon, H.; Choi, W.; Lee, D.; Lee, Y.; Kwon, J.; Yoo, B.; Grigoropoulos, C. P.; Kim, S. Selective and Localized Laser Annealing Effect for High-Performance Flexible Multilayer MoS2 Thin-film Transistors. Nano Res. 2014, 7, 1137−1145. (41) Lee, C.-H.; Vardy, N.; Wong, W. Multilayer MoS2 Thin-film Transistors Employing Silicon Nitride and Silicon Oxide Dielectric Layers. IEEE Electron Device Lett. 2016, 37, 731−734. (42) Zou, X.; Wang, J.; Chiu, C.-H.; Wu, Y.; Xiao, X.; Jiang, C.; Wu, W.-W.; Mai, L.; Chen, T.; Li, J.; Ho, J. C.; Liao, L. Interface Engineering for High-Performance Top-Gated MoS2 Field-Effect Transistors. Adv. Mater. 2014, 26, 6255−6261. (43) Pradhan, N. R.; Rhodes, D.; Zhang, Q.; Talapatra, S.; Terrones, M.; Ajayan, P. M.; Balicas, L. Intrinsic Carrier Mobility of MultiLayered MoS2 Field-Effect Transistors on SiO2. Appl. Phys. Lett. 2013, 102, No. 123105. (44) Schmidt, H.; Wang, S.; Chu, L.; Toh, M.; Kumar, R.; Zhao, W.; Neto, A. H. C.; Martin, J.; Adam, S.; Ozyilmaz, B.; Eda, G. Transport Properties of Monolayer MoS2 Grown by Chemical Vapor Deposition. Nano Lett. 2014, 14, 1909−1913. (45) Zhang, E.; Wang, W.; Zhang, C.; Jin, Y.; Zhu, G.; Sun, Q.; Zhang, D. W.; Zhou, P.; Xiu, F. Tunable Charge-Trap Memory Based on Few-Layer MoS2. ACS Nano 2015, 9, 612−619. (46) Kwon, H.-J.; Kim, S.; Jang, J.; Grigoropoulos, C. P. Evaluation of Pulsed Laser Annealing for Flexible Multilayer MoS2 Transistors. Appl. Phys. Lett. 2015, 106, No. 113111. (47) Lu, C.-P.; Li, G.; Mao, J.; Wang, L.-M.; Andrei, E. Y. Bandgap, Mid-gap States, and Gating Effects in MoS2. Nano Lett. 2014, 14, 4628−4633.

Multilayer MoS2 Film-based Field-effect Transistors for Sensing NO at Room Temperature. Small 2012, 8, 63−67. (11) Kim, S.; Konar, A.; Hwang, W.-S.; Lee, J. H.; Lee, J.; Yang, J.; Jung, C.; Kim, H.; Yoo, J.-B.; Choi, J.-Y.; Jin, Y. W.; Lee, S. Y.; Jena, D.; Choi, W.; Kim, K. High-mobility and Low-power Thin-film Transistors Based on Multilayer MoS2 crystals. Nat. Commun. 2012, 3, No. 1011. (12) Castellanos-Gomez, A.; Cappelluti, E.; Roldán, R.; Agraït, N.; Guinea, F.; Rubio-Bollinger, G. Electric-field Screening in Atomically Thin Layers of MoS2: The Role of Interlayer Coupling. Adv. Mater. 2013, 25, 899−903. (13) Das, S.; Gulotty, R.; Sumant, A. V.; Roelofs, A. All TwoDimensional, Flexible, Transparent, and Thinnest Thin Film Transistor. Nano Lett. 2014, 14, 2861−2866. (14) Pu, J.; Yomogida, Y.; Liu, K.-K.; Li, L.-J.; Iwasa, Y.; Takenobu, T. Highly Flexible MoS2 Thin-film Transistors with Ion Gel Dielectrics. Nano Lett. 2012, 12, 4013−4017. (15) Kwon, J.; Hong, Y. K.; Kwon, H.-J.; Park, Y. J.; Yoo, B.; Kim, J.; Grigoropoulos, C. P.; Oh, M. S.; Kim, S. Optically Transparent Thinfilm Transistors Based on 2D Multilayer MoS2 and Indium Zinc Oxide Electrodes. Nanotechnology 2015, 26, No. 035202. (16) Kwon, H.-J.; Jang, J.; Grigoropoulos, C. P. Laser Direct Writing Process for Making Electrodes and High-k Sol-Gel ZrO2 for Boosting Performances of MoS2 Transistors. ACS Appl. Mater. Interfaces 2016, 8, 9314−9318. (17) Miao, J.; Hu, W.; Jing, Y.; Luo, W.; Liao, L.; Pan, A.; Wu, S.; Cheng, J.; Chen, X.; Lu, W. Surface Plasmon-Enhanced Photodetection in Few Layer MoS2 Phototransistors with Au Nanostructure Arrays. Small 2015, 11, 2392−2398. (18) Sik Hwang, W.; Remskar, M.; Yan, R.; Kosel, T.; Kyung Park, J.; Jin Cho, B.; Haensch, W.; Xing, H.; Seabaugh, A.; Jena, D. Comparative Study of Chemically Synthesized and Exfoliated Multilayer MoS2 Field-effect Transistors. Appl. Phys. Lett. 2013, 102, No. 043116. (19) Sanne, A.; Ghosh, R.; Rai, A.; Yogeesh, M. N.; Shin, S. H.; Sharma, A.; Jarvis, K.; Mathew, L.; Rao, R.; Akinwande, D.; Banerjee, S. Radio Frequency Transistors and Circuits Based on CVD MoS2. Nano Lett. 2015, 15, 5039−5045. (20) Chen, M.; Nam, H.; Rokni, H.; Wi, S.; Yoon, J. S.; Chen, P.; Kurabayashi, K.; Lu, W.; Liang, X. Nanoimprint-Assisted Shear Exfoliation (NASE) for Producing Multilayer MoS2 Structures as Field-Effect Transistor Channel Arrays. ACS Nano 2015, 9, 8773− 8785. (21) Castellanos-Gomez, A.; Barkelid, M.; Goossens, A. M.; Calado, V. E.; van der Zant, H. S. J.; Steele, G. A. Laser-Thinning of MoS2: on Demand Generation of a Single-Layer Semiconductor. Nano Lett. 2012, 12, 3187−3192. (22) Zhang, W.; Huang, J.-K.; Chen, C.-H.; Chang, Y.-H.; Cheng, Y.J.; Li, L.-J. High-Gain Phototransistors Based on a CVD MoS2 Monolayer. Adv. Mater. 2013, 25, 3456−3461. (23) Das, S.; Chen, H.-Y.; Penumatcha, A. V.; Appenzeller, J. High Performance Multilayer MoS2 Transistors with Scandium Contacts. Nano Lett. 2013, 13, 100−105. (24) Kappera, R.; Voiry, D.; Yalcin, S. E.; Jen, W.; Acerce, M.; Torrel, S.; Branch, B.; Lei, S.; Chen, W.; Najmaei, S.; Lou, J.; Ajayan, P. M.; Gupta, G.; Mohite, A. D.; Chhowalla, M. Metallic 1T Phase Source/ Drain Electrodes for Field Effect Transistors from Chemical Vapor Deposited MoS2. APL Mater. 2014, 2, No. 092516. (25) Huo, N.; Kang, J.; Wei, Z.; Li, S.-S.; Li, J.; Wei, S.-H. Novel and Enhanced Optoelectronic Performances of Multilayer MoS2 -WS2 Heterostructure Transistors. Adv. Funct. Mater. 2014, 24, 7025−7031. (26) Yuan, H.; Cheng, G.; You, L.; Li, H.; Zhu, H.; Li, W.; Kopanski, J. J.; Obeng, Y. S.; Hight Walker, A. R.; Gundlach, D. J.; Richter, C. A.; Ioannou, D. E.; Li, Q. Influence of Metal-MoS2 Interface on MoS2 Transistor Performance: Comparison of Ag and Ti Contacts. ACS Appl. Mater. Interfaces 2015, 7, 1180−1187. (27) Sundaram, R. S.; Engel, M.; Lombardo, A.; Krupke, R.; Ferrari, A. C.; Avouris, P.; Steiner, M. Electroluminescence in Single Layer MoS2. Nano Lett. 2013, 13, 1416−1421. 8370

DOI: 10.1021/acsami.6b15419 ACS Appl. Mater. Interfaces 2017, 9, 8361−8370