Probing Interface Defects in Top-Gated MoS2 ... - ACS Publications

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Probing Interface Defects in Top-Gated MoS2 Transistors with Impedance Spectroscopy Peng Zhao,† Angelica Azcatl,† Yuri Y. Gomeniuk,‡,§ Pavel Bolshakov,† Michael Schmidt,‡ Stephen J. McDonnell,∥ Christopher L. Hinkle,† Paul K. Hurley,‡ Robert M. Wallace,† and Chadwin D. Young*,† †

Department of Materials Science and Engineering, The University of Texas at Dallas, 800 W Campbell Rd., Richardson, Texas 75080, United States ‡ Tyndall National Institute, Department of Chemistry, University of College Cork, Lee Maltings, Dyke Parade, Cork, Ireland § V. Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine, 41, pr. Nauki, Kyiv, Ukraine ∥ Department of Materials Science and Engineering, The University of Virginia, Charlottesville, Virginia 22903, United States S Supporting Information *

ABSTRACT: The electronic properties of the HfO2/MoS2 interface were investigated using multifrequency capacitance− voltage (C−V) and current−voltage characterization of topgated MoS2 metal−oxide−semiconductor field effect transistors (MOSFETs). The analysis was performed on few layer (5−10) MoS2 MOSFETs fabricated using photolithographic patterning with 13 and 8 nm HfO2 gate oxide layers formed by atomic layer deposition after in-situ UV-O3 surface functionalization. The impedance response of the HfO2/MoS2 gate stack indicates the existence of specific defects at the interface, which exhibited either a frequency-dependent distortion similar to conventional Si MOSFETs with unpassivated silicon dangling bonds or a frequency dispersion over the entire voltage range corresponding to depletion of the HfO2/MoS2 surface, consistent with interface traps distributed over a range of energy levels. The interface defects density (Dit) was extracted from the C−V responses by the high−low frequency and the multiple-frequency extraction methods, where a Dit peak value of 1.2 × 1013 cm−2 eV−1 was extracted for a device (7-layer MoS2 and 13 nm HfO2) exhibiting a behavior approximating to a single trap response. The MoS2 MOSFET with 4-layer MoS2 and 8 nm HfO2 gave Dit values ranging from 2 × 1011 to 2 × 1013 cm−2 eV−1 across the energy range corresponding to depletion near the HfO2/MoS2 interface. The gate current was below 10−7 A/cm2 across the full bias sweep for both samples indicating continuous HfO2 films resulting from the combined UV ozone and HfO2 deposition process. The results demonstrated that impedance spectroscopy applied to relatively simple top-gated transistor test structures provides an approach to investigate electrically active defects at the HfO2/MoS2 interface and should be applicable to alternative TMD materials, surface treatments, and gate oxides as an interface defect metrology tool in the development of TMD-based MOSFETs. KEYWORDS: molybdenum disulfide (MoS2), high-k dielectrics, interface defects, electrical characterization, top-gated transistors, capacitance−voltage (C−V)

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INTRODUCTION Over the past decade, two-dimensional (2-D) materials have attracted considerable attention due to their atomically thin structure and their unique electronic, optical, and mechanical properties.1−3 Among these materials, transition metal dichalcogenides (TMDs) have demonstrated satisfactory energy bandgap values and promising properties for future applications in electronics and optoelectronics.4−17 Molybdenum disulfide (MoS2), as the most explored TMD material, has been reported to exhibit an electron mobility of 55 cm2/(V s) in a top-gated transistor with a single layer of MoS24−6 and a theoretical value of 410 cm2/(V s) at room temperature.7 Moreover, compared with monolayer MoS2, few-layer MoS2 © 2017 American Chemical Society

has been predicted and experimentally demonstrated as an excellent channel material to achieve high mobility and reduced contact resistivity.8−12 With the ultimate electrostatic control due to the 2-D structure, an energy gap in the range of 1.2−1.8 eV, and the high mobility value, MoS2 is especially attractive for high performance, low power-consumption flexible electronics.1,10,18,19 As the utilization of high dielectric constant (high-k) gate oxide material in conventional silicon CMOS processing has Received: May 3, 2017 Accepted: June 26, 2017 Published: June 26, 2017 24348

DOI: 10.1021/acsami.7b06204 ACS Appl. Mater. Interfaces 2017, 9, 24348−24356

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ACS Applied Materials & Interfaces

situ UV-O3 functionalization26,27 and 8−13 nm ALD HfO2, which are among the thinnest high-k dielectrics on top-gate TMD MOSFETs to date. As we use photolithography for source/drain and gate patterning, the gated area is sufficiently large for C−V characterization. Both transistor performance and gate−stack interface properties were characterized, with an emphasis on the impedance spectroscopy of the dielectric. The interface defect density (Dit) was extracted and analyzed by three different methods. Besides reporting the interface properties of our transistors, the methodology can be potentially applied to other TMDs and surface functionalization, beyond MoS2 and UV-O3 treatment.

been demonstrated to reduce the gate leakage and enable further scaling of transistors, high-k dielectrics are also considered extensively for TMD transistors.5,10,11,16,18−28 In addition, high-k materials can suppress the Coulombic scattering in low-dimensional nanostructures, increasing the carrier mobility, as shown in the literature with both theoretical simulation20 and experimental evidence.5,11 Although backgated structures are ideal for contact and doping research on TMD transistors,8,29,30 top-gated devices are more attractive for integrated circuit manufacturing. Thus, investigating high-k deposition on TMDs and understanding the interface properties is an important scientific and technological research area. An obstacle of integrating high-k dielectrics on these 2-D materials is the lack of bonds available at the surface that enables thin film deposition.21,22 Many top-gated transistors in the literature adopted thick gate dielectric deposition, usually from 15 to 50 nm,5,11,16,23 to avoid pinholes and nonuniformity in the dielectric. Recently, multiple surface functionalization methodologies have been reported for thin, uniform high-k dielectric deposition on MoS2.22,24−27 Metal seed layers,24 oxygen plasma treatment,22,25 and ultraviolet-ozone (UV-O3) treatment26,27 are promising predeposition approaches to gain a uniform dielectric layer. However, since the ultimate goal of these approaches is the enhancement of electronic device performance, detailed reports on device performance related to the impacts of these treatments is vital, but only shown in a few papers.24,25,31 Our previous research suggested that defects existed at the high-k/MoS2 interface region after an ex-situ UVO3 treatment,28 but the gate oxide leakage on these large area MOS structures affected the analysis, due to the rough surface of the bulk MoS2 sample and relatively large capacitor area. Recently, Azcatl et al.26,27 reported that the nondestructive (i.e., no Mo-oxide formation) in-situ UV-O3 treatment featured a uniform atomic layer deposited (ALD) high-k oxide without unexpected interfacial layers for exfoliated MoS2. Impedance measurements are recognized as one of the fastest and most robust methods to investigate properties of a dielectric and its interface with the underlying substrate. However, impedance measurements of metal/high-k dielectric/TMD MOS system have only been reported in a limited number of works.10,11,18,31−33 Most publications report capacitance−voltage (C−V) curves without further analysis,10,11,32 or back-gated capacitors with high-k deposited on Si.33 Recently, Park et al.31 reported C−V characteristics of capacitors with Al2O3 on 100−200 nm thick MoS2 yielding Dit values of 1011−1014 cm−2 eV−1. For high-k on chemical-vapordeposited (CVD) MoS2 thin films, a comprehensive study of dielectric impedance was performed, showing Dit extraction and modeling work based on capacitors with 30 nm ALD HfO2 on monolayer MoS2 with 2 nm Al as an interfacial seed layer.18 Another relevant and useful Dit extraction work has been reported by Takenaka et al.,33 which uses the Terman method to analyze and compare interfaces of MoS2 and SiO2/HfO2/ Al2O3. The extracted Dit values are about 1 × 1013 cm−2 eV−1 regardless of the dielectric selection for back-gated devices on semibulk MoS2. However, the device architecture may not be commensurate with the necessary solution for continued device scaling where top-gated architectures dominate. Here, dielectric/substrate interfaces are dependent upon how device fabrication was executed and therefore should be investigated in this context. In this work, we designed and fabricated top-gated transistors on exfoliated, few-layer MoS2 as the test structures, with an in-

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EXPERIMENTAL METHODS

The transistor structure used for the few-layer MoS2 MOSFETs examined in this work is shown in Figure 1a. Before device fabrication,

Figure 1. (a) Schematic cross section of the top-gated MoS2 field effect transistor structure used in this work. Gate stack: Au/Cr/HfO2/ MoS2. (b) Cross-sectional transmission electron microscopic image of the metal/HfO2/MoS2 transistor gate stack. 13 nm HfO2 is uniformly deposited on a 7-layer MoS2 flake, showing no evidence of unintentional oxidation of the MoS2 surface. 270 nm SiO2 was thermally grown on highly doped p-type Si wafers as a substrate. Few-layer MoS2 flakes were mechanically exfoliated from commercially available natural MoS2 crystals and transferred onto the SiO2. By using conventional photolithography, we aligned a source/ drain pattern on the photomask directly on the selected flake. After patterning, Au/Ti (380/20 nm) was deposited as contacts in an ebeam evaporator at 2 × 10−6 Torr, followed by a lift-off process. Thereafter, a 15 min in-situ UV-O3 surface treatment26 was performed. The UV-O3 is generated based on irradiance from the fused quartz envelope, low-pressure UV Hg lamp employed previously26,27 and is estimated to be 5 mW/cm2 which ensures no etching or Mo-oxide formation according to Park et al.31 Following the UV-O3 surface preparation, HfO2 was deposited at 200 °C in the ALD chamber 24349


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Figure 2. Electrical characterization of device with 13 nm HfO2 and 7-layer MoS2 (L = 6.5 μm, W = 9.5 μm). (a) IDS−VGS: ION/IOFF = 106 with ultralow gate leakage; (b) IDS−VDS with VGS from −4 to 0 V; (c) C−V: frequency dependence, where a “hump” in the range −2.5 to −3.5 V is indicating an interface defect response. The 0.6 V stretch-out of 500 kHz curve indicates the Fermi energy pinning at the MoS2/HfO2 interface.

possibility due to the fixed positive charge in the dielectric layer(s). Similar large |VT| was also observed by other researchers using top-gated MoS2 transistors with high-k dielectrics.11,24 Since the HfO2 is deposited at low temperature (200 °C) with no postdeposition annealing (to assess the UVO3 treatment without convolution from additional annealing), a possible net oxide charge being present in the HfO2 layer may result. Furthermore, possible contribution of induced charges in the underlying SiO2 from potential X-rays exposure during the electron beam deposition processwhich was used to form the metal gate and source/drain regionscould occur. Thus, both oxide layers could possess trapped charge. Assuming the threshold voltage shift ΔV = −3 V originates from oxide charges, the density of the positive fixed charges can be estimated by Qf/q = −CoxΔV/q = 1.4 × 1013/cm2. Figure 2b shows the IDS−VDS curves with VGS swept from −4 to 0 V. A nonlinear region was observed at low VDS, likely because of high resistance Schottky barriers at the source/drain contacts associated with this unannealed device.5,34 This is expected, as there is no intentional doping in the MoS2 film in the source and drain region. As is the case in conventional 3D semiconductors, increasing the doping in the MoS2 film to high concentrations (>1 × 1019 cm−3), for example via Nb doping,35 significantly reduces the specific contact resistivity at the Ti/MoS2 interface. In addition, it is noted from Figure 1a

immediately after the treatment without a break in a vacuum. The thermal ALD used H2O and TDMA-Hf as the precursors and started the deposition with a TDMA-Hf pulse. We intentionally avoided annealing the HfO2 after deposition to study the effects of the UV-O3 functionalization treatment and its role on HfO2/MoS2 interface properties without the impact of any subsequent annealing. The final step of fabrication was patterning and evaporating of Au/Cr (250/50 nm) metal gate. The typical MoS2 thickness studied in our work was about 5−10 layers (3−6 nm). The device size was determined by both lithography and the flake shape. Electrical measurements in this work were performed using a Keithley 4200 semiconductor characterization system and an Agilent E4980A LCR meter at room temperature (25 °C) in a shielded probe station.

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RESULTS AND DISCUSSION A high-resolution transmission electron microscopic (TEM) image is shown in Figure 1b, illustrating the cross section of a device gate stack with 7-layer MoS2 and a 13 nm HfO2 dielectric. The active channel length under the metal gate is 6.5 μm, and the channel width is 9.5 μm. Figure 2a shows the IDS−VGS and the gate leakage characteristics for this MoS2 transistor. VDS was kept at 0.5 V. An excellent on/off ratio of 106 was observed, with an ultralow leakage current on the gate. The MoS2 was intrinsically n-type doped, consistent with our previous observation28 and literature reports.5,8,24,29 The relatively large negative threshold voltage (VT = −3 V) is 24350


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V curves possibly convoluted positive oxide charge with interface defects in the Dit extraction process. The techniques that we are about to describe to analyze the Dit are only valid when the device is not fully depleted, which must be carefully adhered to when using very thin flakes. In this work, the flake is not fully depleted over the bias range where the Dit response is detected. If the MoS2 thin film is fully depleted, the capacitance should be 0 F (or at a constant number over a voltage range due to parasitic capacitance components).41 As shown in Figure 3a, at about −3 V where interface traps are detected, the transistor is not fully turned off (i.e., not fully depleted and still has carriers in the flake responding to the ac signal). Further evidence, based on series resistance analysis (Supporting Information Figures S1 and S2),

that the top-gated MOSFET has nongated regions between the gate edge and the source and drain contacts (approximately 1− 2 μm on each side), which is another source of series resistance in the structure. To investigate the electronic properties at HfO2/MoS2 interface, the source and drain were connected to one terminal of the LCR meter, while the gate was connected to the other terminal. Variable frequency C−V measurements were conducted. The back-gate contact was intentionally floated to minimize the effect from oxide charge in the underlying SiO2. The frequency dependence is shown in Figure 2c. Since this transistor operates in accumulation mode, the reaction of the majority carriers (electrons) to the ac signal is observed. In contrast to our previous study on the ex-situ UV-O3 treatment and bulk MoS2 crystals,28 these C−V frequency dependence results showed a highly improved high-k/MoS2 interface, with significantly less dispersion and lower gate leakage due to the in-situ UV-O3 treatment and the few-layer TMD thickness. The C−V characteristics demonstrate an approximately constant capacitance for positive gate voltage, corresponding to the HfO2 gate oxide capacitance, and a decrease in capacitance in the region −2 to −4 V, consistent with depletion of negative charge at the HfO2/MoS2 interface. It is noted that the region of surface depletion in the C−V response in Figure 2c is consistent with the subthreshold region in the transfer characteristics in Figure 2a. The measured accumulation capacitance is 0.76 μF/cm2. Based on cross-section TEM images, the HfO2 is 13 nm, and assuming a k value of 17 for ALD grown HfO2, this would yield a maximum capacitance value of 1.1 μF/cm2. The lower value obtained experimentally suggests the possibility of a lower k value interface transition region between the HfO2 and the MoS2 which is not immediately obvious from the TEM analysis. In the capacitance−voltage response in the region −4 to −2 V, a frequency-dependent distortion (“hump”) in the depletion region is observed, which is consistent with an electrically activated trap response at the high-k/MoS2 interface region. In conventional Si MOSFETs with either SiO2 or high-k oxides, this “hump” is usually attributed to interface traps which exhibit a peak density at a specific energy in the bandgap,36,37 and usually a forming gas anneal around 400 °C can passivate the defects,38,39 which are primarily silicon dangling bond (Pb) defects. The C−V response of Si control sample under the same ALD condition was reported in our previous work.28 HfO2 formed at low temperature (200 °C), without any higher temperature annealing in N2 or H2/N2 can exhibit gap states which result in C−V hysteresis, interface defect response, and lower than expected dielectric constant. However, the HfO2/Si control sample will not be representative of the HfO2/MoS2 interface due to the different substrate material and interfacial condition (e.g., the Si substrate surface will spontaneously form a SiO2-like interfacial layer during an ALD process, which primarily determines the interfacial property of the HfO2/Si40). Published C−V frequency dependence data on a metal/(30 nm) HfO2/monolayer MoS2 gate stack was reported by Zhu et al.,18 where chemical vapor deposited (CVD) MoS2 was utilized in the device structure. Compared with the device based on CVD MoS2, this gate stack with mechanically exfoliated MoS2 shows much less frequency dispersion, suggesting significantly fewer interface defects. A limited study of the C−V frequency dependence on semibulk MoS2 with Al2O3 has also been reported,31 where interface defects (Dit) ranging from 1011 to 1014 cm−2 eV−1 were reported. However, the lateral shift of C−

Figure 3. (a) ID−VG and multifrequency C−V overlaid to illustrate the impact of Dit in both measurements occurs at the same Vg. SS is degraded due to interface traps, and Dit = 1.6 × 1013 cm−2 eV−1 is estimated. (b) Energy band diagram of high-k/MoS2 interface and equivalent circuits. (i) At gate voltages higher than −2.8 V or lower than −3.4 V, the total ac capacitance is due to the Cox and CMoS2 connected in series. (ii) At gate voltage between −3.4 and −2.8 V, the EF is pinned at interface, and there is an ac response at low frequencies due to Dit but no ac response at high frequencies. 24351


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Figure 4. Dit extraction. (a) Dit vs VGS, calculated by high−low frequency method. (b) Replotted “capacitance vs voltage” to “capacitance vs frequency” (dots) and modeling (solid lines). (c) Dit vs VGS and τit vs VGS, from the modeling work in (b). (d) Comparison of two Dit extraction methods in (a) and (c), showing similar Dit distribution, with a Dit peak at 1.2 × 1013 cm−2 eV−1.

confirms that the device is not fully depleted in the Vg range used to analyze the Dit from the multifrequency C−V measurements. Because of the influence of the interface traps, the inverse subthreshold slope (SS) also increases at around −3 V. This change of SS is also consistent with the charging of MoS2/HfO2 interface traps providing an independent measurement technique indicating that the C−V response is detecting interface traps at the corresponding region of the C−V response. SS can be used to roughly estimate Dit since SS = 60 mV·[1 + (Cdm + Cit)/Cox], where Cdm is the capacitance of depleted MoS2 and Cit is the capacitance due to interface traps. Thus, Cit and Dit(Cit/q) can be estimated by comparing the change in SS around −3.8 V (110 mV/dec) and around −3.2 V (318 mV/dec). The calculated result gives Dit = 1.6 × 1013 cm−2 eV−1. Next, we quantified the Dit from the C−V response (Figure 2c). As the frequency is increased from 1 to 500 kHz, this reduces the ac response of the interface defects to the measured capacitance, resulting in the dispersion of capacitance with frequency noted in the region from −2.5 to −3.5 V in Figure 2c. In the limit of increasing frequency, the interface defects will only respond to the dc bias (high frequency Dit response), and the interface states will be evident as a “plateau” region of the C−V in the case where the interface states are located in a narrow band of energies. From Figure 2c, at frequencies above 100 kHz, an approximate plateau region is observed. At 500 kHz this region extends from −2.8 to −3.4 V. We interpret this

0.6 V gate voltage region to be due to the dc response of the defects.42 This is illustrated in schematic energy band diagrams in Figure 3b, with surface Fermi level pinning due to interface states with a peak density in a specific energy in the band gap.a The total density of interface defects, in the areal density units of cm−2, can be estimated from the oxide capacitance and the width of the plateau region in the 500 kHz C−V response, and this yields an interface trap density Dit = 2.7 × 1012 cm−2. A more detailed calculation is shown in Figure S.3. Although the possibility that the defects still respond with ac signal at 500 kHz could not be fully excluded, an abrupt C−V distortion due to peaked distribution of interface defects42 is consistent with our following Dit extraction and analysis. Figure 4a shows the Dit calculated by the conventional highlow frequency method42 from equations −1 −1 ⎛ 1 ⎛ 1 1 ⎞ 1 ⎞ − − C it = ⎜ ⎟ −⎜ ⎟ Cox ⎠ Cox ⎠ ⎝ C LF ⎝ C HF

(1)

Dit = C it /q

(2)

where capacitance of interface traps (Cit) represents the capacitance when all the traps reacted with ac signal at low frequency; CLF and CHF are the capacitance measured at 1 and 500 kHz, respectively. In Figure 4a, the polynomial function is a guide to the eye. Dit ranges from the order of 1012 to 1013 cm−2 eV−1, with a peak value of 1.2 × 1013 cm−2 eV−1. The peak value is 1 order of magnitude lower than what was reported in ref 31 24352


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Figure 5. Electrical characterization and Dit extraction of a device with 8 nm HfO2 and 4-layer MoS2 (W = 7.2 μm, L = 5.6 μm). (a) IDS−VGS and gate leakage. (b) Corresponding IDS−VDS. (c) C−V: frequency dependence; C−V curves disperse in the entire depletion voltage range, indicating interface traps in range of energy levels. (d) Dit vs VGS and τit vs VGS, Dit ranges from 2 × 1011 to 2 × 1013 cm−2 eV−1, with both H−L frequency method and multifrequency method.

defects response in the C−V characteristic. From Figure 4b, the values of Dit, and the corresponding τit values, can be determined at each gate voltage, and the characteristics are shown in Figure 4c. The two methods are compared in Figure 4d, demonstrating consistency between the two Dit extraction approaches. Detailed modeling work for these two methods can be found in Figures S.3 and S.4. Because of possible variation in the electronic properties of exfoliated MoS2 flakes for differing samples, and within a given crystal, in addition to contaminants and the presence of surface defects,44 we applied the same methods on a different MoS2 transistor with 8 nm HfO2 and a 4-layer MoS2 flake to verify if the C−V analysis method is more broadly applicable. Figures 5a and 5b show the I DS −V GS , gate leakage and I DS −V DS characteristics of this transistor. The gated area is width × length = 7.2 μm × 5.6 μm. Figures 5c and 5d show the C−V frequency dependence, along with the extracted Dit with two methods. The C−V frequency dispersion (Figure 5c) suggests a different distribution of interface defects at the HfO2/MoS2 interface compared to the sample analyzed in Figure 4. The frequency-dependent C−V characteristics are consistent with an interface state density distributed throughout the MoS2 energy gap at the HfO2/MoS2 interface. Figure 5d shows the Dit and τit extracted using high-low frequency and multifrequency methods. The magnitudes of Dit and τit are comparable to the 7-layer MoS2 flake MOSFET shown in Figure 4, but in this case no peak in Dit is evident. Similar variation has also been reported in other publications using

using the same high−low frequency method and aluminum oxide as the dielectric. It is in the same range as the defect density in the literature for exfoliated MoS2 by photoexcited charge collection spectroscopy.43 Translating each gate voltage in Figure 4a to a corresponding surface potential at the MoS2/ HfO2 interface requires a known value of the active n-type doping concentration in the MoS2. This value is not readily known for the geological samples employed here, and as a consequence, the Dit versus energy in the MoS2 energy gap cannot be determined for these devices. An alternative method was also employed to extract Dit.18 Instead of only using the C−V data of high and low frequencies, data from the complete span of frequencies were used, and using this approach both Dit and the trap time constant τit can be extracted. (The importance of τit is that one can extract the trap cross section, σ, and trap energy, ET, with temperaturedependent experiments33 to understand the physical origin of the interface traps, and this is beyond the scope of this work.) In this multifrequency method, Cit is determined by Dit and τit at certain voltages. C it =

qDit 1 + ω 2τit 2

(3)

where ω = 2πf, and f is the applied ac frequency. Thus, at certain voltages, Dit and τit can be extracted from the C−f or C−ω relationship. Figure 4b shows the measured data (symbols) and model fit (lines) for the capacitance versus frequency for the voltage range corresponding to the interface 24353


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ACS Applied Materials & Interfaces thicker MoS2 layers,33 and the variation from sample to sample (with nominally identical processing) is also manifest in the transport properties.32 This variability in interface and transport properties is most likely a consequence of the high density and variability of impurities and defects in both geological and grown MoS2.44,45 Interfacial sulfur vacancies46,47 and other types of surface structural defects48 are the defects often observed by researchers and can potentially generate these defect responses in the impedance measurement. One possible suggestion for the defect level which shows a peak response at a specific energy in the band gap (Figure 4) is that the defect results from sulfur vacancies,33 which is reported to have an energy level of 0.35 eV from mid gap, from measurements.46 The alternative behavior of an almost constant Dit across the energy gap (Figure 5), observed in this work and in the literature,33 could be a consequence of the area of the certain devices not containing S vacancies within the gate area probed. Both cases (peaked Dit and uniform Dit) were also reported in ref 33, showing C−V response of MOS capacitors on semibulk MoS2 flakes, indicating that the samples that we report in this work are representative. We also suspect that the defect response observed in our devices can potentially originate from other impurities and defects present in the flake source44,45 (i.e., the exfoliated MoS2 crystal), which can exhibit equivalent surface density values in the range 1 × 1012−1 × 1013 cm−2. In addition, it is possible that the response could originate from defects located in an interfacial transition region between the MoS2 and the HfO249−51 because this methodology can also capture border trap response. This is also the subject of ongoing studies. This work provides a relatively easy fabrication procedure and robust electrical characterization methodology to study top-gated metal/high-k/TMD devices. The multifrequency C− V response of the structure is consistent with the existence of electrically active defects at the interface between high-k and MoS2. By combining with simulation and other physical characterization, a route to understand and passivate electrically active interface defects in high-k gate TMD MOSFETs is possible.

values which allow modulation of the Fermi level at the HfO2/ MoS2 interface. The relatively simple MOSFET test structure, combined with the gate to channel C−V response, indicates the existence of specific electrically active HfO2/MoS2 interface defects, and combining these results with simulation and other physical characterization methods, will provide an increased understanding of the physical origin of defects as well as a method to monitor the impact of different high-k oxides and varying surface preparations on the interface state density at high-k/MoS2 interfaces.

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.7b06204. Proposed equivalent circuits of C−V characterization; series resistance analysis and full depletion of MoS2 flake; number of interface defects (Nit) extraction from C−V curves; defects density (Dit) calculation by high−low frequency method; Dit and traps time constant τit extraction by the multifrequency method (PDF)

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. ORCID

Robert M. Wallace: 0000-0001-5566-4806 Chadwin D. Young: 0000-0003-0690-7423 Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This work is funded by NSF UNITE US/Ireland R&D Partnership for support under NSF-ECCS-1407765 and Science Foundation Ireland under the US-Ireland R&D Partnership Programme Grant SFI/13/US/I2862.

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ADDITIONAL NOTE The plateau region is not a constant capacitance. This would only occur for a monoenergetic defect level at a temperature of 0 K.

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a

CONCLUSION In conclusion, we designed and photolithographically fabricated top-gated FETs on exfoliated, few-layer MoS2 flakes, with an insitu UV-ozone functionalization treatment and 8 nm to 13 nm ALD HfO2 dielectrics. Both the transistor performance and the gate-stack interface properties were characterized electrically. Based on impedance spectroscopy of the HfO2/MoS2 gate stack in the MOSFET structure, Dit was extracted from the frequency dependence of the C−V response using two different methods. The interface state density values were in the range 1 × 1012−1 × 1013 cm−2 eV−1 for the devices studied, with trapping time constants in the range 1 × 10−5 to 1 × 10−6 s. One device with 7-L MoS2 and 13 nm HfO2 as the gate oxide exhibited a C−V response consistent with a Dit distribution peaking at a value of 1.2 × 1013 cm−2 eV−1 at a specific energy in the MoS2 band gap. A second device with 4-L MoS2 and 8 nm HfO2 yielded Dit values ranged from 2 × 1011 to 2 × 1013 cm−2 eV−1 with no peak value of Dit observed. The device performance and interface properties indicate that the UVozone functionalization is promising for MoS2-based devices with high-k dielectrics to achieve low leakage, thin and continuous high-k oxide layers, with interface state density

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REFERENCES

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Probing Interface Defects in Top-Gated MoS2 ... - ACS Publications

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