Realization of Functional Complete Stateful Boolean Logic in

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Realization of Functional Complete Stateful Boolean Logic in memristive crossbar Yi Li, Yaxiong Zhou, Lei Xu, Ke Lu, Zhuo-Rui Wang, Nian Duan, Lei Jiang, Long Cheng, Ting-Chang Chang, Kuan-Chang Chang, Hua-Jun Sun, Kan-Hao Xue, and Xiangshui Miao ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b11465 • Publication Date (Web): 25 Nov 2016 Downloaded from http://pubs.acs.org on November 29, 2016

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ACS Applied Materials & Interfaces

Realization of Functional Complete Stateful Boolean Logic in memristive crossbar Yi Li, †,‡,# Ya-Xiong Zhou,†,‡Lei Xu,†,‡ Ke Lu,†,‡ Zhuo-Rui Wang, †,‡ Nian Duan,†,‡ Lei jiang,†,‡ Long Cheng, †,‡ Ting-Chang Chang,# Kuan-Chang Chang,§ Hua-Jun Sun, †,‡ Kan-Hao Xue,†,‡ and Xiang-Shui Miao*,†,‡ † School of Optical and Electronic Information, Huazhong University of Science and Technology (HUST), Wuhan 430074, China. ‡ Wuhan National Laboratory for Optoelectronics (WNLO), Huazhong University of Science and Technology, Wuhan 430074, China. # Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan.

§ Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 804, Taiwan

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ABSTRACT

Nonvolatile stateful logic computing in memristor is a promising paradigm to realize the unity of information storage and processing in the same physical location, which has shown great feasibility to break the von Neumann bottleneck in traditional computing architecture. How to reduce the computational complexity of memristor based logic function is a matter of concern. Here, based on a general logic expression, we proposed a method to implement arbitrary logic of complete 16 Boolean logic in two steps with one memristor in the crossbar architecture. A representative functional complete NAND logic is successfully experimentally demonstrated in the filamentary Ag/AgGeTe/Ta memristors to prove the validity of our method. We believe our work may promote the development of the revolutionary logic-in memory architectures. KEYWORDS: Memristor, AgGeTe, resistive switching, Boolean logic, functional completeness.

INTRODUCTION Memristor is the fourth independent two-terminal passive circuit element apart from the resistor R, the capacitor C, and the inductor L. Defined axiomatically via the constitutive relation between the pair of variables {q(charge), φ(flux linkage)}, memristor was first mathematically predicted by Leon Chua in 1971 from symmetric principles without experimental observation at that time.1 This unique electronic device can change its resistance according to the amount of change that flowed through it, thus multi-level resistance could be obtained under the external electrical stimulus. Until 2008 Hewlett Packard (HP) laboratory firstly linked this theoretical concept with the ubiquitous resistive switching phenomena in many materials or devices,2 such as oxides,3-5 chalcogenides,6,7 two-dimensional materials8-10 and organics.11-13 Since then,


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memristors have received explosive attention from both academic and industrial communities due to its prospective potential in various fields, such as high-density information storage (i.e. resistive

random

access

memory,

RRAM),14,15

neuromorphic

system16-19

and

logic

computing.20,21 Especially, implementation of logic computing is gaining unprecedented attention. Unlike the complementary metal-oxide-semiconductor (CMOS) transistor-based logic devices, the memristor is capable of performing nonvolatile stateful logic.21 In other words, the resistive states are utilized to represent logic value ‘0’ and ‘1’, rather than voltage level, and the logic computing results could be in-situ stored in the nonvolatile resistive states. This logic-inmemory functionality indicates that the memristor could be a key component to building highperformance parallel information processing platform. The von Neumann bottleneck in traditional computing architecture could be broken since logic and memory are combined together. So far, most recent researches have focused on the physical realization of memristors for a better understanding of the mechanisms and their tuning to obtain better performances in switching speed, energy efficiency, endurance, cycling, scalability and CMOS compatibility. Growing studies are dedicated to the experimental implementation of Boolean logic functions.22-31 To evaluate the performance of different memristive logic methodologies, several vital criteria are introduced, such as functional completeness and computation complexity. In logic, functional completeness problem means whether all possible truth tables can be expressed by a basic set of logical connectives.32 It is mathematically important and has a direct relationship to logical circuit design. For instance, in binary Boolean logic, {AND, NOT} and {NAND} are two wellknown complete set, thus all CMOS logic gates can be assembled from the NAND gates. Moreover, material implication (IMP) and False logic were shown to constitute a functional


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complete logic set based on which 16 distinct binary Boolean logic operations can be realized through iteration process.22,23 Computational complexity means the amount of resources needed to complete the computation.33 It includes spatial complexity and temporal complexity, which can be simply interpreted as the number of logic gates and logic cycles to implement a particular logic function. Via IMP and False logic, Borghetti et al. realized arbitrary Boolean logic in several basic circuits composed by two memristor and one fixed-value resistor with multiple logic cycles.22 For example, exclusive OR logic is realized through an equation: p XOR q = (p IMP q) IMP ((q IMP p) IMP 0). As another attractive logic method, sequential memristive logic has been proposed to implement an arbitrary Boolean logic in three steps using one binary or complementary device.23-25 Our previous work also demonstrated functional complete logic in three steps with an anti-series connected structure.26 The further optimization of logic operation methodology to reduce the computing complexity could be an important topic of memristor based computing. Moreover, few studies have considered the realization of logic operation in a crossbar structure which is a commonly accepted high-density integration architecture for largescale memristors.29,30,34,35 Here, we aim at the realization of functional complete binary Boolean logic with optimized computation complexity based on a general logic expression. Specifically, employing one memristor in the universal crossbar architecture, an arbitrary logic function could be accomplished within two steps: the initialization and logic computing, and to read out the logic results an extra read step is needed. In our experiments, Ag/AgGeTe/Ta memristors are fabricated as the demo. The repeatable resistive switching behaviors are ascribed to the formation and disruption of localized conductive metallic filaments. A representative functional complete NAND logic is successfully experimentally demonstrated.


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EXPERIMENTAL DETAILS Materials deposition. In this work, GeTe and AgGeTe films are deposited by means of direct current (DC) magnetron sputtering method at room temperature, using a germanium telluride target (99.99% purity, 4 in. in diameter) with silver slices. The base vacuum of the chamber was better than 1×10-5 Pa and the sputtering argon pressure was fixed at 0.5 Pa with a 30 W sputtering power. The Ag and Ta electrodes were deposited also by DC magnetron sputtering with 0.5 Pa argon pressure at room temperature. Film characterization. For characterization, 200 nm amorphous AgGeTe film samples were deposited on quartz and silicon substrates. The surface morphology was analyzed by atomic force microscopy (AFM, Bruker Dimension EDGE) in contact mode. The composition and chemical states were analyzed by X-ray photoelectron spectroscopy (XPS, AXIS-ULTRA DLD600W). The phonon vibrational modes of Ge atoms were studied by Raman scattering (LabRAM HR800), and the laser wavelength was 523 nm and the spot size of the incident laser beam was ~1 μm. Samples were annealed at different temperatures under vacuum ambient for X-ray diffraction (XRD, X’ Pert PRO Dy2198, Cu K-alpha radiation at a wavelength of 0.15418 nm, a scan rate of 0.2°/s) characterization to examine the structural variation. Device Fabrication and Characterization. The Ag 150/AgGeTe 10/Ta 100 (nm) memristors with a feature size of 20 µm in a crossbar architecture were fabricated on SiO2(1 µm)/Si substrates. Each layer was patterned using ultraviolet photolithography (Karl Suss MJB3) followed by film deposition and lift-off processes. Cross-sectional morphology of the device was observed by transmission Electron Microscope (TEM, Titan G2 60–300 Probe Cs Corrector HRSTEM). SEM/FIB Microscope (Quanta 3D FEG) was used to fabricate the cross-sectional


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samples for the TEM observation. The devices were wire-bonded to a ceramic package embedded in a custom printed circuit board high-speed interface module connecting to a picosecond pulse generator (picosecond Pulse Lab 10070A), a semiconductor characterization system (Agilent B1500) and an oscilloscope (Agilent DSO7104B). During the I–V and pulse measurements at room temperature in air, a 100 µA compliance current was applied, the positive bias was defined by the current flowing from the top Ag electrode to the bottom Ta electrode. The temperature dependence relation of the low resistance state was performed using a physical property measurement system (PPMS-9T, Quantum Design). RESULTS AND DISCUSSION Chalcogenide materials, such as Ag2S,6 GeSe,7 Cu2S,36 GeS,37 CuTe,38 CuGeTe,39 GeSbTe,40 and AgInSbTe,41 is one important class of solid-state electrolytes widely applied in the electrochemical metallization memristors (ECM) as the ionic transport layer. With a Ag (or Cu) active electrode acting as a cation source, the Ag electrode can easily be oxidized into Ag+ ions. On application of an electric field, Ag+ migrate into the solid electrolyte to form conductive filaments that bridge the bottom electrode. The high ion mobility in chalcogenide could result in a fast switching time. The thermal stability of the chalcogenide matrix layer against phase transition could be an important factor to survive from the thermal process during manufacturing and ensure the switching uniformity of the device.38 Our previous study has shown that the introducing of Ag dopant to modify the local order of Ge atom could enhance the thermal stability of amorphous GeTe materials.42 In this work, the material properties of silver-doped GeTe (AgGeTe) was characterized, then the resistive switching behavior of Ag/AgGeTe/Ta devices was investigated and utilized as the basis to verify the proposed logic methodology.


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GeTe and AgGeTe films are deposited via sputtering to study the effect of doped silver atoms on the structure of GeTe. Atomic force microscopy (AFM) was used to characterize the asgrown AgGeTe/Ta surfaces. The AFM image in Figure 1a reveals a well-deposited film with a root mean square roughness of 0.333 nm. The elemental composition of as-deposited amorphous GeTe and AgGeTe films was confirmed by X-ray photoelectron spectroscopy (XPS) analysis (Figure 1b). The Ge: Te atomic ratio for GeTe film is determined to be 52.33: 47.67, whereas the Ag: Ge: Te atomic ratio is approximate 4.48: 49.99: 45.53. Raman spectroscopy was employed to test both films, as shown in Fig 2b and 2c. The four main peaks at 80, 125, 160 and 215 cm-1 labeled as A, B, C, D are observed and in good agree with previous literature.43-45 For a quantitative analysis of individual vibrational modes, bands A, B, C can be further divided into two peaks each, denoted as A1, A2, B1, B2, and C1, C2. Especially, the peak B2 at 125 cm-1 and C1 at 156 cm-1 corresponds to the vibration modes of Ge atoms in defective octahedral and tetrahedral sites, respectively. It is clearly observed that for the AgGeTe film, the intensity of peak B2 decreases with increasing C1. That means through introducing of Ag atoms, the Ge atoms are more prone to be in tetrahedral environment rather than the octahedral one, while the latter is more similar to its local structure in crystalline phase. This variation in local order of Ge atoms results in the enhancement of thermal stability and a higher crystallization temperature of AgGeTe.42 The XRD results for GeTe and AgGeTe at different annealing temperatures also confirmed this tendency (Figure 1e and 1f). Diffraction of cubic phase are observed in GeTe film annealed at 200 °C, whereas AgGeTe still remains amorphous. Diffraction peaks belonging to rhombohedral structure emerge as the annealing temperature increases to 300 °C for the AgGeTe films, in consistence with previous studies.46,47


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Figure 1. Characterization of silver doped GeTe thin film. (a) 3D AFM image (scan size 1×1 μm2) of as-grown AgGeTe film surface on Ta bottom electrode. (b) Survey scan of X-ray photoelectron spectra of as-deposited GeTe (blue curve) and AgGeTe (read curve) films. The atom ratio of doped Ag is approximately 4.48%. Here we denote the Ag-doped film as Ag5%GeTe. (c) and (d) are Raman spectra for as-deposited GeTe and AgGeTe film, respectively. The variation of peak B2 and C1 indicates more Ge atoms in the rather than due to the Ag dopants. (e) and (f) are XRD results for as-deposited GeTe and AgGeTe film, respectively. A higher crystallization temperature is shown for AgGeTe, and the GeTe film shows a metastable cubic phase while only rhombohedral structure phase is found in crystallized AgGeTe film. Crossbar structural Ag/AgGeTe/Ta memristors were fabricated using standard ultra-violet lithography and lift-off processes, and then used for electronic characterization and logic computing. Figure 2a shows a top scanning electronic microscopy (SEM) view of the crossbar


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structure of 8×8 devices with Ag as the top electrodes. Figure 2b shows cross-sectional scanning transmission electron microscopy (TEM) of one device exhibiting extinct layered structure. The inset shows the diffuse halos of the fast Fourier transform (FFT) pattern verify the disordered amorphous phase of chalcogenide layer. Figure 2c shows the typical I-V characteristics measured by dc voltage sweeping from 0 V → 0.5 V → -0.5 V → 0 V without an electroforming process. A sudden increase in the current appeared at 0.27 V (current flows from Ag to Ta) representing a SET process from high resistive state (HRS) to low resistive state (LRS). Subsequently, the device recovers to HRS at -0.15 V in the RESET process. In the pulse mode measurement, our device exhibited fast switches between HRS and LRS. As shown in Figure 2d, the pulse width is fixed at 5 ns with increasing pulse amplitude. When the amplitude is less than approximately 3 V, the device remains at a HRS over 600 kΩ，whereas once the amplitude exceeds 3 V, the resistive switch to a ~ 2 kΩ LRS happens. Reversible switches under SET (−3.4 V, 5 ns) and RESET (3.4 V, 5 ns) pulses with an HRS/LRS ratio of 100 are shown in Figure 2e. Data retention test was performed to appraise the stability of the HRS and LRS with a reading bias of 0.05 V under ambient conditions. The device maintained the HRS/LRS ratio without noticeable degradation for 5000 s (Figure 2f).


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Figure 2. Characterization of Ag/AgGeTe/Ta memristor. (a) A scanning electron microscope (SEM) image of the crossbar devices. (b) Cross-sectional transmission electron microscopy (TEM) view of one memristor device in the red square area in Figure 1a. The inset shows the fast Fourier transform pattern of the AgGeTe area. The broad rings confirm the amorphous state. (c) Typical I-V characteristics showing bipolar resistive switching behaviors. The measured current values were plotted on a logarithmic scale. Arrows indicate the voltage sweep direction. The SET and RESET voltages are 0.27 V and -0.15 V, respectively. (d) The resistive switching behaviors under 5 ns pulses with different amplitudes. (e) Repetitive switching cycles with an over 100 HRS/LRS ratio by voltage pulses. The SET pulse and RESET pulse are (−3.4 V, 5 ns) and (3.4 V, 5 ns), respectively. (f) Retention test results up to 5000 s, confirming the nonvolatile nature of the states.


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To clarify the carrier transport mechanism in the device, the I-V curves were fitted as shown in Figure 3a. The fitting results show that HRS in set/reset states all exhibit ohmic conduction in low voltage region. When the voltage is further increased, the conduction is dominated by hopping mechanism, given by the linear relationship between ln(I) and V in Figure 3b and 3c. The hopping conduction can be explained by the shallow trapped electrons surpassing the energy barrier and forming leakage current in discontinuous residual metallic filament and the random distributed doped silver atoms.48 The negative temperature coefficient of resistance also indicates a semiconductor conduction behavior of the HRS (Figure S1 in Supporting Information). In contrast, the LRS is dominated by ohmic conduction (Figure. 3d and 3e), which is ascribed to the formation of stable metallic filament composed of silver atoms and ions. The temperature dependence of LRS was also measured. As shown in Figure 4f, LRS exhibits electronic transport behavior of metals, and the temperature coefficient of resistance (TCR) was calculated as 8.01×10-4 K-1, which is quite close to that of Ag filament of 7.86×10-4 K-1 as previously reported.49 The result suggests that the conduction channels could originate from the Ag clusters, which is consistent with the ECM theory and our fitting results. Figure 3g and 3h further illustrate the conduction processes in LRS and HRS, respectively. A positive voltage applied on the top oxidizable electrode leads to the dissolution of Ag and generation of Ag+. The cations migrate to the negatively biased counter Ta electrode, where they get reduced back to the neutral state and grown as a metallic filament in the AgGeTe electrolyte layer. This filament can then be dissolved by applying a negative voltage to the active electrode.


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Figure 3. Mechanism analysis of Ag/AgGeTe/Ta memristor. (a) Current fitting results for the bipolar I-V curve. Fitting curves for (b) HRS in the set process, (c) HRS in reset process both indicating hopping conduction. Ohmic conduction for (d) LRS in the set process, and (e) LRS in the reset process. (f) Temperature dependence of LRS. A temperature coefficient of resistance of 8.01×10-4 is close to that of Ag, indicating a filament with clustered Ag atoms. Illustration of the conduction mechanisms for (g) LRS and (h) HRS. The metallic filament formation and dissolution are responsible for the SET and RESET processes.

Next, we explain the proposed logic operation principle in a memristive crossbar array. Functional complete Boolean logic could be a fundamental basis for complex combinational and sequential logic computations. From previous publications, we already know that four logic variables could result in a complete logic through mathematical equations.24-26 Hence, in our


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method, the key is how to define the four mathematical variables by physical representations in the crossbar array. For the binary logic, every variable contains two distinctive physical states to affect the final logic result. In our work, the implementation of an arbitrary Boolean logic function requires two write cycles, named “initialization” and “logic operation” step, respectively. Then one additional non-destructive read step is needed to read out the logic results stored in the memristor as resistance state. During the write and read process, “1/2 bias” scheme is adopted to operate the array and prevent unintended switching. For the device under operation, selected word line (WL) voltage is pulled up to Vdd or VREAD and selected bit line (BL) grounded or vice versa. The voltages on unaddressed devices are either V/2 or 0 V. Here the Vdd is a write voltage larger than the value of SET and RESET threshold voltages, and VREAD is a small voltage that can not disturb the resistance state of the memristor. Firstly, an initialization step representing the first physical variable W is executed to set memristor into an initial state. As shown in Figure 4a, W=1 is defined as WL pulled up to Vdd and BL grounded to ensure the memristor in LRS, while W=0 is defined as WL grounded and BL pulled up to Vdd to ensure the memristor in HRS. The initialization is followed by a writing operation step, as shown in Figure 4b, during which the rest three logic variables (A, B, and C) are assigned simultaneously. Especially, two logic input A and B are represented by the voltage potential of WL and BL. High potential Vdd represents logical 1 and zero potential (grounded) represents logical 0. The last variable C is a control signal to determine the applied path of A and B. When C=1, A is applied to WL and B to BL, whereas when C=0, A is applied to BL and B to WL, respectively. The variable C signal could be obtained using MOSFET, gating switch, decoder or other components in the peripheral circuit. Compared to the methods of refs. 24-26, assigning three logic variables (A, B, and C) simultaneously will save one logic operation step.


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The variable C can be realized by a commonly shared peripheral control circuit, which will not significantly increase the complexity of a logic-in-memory chip with a large-scale crossbar array. As mentioned above, a W=1 signal will ensure the memristor in a LRS. In this case, the device can switch to HRS under two conditions: A=0, B=1, C=1 or A=1, B=0, C=0, both of which means Vdd on BL and 0 V on WL. Similarly, in the case of W=0, the HRS device will switch to LRS only when A=1, B=0, C=1 or A=0, B=1, C=0. For definition, the LRS of a device represents a logical ‘1’ and HRS a logical ‘0’ for logic output. Hence, the relationship between the logic output L and four input variables can be defined by the equation below:

L = W ⋅ ( A ⋅ B ⋅ C + A ⋅ B ⋅ C) + W ⋅ ( A ⋅ B ⋅ C + A ⋅ B ⋅ C) = ( A + B ) ⋅ C ⋅ W + ( A + B) ⋅ C ⋅ W + A ⋅ B ⋅ C ⋅ W + A ⋅ B ⋅ C ⋅ W

Through above two steps, arbitrary 16 Boolean logic function can be achieved. The logic results can be in-situ stored in the operating memristor and read out by a VREAD bias as shown in Figure 4c. Note that the nonvolatile stored result can be regarded as an ‘initial’ state to participate in the next logic computing cycle. The assignment for the four logic variables are summarized in Figure 4d. Table 1 listed the algebraically Boolean expressions for the 16 functions of two input variables p and q, with corresponding names. In previous studies, W is preferred to set as a constant (0 or 1) for each logic function.23-26,28,29 However, since W is considered as a variable and the logic result could be used as the initial state of next logic operation cycle, we assigned p or q to W for certain logic functions, for instance, W = q for OR function.


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Figure 4. Schematic logic computing principle using one memristor in crossbar architecture. (a) Step 1: initialization. In this step variable W is determined. (b)Step 2: writing operation by input the other three variables: A, B, and C. (c) Step 3: read out the logic computing results by a small read voltage. (d) The logic variable assignment table for the four logic input. Table 1. Boolean expressions for 16 binary functions Boolean Functions 0 1 p

W

A

B

C

Name

Description

0 1 q

p p 1

p p 0

q q p

Null Identity Transfer

Binary constant 0 Binary constant 1 p


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q p q p⋅q

p+q p+q p⋅q p+q p+q p⋅q p⋅q p⋅q + p⋅q p⋅q + p⋅q

p q p

0 1 q 0 1 1 0 0 0 1

1 0 0 p 0 0 p p p p p p p

0 1 1 0 p p 1 q q q q q q

q p q q q 0 q 0 1 0 1 p q

Transfer Complement Complement AND NAND OR NOR Implication Implication Inhibition Inhibition Exclusive-OR Equivalence

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q Not p Not q p and q Not-AND p or q Not-OR If p , then q If q , then p q but not p p but not q p or q , but not both p equals q

NAND is a universal functionally complete logic extensively used in the design of digital systems. Here we experimentally demonstrate its implementation in the Ag/AgGeTe/Ta memristive crossbar array to verify our methodology (Figure 5). For this specific function, variables (W, A, B, and C) are assigned (1, 0, p and q), respectively. The pulse width of operating signals is fixed at 500 ns to ensure stable switching behaviors, and Vdd is designated 3.4 V to match the working voltage in IC chips. Figure 5a – 5c shows the variable assignment for NAND logic in three steps. In the initialization step, W = 1, which means the selected memristor is set to LRS by applying Vdd and 0 V to corresponding WL and BL, respectively. Then, in the writing operation step, When C = q = 0, A (always 0 V) and B (p) are assigned to BL and WL, respectively; When C = q = 1, the direction of A and B is reversed, i.e. A is applied to WL and B is applied BL. Finally, a read voltage (50 mV in this work) in the third step is used to read out the nonvolatile resistance state as the logic output. Figure 5d-f show the experiment results of NAND for all four possible combinations of p and q. In case B = p = 0, hence the voltage bias on memristor is always 0 V, and the memristor maintains at LRS (logic 1) without resistive


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switching phenomena in the logic operation step (Figure 5d and 5f). In case B = p = 1, a Vdd bias is obtained while C = q = 0, and the memristor also stays at LRS (logic 1), as shown in Figure 5e. Only if B = p = 1 and C = q = 1, the memristor would switch to HRS (logic 0) due to a -Vdd bias, as shown in Figure 5g. (Experimental results for the other 15 Boolean logic functions can be found in Figure S2 to Figure S16 in supporting information.)


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Figure 5. Implementation of NAND function with a Ag/AgGeTe/Ta memristor in the crossbar array. (a-c) The variable assignment in the two logic operation steps and one readout step for NAND logic. (d-g) Experiment results for the four possible input-output combination of NAND


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logic. The red and blue curves display the applied potential in the initialization and writing steps, respectively. The green dotted lines are the device resistance representing the logic output.

We have demonstrated theoretically and experimentally the feasibility of nonvolatile logic computing using one memristor in crossbar structure. To implement functionally complete logic in one device, the assignment of (W, A, B, and C) variables is not unique and we try to simplify it in our work. As you can see in Table 1, variable assignment with minimum different ones is intentionally designed for inverse (such as “p inhibit q” and “p IMP q”) and reverse (such as “p inhibit q” and “q inhibit p”, “p IMP q” and “q IMP p”) logic functions. Especially, although in conventional method, a reverse logic (IMP, p +q ) could be realized by exchanging p and q of its counterpart (RIMP, p + q ), here we assign p and q to the same variable position that only the finally C variable varies, i.e. 0 and 1 for IMP and RIMP, respectively. For logic “Null” and “Identity”, the logic results are always “0” or “1” regardless of arbitrary logic input. However, these two functions have not been properly implemented. In some previous work, zero setting method is adopted to realize the Null function. In some other work,

p and q were directly utilized as the logic input25, 28-29, but theoretically they are also unknown variables which need to be calculated with additional logic cycles. In our work, the initialization cycle is the key to implement “Null” and “Identity” functions. Specifically, since A, B, and C are assigned p, p, and q, respectively, the voltage drop across the device is always zero resulting in an unchanged resistance state.


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Although filamentary or interface-induced resistive switching behaviors have been observed in various material systems50-53, the performance criteria for logic device could be different with memory application. For this nonvolatile memory-enabled emerging logic application, several device performances could be more crucial, such as switching speed, power consumption, endurance and uniformity. Sub-ns and sub-pJ/bit switching could help to compete with chargebased CMOS logic in certain area, such as reconfigurable logic computing. High uniformity of set/reset voltage and resistance distribution from cycle-to-cycle and device-to-device would be beneficial to reduce the logic error rate. Repeatable switching cycles may be several orders of magnitude larger than that in memory application. Moreover, the sneak current can not be neglected in the large-scale integration. Devices with high I-V nonlinearity are preferred. Logic method should also be further optimized based on those structures with the ability to resist crosstalk in array, such as complementary RRAM, self-rectifying devices, one-transistor-oneresistor, and one-selector-on-resistor structures. CONCLUSION In summary, we showed the ability of silver dopant to enhance the thermal stability of germanium telluride serving as the electrolyte layer in metallic filamentary-type memristor. Functional devices were demonstrated, showing

Realization of Functional Complete Stateful Boolean Logic in

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