Room-Temperature Quantum Ballistic Transport in Monolithic

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Room Temperature Quantum Ballistic Transport in Monolithic Ultrascaled Al-Ge-Al Nanowire Heterostructures Masiar Sistani, Philipp Staudinger, Johannes Greil, Martin Holzbauer, Hermann Detz, Emmerich Bertagnolli, and Alois Lugstein Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.7b00425 • Publication Date (Web): 22 Jul 2017 Downloaded from http://pubs.acs.org on July 23, 2017

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Room Temperature Quantum Ballistic Transport in Monolithic Ultrascaled Al-Ge-Al Nanowire Heterostructures M. Sistani1, P. Staudinger1, J. Greil1, M. Holzbauer2, H. Detz3, E. Bertagnolli1, A. Lugstein1 1

Institute for Solid State Electronics, Technische Universität Wien, Floragasse 7, 1040 Vienna, Austria

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Center for Micro- and Nanostructures, Technische Universität Wien, Floragasse 7, 1040 Vienna, Austria

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Austrian Academy of Sciences, Dr. Ignaz Seipel-Platz 2, 1010 Vienna, Austria

KEYWORDS: Ballistic transport, germanium, nanowire, heterostructure, aluminum

ABSTRACT: Conductance quantization at room temperature is a key requirement to utilize ballistic transport for e.g. high performance, low power dissipating transistors operating at the upper limit of ON-state conductance or multi-valued logic gates. So far, studying conductance quantization has been restricted to high mobility materials at ultralow temperatures and requires sophisticated nanostructure formation techniques and precise lithography for contact formation. Utilizing a thermally induced exchange reaction between single-crystalline Ge nanowires (NW) and Al pads, we achieved monolithic Al-Ge-Al NW heterostructures with ultrasmall Ge segments contacted by self-aligned quasi one-dimensional crystalline Al (c-Al) leads. By integration in electrostatically modulated back-gated field-effect transistors (FETs), we

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demonstrate the first experimental observation of room temperature quantum ballistic transport in Ge, favorable for integration in CMOS platform technology.

After decades, following Moore’s law1 by continuously shrinking feature sizes of classical planar metal-oxide-semiconductor FETs, physical limitations and the dramatic repercussions of short channel effects2 have forced a shift of research efforts towards the integration of new materials, novel processing techniques and ultrascaled device architectures.3 Owing to miniaturization in engineering systems, as well as an increasing interest in fundamental research in accompanying quantum confinement effects and ballistic transport, quasi one-dimensional nanostructures, such as semiconductor NWs gain particular interest.4,5,6 As the minimum feature size approach the bulk electron mean free path, novel physics due to the confinement of electrons and phonons may pave the way for future high performance, nanoelectronic devices.7,8 Although, room temperature ballistic transport was demonstrated in constricted two-dimensional electron gases of high mobility materials,9,10,11 forming quantum point contacts, ballistic transport in NWs was restricted to high magnetic fields (>4 T) and/or ultralow temperatures.12 Motivated by the relevance of ballistic transport for multi-valued logic gates,13 quantum computing,14,15 and recently the realization of topological superconductivity or Majorana fermions,16,17,18,19 ballistic transport observed in Si/Ge core-shell NWs7,20,21 triggered further research activities on group IV NWs favorable for CMOS process integration. Particularly Ge NWs represent a unique quasi 1D system for exploring quantum coherence phenomena because of the high hole mobility22 and an exciton Bohr radius of aGe = 24.3 nm,23 approximately five times larger than that of Si (aSi = 4.9 nm), leveraging strong quantum confinement effects.24 In addition, as compared with III-V materials where hyperfine coupling limits the electron spin coherence, the prospect of long coherence times in group IV semiconductors with spin-zero nuclei has stimulated a lot of


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experimental effort also for spin-based quantum information applications.25 Despite the above mentioned beneficial properties of Ge to study quantum confinement effects,26 ballistic transport was not observed for temperatures above T = 2 K27 also attributed to precise nanopatterning and contact formation issues. Further, in these quasi 1D structures surface states create inhomogeneities in the local electrostatic environment increasing the probability of electron reflections and backscattering.12 In this letter, we demonstrate for the first time room temperature quantum ballistic transport in ultrascaled Ge NWs with diameters comparable to the Bohr radius of Ge of aGe = 24.3 nm. Therefore monolithic Al-Ge-Al NW heterostructures with ultrashort Ge segments are integrated in a back-gated FET architecture (figure 1a) accomplished by a novel heterostructure formation process via a thermally controlled exchange reaction between the single-crystalline Ge NWs and Al contact pads.28 As shown in the SEM image in figure 1a, applying this fabrication technique enables an axial metal-semiconductor-metal arrangement, featuring an ultrashort Ge segment connected by quasi one-dimensional c-Al leads with abrupt metal-semiconductor interfaces (see TEM image in the inset).


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Figure 1. (a) Schematic illustration of the Al-Ge-Al NW heterostructure with self-aligned c-Al leads integrated in a back-gated FET device. The SEM image shows an Al-Ge-Al NW heterostructure with a Ge segment length of LGe = 30 nm. A magnified view showing the abrupt metal-semiconductor interface between the quasi one-dimensional c-Al leads and the Ge segment is provided by the TEM image in the inset. (b) Comparison of the transfer characteristics of Al2O3 passivated and unpassivated Al-Ge-Al NW heterostructures integrated in the FET with respective hysteresis effects. The data were recorded for back gated FET devices with Ge segment lengths of LGe = 150 nm in the gate-voltage range between VG = -15 V and VG = +15 V for a bias of VD = 10 mV at T = 300 K. The left inset shows the time dependence of the drain current ID for the passivated Al-Ge-Al NW heterostructure device (LGe = 150 nm) for VG = -15 V and a bias of VD = 10 mV at T = 300 K. A comparison of the I/V characteristic for a passivated (red) and an unpassivated (black) device with a channel length of LGe = 77 nm at VG = 0 V is provided in the right inset. To exclude the influence of adsorbates on the NW surface, all measurements were performed in vacuum.


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To achieve ultrashort Ge segments, vapor-liquid-solid (VLS) grown Ge NWs with diameters of around 25 nm occasionally coated with 20 nm high-k Al2O3 by atomic layer deposition are drop casted onto an oxidized highly p-doped Si substrate. For the subsequent exchange reaction and self-aligned contact formation, Al pads are fabricated by electron beam lithography, sputter deposition and lift-off techniques. Thus, the device resembles a fully featured back-gated FET, whereby the actual Ge channel length (LGe) can be controlled by a successive thermally induced exchange reaction between the single-crystalline Ge NWs and the Al contact pads by rapid thermal annealing at a temperature of T = 623 K in forming gas atmosphere. Details of the exchange reaction, TEM and compositional analysis by high resolution EDX investigations revealing the perfect crystallinity and purity of the remaining Ge segments connected to single crystalline Al leads were already given in a previous letter.28 In contrast to common short channel devices, utilizing this unique device architecture effectively prevents screening of the gate electric field by extended source/drain contacts.29 The transfer characteristics in figure 1b for a device with a bare Ge NW segment and one covered by Al2O3 demonstrate the necessity of the high-k passivation layer to achieve reliable and reproducible electrical performance of the device. Although intrinsic VLS grown Ge NWs were used, negative surface charges accumulating in interband trap levels30 lead to an overall ptype behavior of the back-gated FET device for both, the bare as well as the Al2O3 covered NWs. As adsorbates influence the electrical behavior of Ge NW based devices,31,32 in order to reduce interface traps and surface disorder33,34 and thus ultimately gain the ability to observe ballistic transport at room temperature, it was mandatory to passivate the Ge NWs prior to the heterostructure formation.


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In agreement with previous reports,35,36 using a high-k passivation layer results in less pronounced hysteresis effects. In addition, the ON-current and the ION/IOFF ratio of the passivated FET increases by more than two orders of magnitude. However, even the passivated device shows a small hysteresis due to kinetic effects mostly related to charge carrier trapping at the interface and the devices exhibit transient behavior as shown in the left inset of figure 1b. For a negative gate voltage of VG = -15 V the accumulation of holes continuously neutralizes trapped electrons, resulting in an exponential decay of the drain current over time.30 In accordance with Zhang et al. 37 we assume that during the annealing in forming gas a thin GeOx layer is formed at the interface between the Ge NW and the Al2O3 passivation. Dedicated to a multiexponential time-dependence, indicating a significant spread in the spatial and energetic distribution of the surface trap states, as well as kinetic limitation by either a diffusion barrier or a tunnel barrier at the NW surface, charging and discharging of trapped surface states are relatively slow processes.30 Therefore, for the actual device geometry and under the given experimental conditions, steady-state is achieved after a time span of approximately one hour, which has to be taken into account to achieve reliable ballistic transport measurements. Further, as shown in the right inset, a combination of conformal high-k passivation and controlling the trap population allows to effectively tune the electronic transport characteristic of the back-gated Ge NW device. Whereas the devices with uncoated Al-Ge-Al NW heterostructures provoke a distinct non-linear I/V characteristic, the ohmic behavior and higher conductivity for the passivated devices after trap depletion indicates improved contact properties enabling effective carrier injection (see supporting information).


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Two terminal I/V measurements of passivated Al-Ge-Al NW heterostructure devices with different Ge segment lengths shown in figure 2a revealed a clear transition from a non-linear behavior to an almost linear characteristic for devices with channel lengths below LGe = 45 nm.

Figure 2. (a) I/Vs of passivated Al-Ge-Al NW heterostructures with different Ge segment lengths integrated in back gated FET devices for VG = 0 V at ambient conditions and (b) thereof calculated resistance as a function of Ge segment length normalized with respect to the crosssection of the NWs. The enlarged view depicts the resistance of the heterostructure devices with Ge segment lengths smaller than LGe = 100 nm. Essentially, one may assume that devices with Ge segment lengths LGe > 45 nm operate as backgated Schottky barrier FETs, with ID ∝ exp(eV/kT) due to two back-to-back Schottky contacts, which is commonly addressed to explain nonlinear I/V curves of semiconductor NW devices.38 Figure 2b shows further that the thereof calculated overall resistance of longer devices is direct proportional to the Ge segment length in accordance with ohm´s law. In contrast, heterostructure devices with Ge segment length below LGe = 45 nm reveal a linear I/V characteristic, with the resistance being independent of the Ge segment length. Assuming a square-well confining potential as well as periodic boundary conditions for a Ge NW with a diameter of 25 nm the


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current from the continuous bands in the contact leads is redistributed to a maximum of four conductance channels inside the Ge NW (see supporting information).39,40 According to figure 2b, we assume that under the given experimental conditions (VG = 0 V), we can only access one conductance channel. Thus, figure 2b illustrates actually the modification of the transmission coefficient as a function of the channel length for the first conductance channel. This is supported by the enlarged view in the inset of figure 2b, which shows that the resistance of AlGe-Al NW heterostructures with ultrascaled Ge channels is approaching the fundamental contact resistance of RC = 12.9 kΩ, which is a first indication of ballistic transport.39 For thin Ge NWs with diameters of about 25 nm and thus close to aGe, quantum confinement results in a band structure being composed of multiple 1D subbands. According to the schematic shown in figure 3a with the NW axis being oriented along the z-direction, due to the quantum confinement in the y-z direction, the respective dispersion relation E(k) for holes of such a quantum wire, provokes the corresponding quantization of conductance,42,43 with each 1D subband contributing a quantum unit of conductance of G0 = 2e2/h.41


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Figure 3. (a) Schematic illustration of the 1D dispersion relation E(k) and the corresponding density of states D(E) of an Al-Ge-Al NW heterostructure with thin Ge NWs. The Fermi level as well as the expected G-VG characteristic for NWs with filled and depleted surface traps are sketched. (b) Time dependent G-VG behavior for Al-Ge-Al NW heterostructure devices with Ge segment lengths of LGe = 15nm (blue), 45 nm (green) and 150 nm (red) at ambient conditions. The upper left inset shows the G-VG characteristics recorded for different trap filling levels of an Al-Ge-Al NW heterostructure device with a 15 nm long Ge segment for VG = -15 V. Fast G-VG measurements were performed after the time intervals given in the inset. The upper right inset shows the experimental G-VG behavior of Al-Ge-Al NW heterostructures with varying Ge segment lengths with depleted traps. All measurement data were recorded for a bias of VD = 1 mV at T = 300 K in vaccum. The conductance was directly obtained from the measured current G = ID/VD. The lower inset schematically depicts the discharging of traps due to an accumulation of holes at negative VG. Figure 3b shows the transient behavior of the measured conductance of three Al-Ge-Al NW heterostructure devices with Ge channel lengths of LGe = 15 nm, 45 nm and 150 nm at VG = -15 V and a bias of VD = 1 mV in quantum units of conductance G0. For the 15 nm long Ge segment and thus expected ballistic transport, an initial conductance of 2.5G0 indicates that the current from the continuous bands of the microscopic Al leads is redistributed to the first two subbands. The corresponding Fermi level and G-VG characteristic is schematically depicted by the green line in the schematic of figure 3a. However, keeping the gate voltage constant at VG = -15 V, the traps are getting discharged resulting in less effective gating (lower inset of figure 3b). Finally, after approximately 80 min of trap depletion, the Fermi level adjusts close to the edge of the first subband (blue line of figure 3a). In contrast, applying a positive gate-voltage


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of VG = 15 V provokes filling of empty traps below the Fermi energy, resulting in a more negative “effective” gate. This process continues until equilibrium is reached, having a higher number of trap states filled, which results in a Fermi level slightly below the edge of the third subband (red line of figure 3a). Thus, to support the proposed model, the upper left inset of figure 3b shows the transfer characteristic for the ultrascaled (LGe = 15 nm) device for different trap filling levels. Initially, without any depletion or filling of the traps, sweeping VG from zero to -15 V, two distinct steplike features are observed at 1 and 2 G0, which are due to quantization of the density of states, with each step attributed to the population of a single spin-degenerated 1D subband. As already discussed above, attributed to the almost insignificant contact resistances, the injection barriers appeared to be negligible,41 indicating effective carrier injection with hole tunneling at the abrupt Al-Ge interface. However, G-VG measurements conducted for different trap depletion times between 15 min and 60 min show that due to gradually trap depletion, the Fermi level moves upwards and thus finally only the first subband contributes to ballistic current transport, which is indicated by a step-like feature at G0. Further, operating the device with filled traps due to effective gating, the Fermi level lowers and populates the first three subbands, which is supported by distinct step-like features in the G-VG characteristic at integer multiples of G0. Hence, by investigating the transient behavior of trap neutralization/filling on the electronic transport of ultrascaled Al-Ge-Al NW heterostructures, we demonstrate that although the Fermi level shifts in respect to the trap filling level, conductance quantization persists. With increasing channel length, carrier scattering and for NWs particularly surface roughness scattering will influence charge transport and finally when exceeding the mean free path, carrier


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transport will become diffusive. Hence, for the device with LGe = 45 nm in the steady state the conductance level is in the order of 0.25G0, however, close to the ballistic limit. For the device with the channel length of 150 nm, exceeding the mean free path in Ge, the conductance level is only 0.1G0. For even longer devices in the steady state the diffusive transport leads to the observed linear dependency of the resistance on the channel length. The upper right inset in figure 3b depicts a compilation of steady state G-VG measurements at T = 300 K of Al-Ge-Al NW heterostructure devices with Ge segment lengths between LGe = 15 nm and 45 nm. However, with increasing channel lengths, the plateau is shifted to lower conductance values corresponding to an added series resistance and thus a decrease of ballistic traversing charge carriers due to increased scattering. Investigations on numerous devices revealed that for devices with Ge segment lengths above LGe = 45 nm all signs of conductance quantization at room temperature vanish. Finally, we focus on the investigation of the temperature dependency of the ultrascaled Al-Ge-Al NW heterostructure devices. Figure 4a depicts the G-VG behavior of a device with a physical channel length of LGe = 15 nm measured in the temperature range between T = 5 K and 300 K.


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Figure 4. (a) G-VG plot for an Al-Ge-Al NW heterostructure device with a Ge segment length of LGe = 15 nm for temperatures between T = 5 K and 300 K. The inset shows the G-VG behavior shifted in VG for presentation clarity. The conductance was directly obtained from the measured current according to G = ID/VD. (b) Bias spectroscopy dID/dVD of the 1D subband structure at T = 70 K. The differential conductance dID/dVD was directly obtained from I/V measurements at different gate-voltages and is plotted in units of G0.

Distinct plateau like features can be observed over the entire temperature range and neither the overall conductance nor the steepness of the conduction plateaus change with increasing temperature. For the long channel devices, drift current due to the applied electric field dominates the charge carrier transport and in accordance with the work of Jones et al.,42 we observed a distinct decrease of conductivity due to a freeze out of charge carriers below T = 25 K. The lack of such temperature dependence for the ultrascaled devices is thus a further proof of ballistic transport. In addition to the plateau at G0, the ultrascaled Al-Ge-Al NW heterostructure device with a Ge segment length of LGe = 15 nm, exhibit several resonances below G0. A plateau like feature at approximately 0.85G0, that could clearly be observed for temperatures up to T = 200 K and is assumed to be a result of spin effects but so far there is no generally accepted explanation for the origin of this conductance feature.43 Further plateau-like features observed at T = 5 K fading away for higher temperatures can be classified in intrinsic and extrinsic mechanisms.39,43,44,45 The origins of these conductance anomalies are assumed to be dedicated to tunneling resonances,46 single-electron charging effects47 or geometric transmission resonances48 arising from impurities.


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Figure 4b shows the bias spectroscopy at T = 70 K (figure 4b) where the device was cooled down without prior trap neutralization. Based on I/Vs measured for different VG, the depicted curves correspond to dID/dVD versus VD. In the low bias region (linear regime), due to overlapping of measurements at different VG, dense regions appear at integer multiples of G0, which is consistent with quantized conductance plateaus for individual spin degenerate 1D subbands, where the influence of the gate-voltage on dID/dVD is insignificant.20 With increasing bias voltage we observed the evolution of conductance from integers multiples of G0 to intermediate values at higher bias voltages (+/- 10 mV). As reported previously in QPCs49 and 1D quantum wires,20 such half plateaus appearing at intermediate values of G0 at higher bias voltages arise when the chemical potentials of source and drain occupy different subbands.50 Further, the bias spectroscopy clearly revealed a conductance anomaly at 0.7G0, which is considered to be an intrinsic low temperature sub-G0 feature of mesoscopic devices that is assumed to originate from many-body physics and was the first conduction anomaly that turned out to be independent of the material system. 44,45,51 In conclusion, utilizing a controlled thermal exchange reaction between single-crystalline VLS grown Ge NWs and Al pads, we demonstrated room temperature quantum ballistic transport in back-gated Al-Ge-Al NW heterostructure devices with ultrascaled Ge segments. In addition, we have shown that the number of populated subbands can be modulated with respect to the trap filling level. Most importantly, the investigations provide a platform for the exploration of ultrascaled devices based on Ge NWs and thus are an important step towards practical applications of ballistic transport at room temperature.


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ASSOCIATED CONTENT Supporting Information

Further information supporting the discussion of injection barriers for passivated and unpassivated Al-Ge-Al NW heterostructures is provided.

AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] Author Contributions The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. Notes The authors declare no competing financial interest. ACKNOWLEDGMENT The authors gratefully acknowledge financial support by the Austrian Science Fund (FWF): project No.: P28175-N27, P29729-N27 and P26100-N27. The authors further thank the Center for Micro- and Nanostructures for providing the cleanroom facilities as well as M. StögerPollach from USTEM TU Wien for conducting the TEM investigations.


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Page 20 of 25

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Page 23 of 25

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Page 24 of 25

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Room-Temperature Quantum Ballistic Transport in Monolithic

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