Silicon Nanosheets: Crossover between Multilayer Silicene and

Mar 6, 2017 - D.A. acknowledges the TI/Jack Kilby Faculty Fellowship and the Presidential Early Career Awards for Scientists and Engineers (PECASE) Aw...
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Silicon Nanosheets: Crossover between Multilayer Silicene and Diamond-like Growth Regime Carlo Grazianetti,† Eugenio Cinquanta,†,⊥ Li Tao,‡ Paola De Padova,§,∥ Claudio Quaresima,§ Carlo Ottaviani,§ Deji Akinwande,*,‡ and Alessandro Molle*,† †

Laboratorio MDM, IMM-CNR, via C. Olivetti 2, Agrate Brianza I-20864, Italy Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758, United States § ISM-CNR, via Fosso del Cavaliere 100, Roma I-00133, Italy ‡

S Supporting Information *

ABSTRACT: The structural and electronic properties of nanoscale Si epitaxially grown on Ag(111) can be tuned from a multilayer silicene phase, where the constitutive layers incorporate a mixed sp2/sp3 bonding, to other ordinary Si phases, such as amorphous and diamond-like Si. Based on comparative scanning tunneling microscopy and Raman spectroscopy investigations, a key role in determining the nanoscale Si phase is played by the growth temperature of the epitaxial deposition on Ag(111) substrate and the presence or absence of a single-layer silicene as a seed for the successive growth. Furthermore, when integrated into a field-effect transistor device, multilayer silicene exhibits a characteristic ambipolar charge carrier transport behavior that makes it strikingly different from other conventional Si channels and suggestive of a Dirac-like character of the electronic bands of the crystal. These findings spotlight the interest in multilayer silicene as a different nanoscale Si phase for advanced nanotechnology applications such as ultrascaled nanoelectronics and nanomembranes, as well as for fundamental exploration of quantum properties. KEYWORDS: multilayer silicene, STM, Raman, transistor, ambipolar carrier transport

A

epitaxial growth regime of single-layer silicene, from other Si nanoscale films with a more trivial crystalline phase (e.g., amorphous or diamond-like ones), thus allowing for the manipulation of conventional and unconventional Si phases at the nanoscale. Single-layer silicene is a buckled sp2/sp3 metastable lattice of Si, which can be obtained by deposition of Si atoms on different stabilizing substrates8 and can be used as a pathfinder for functionalized compounds such as the half-silicane10 and the multilayer phase of silicene.11 Indeed, one may argue whether the pile-up of single layers of silicene can lead to the realization of a graphite-like allotropic form of Si, thus paving the way to a radical exploitation of Si nanosheets in applications and in searching for fundamental physical properties. In this respect, here we show that the electrical response of a FET device based on a carefully isolated multilayer silicene channel is strikingly

lthough Si is still ubiquitously used in nanotechnology, nanoscale reduction of Si-made active elements pose severe concerns for its future role in ultrascaled devices. In particular, scaling the dimensions of field-effect transistors (FETs) should meet the requirement of defect-free and highly crystalline Si at the nanoscale. Nonconventional allotropic forms of Si can be an alternative option to keep up with the current technology mainstream,1−3 and among them, silicene, the Si-based graphene counterpart, can be a promising option enabling the use of dimensionally reduced Si in the next technological nodes of solid-state nanoelectronics as well as in flexible and wearable electronics where Si can serve as a responsive or adaptive nanomembrane.4,5 In addition to these technology drivers, the dimensional reduction of Si defines a playground to study unexplored quantum properties such as the realization of a Dirac solid in Si.6 Since its original epitaxy on Ag(111),7 silicene has been successfully synthesized on substrates8 and integrated into a FET device.9 The silicene transistor platform now offers an unprecedented methodology to univocally discriminate the electrical response of multilayer silicene, herein referred to as the pile-up of Si layers in the © 2017 American Chemical Society

Received: February 3, 2017 Accepted: March 6, 2017 Published: March 6, 2017 3376

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Figure 1. (a) a-Si phase obtained in the low-GT regime. (b) Multilayer silicene synthesized in the intermediate-GT regime characterized by the √3 × √3 surface reconstruction. (c) Diamond-like Si phase grown in the high-GT regime. All 3D renderings are based on representative STM images (200 × 200 nm2) reported in Supporting Information. (d) Right STM image (29 × 50 nm2) shows the typical terrace-growth mode where the presence of seed single-layer silicene in a 3 ML thick sample is evidenced. Left inset shows a high-resolution STM topography of the √3 × √3 multilayer silicene surface structure along with the hard-spheres model, where the cyan (blue) spheres are the top (bottom) atoms. Only the top atoms are STM-recorded according to ref 43. The red rhombus defines the unit cell.

Figure 2. (a) First-order Raman spectra showing the characteristic mode for multilayer silicene (blue), diamond-like Si (red), and a-Si (green) samples compared to bulk Si(111) (dashed black line). (b) Second-order Raman spectra acquired with the 514 nm wavelength. Vertical dashed line is placed at the 2TO(L) frequency of 980 cm−1 for clarity.

a terrace-growth mode11,13,15 (see Supporting Information Figure S1). While the multilayer silicene exhibits a √3 × √3 surface termination, its inner bulky structure has so far been questioned as whether it shows up as a graphite-like phase or as a more trivial diamond-like one.13,15−18 In the former case, multilayer silicene should be regarded as silicite,19 in close analogy with graphite, where silicene layers are stacked up, forming a 3D structure. In the latter case, multilayer silicene is considered as another type of Si(111) surface arrangement, where the sp3 bulk is terminated with a √3 × √3 reconstruction, in constrast with the commonly observed 7 × 7, 5 × 5, or 2 × 1 ones,13,20,21 or eventually stabilized by Ag segregation from the substrate.16,17,22,23 To differentiate the phases in differently grown Si nanosheets, three GT regimes were investigated: low (T ∼ room temperature), intermediate (T = 200−230 °C), and high (T = 350 °C). Figure 1 displays the distinctive features of the three different configurations derived from the 3D-elaborated surface morphology of the in situ scanning tunneling microscopy (STM) analysis. The low-GT regime results in a disordered surface structure that is indicative of an amorphous Si (a-Si) layer (Figure 1a). In the intermediate-GT regime, a √3 × √3

hallmarked by the evidence of an ambipolar behavior that sharply differs from that measured in other Si nanosheet channels obtained in different growth temperature (GT) regimes. Our findings are solidly based on the identification of a nonconventional allotropic form of a nanoscale Si phase with a mixed sp2/sp3 hybridization (herein denoted as multilayer silicene, in agreement with the previously proposed terminology11) away from other more conventional nanoscale Si phases (amorphous and diamond-like) by taking advantage of the single-layer silicene as a seed for the successive overlayers and then narrowing the parametric range of growth, and they are supported by a comparative study of the electrical transport and the Raman spectrum in the differently grown Si nanosheets.

RESULTS AND DISCUSSION At variance with the multiphase character of the single-layer silicene on Ag(111),12 hitherto any layer epitaxially grown on top of the seeding single-layer silicene was shown to expose a unique √3 × √3 surface reconstruction.11,13,14 Interestingly, this √3 × √3 reconstruction, with respect to the freestanding silicene lattice,8 is displayed for each Si layer which piles up via 3377

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Figure 3. Schematic drawing of transistor fabrication for multilayer silicene-grown Ag(111)/mica substrate. After being delaminated from mica, the “silicene sandwich” is flipped and attached to the device-friendly SiO2/Si substrate. Red arrow indicates the seeding single-layer silicene. Source and drain electrodes are then patterned by lithography on a native Ag layer, thus completing the bottom-gate FET configuration. This process flow has a pictorial characterization related to the descriptive intent of the process and is not representative of an atomic structural model.

(FBZ).29 Whereas for conventional noncrystalline Si the red shift and the activation of out-of-Γ modes are due to quantum confinement and disorder, respectively,30,31 in the case of multilayer silicene, these models no longer hold. Indeed, on one hand, quantum confinement would lead to a red shift of the Raman mode as a function of the nanocrystallites size instead of the observed blue shift; on the other hand, disorder would cause a broad and asymmetric peak, which is not observed in our data.30,31 In analogy with single-layer silicene,25,26,32 we rationalize the observed discrepancies in terms of a shorter Si− Si bond length with respect to the one of bulk Si(111), being consistent with mixed sp2/sp3 bonds in multilayer silicene instead of purely sp3 ones.13 The resulting lower lattice symmetry with respect to both freestanding silicene and bulk Si is responsible for the presence of additional Raman-active modes (see Supporting Information Figure S4). The second-order Raman (SOR) spectra in Figure 2b shed light on the structural and vibrational properties of the samples. Multilayer silicene and diamond-like Si samples are characterized by a different overtone of the first-order Raman modes if compared with the bulk Si(111). This overtone is due to the superimposition of TO modes at different high-symmetry points (X, W, and L) in the FBZ.33 The most intense SOR mode in bulk Si(111) is the 2TO(L) at 980 cm−1 (namely, double the frequency of the TO(L) at 490 cm−1) with 514 nm excitation wavelength. Remarkably, the intensity of this overtone increases as a function of the GT resembling the peak profile of sp3 Si for diamond-like Si samples. The temperature behavior of the SOR intensity in Figure 2b and of the red shift in Figure 2a are mutually related by the transition from a sp2/sp3 hybrid state in the multilayer silicene to a sp3 state in the diamond-like Si. Finally, at variance with the singlelayer silicene case, the improved air stability of multilayer silicene allows one to perform ex situ characterization (e.g., Raman spectroscopy) without the need for an Al2O3 capping layer13 (see also Figure S10 in Supporting Information), thus multilayer silicene is an effective solution for the air instability of single-layer silicene.9,13,34 In this light, the bulk of our STM and Raman observations describes the multilayer silicene as a mixed sp2/sp3 hybrid phase where the sp2 coordination is induced by the seeding singlelayer silicene and is mostly extended in-plane. The latter fact is consistent with the recently reported X-ray diffraction evidence of the in-plane lattice parameter in multilayer silicene strikingly deviating from that of bulk-like tetragonal Si with various surface terminations.35 Given the peculiarity of the structure, it is then interesting to investigate the electrical response of the as-grown multilayer silicene when integrated as an active channel in a FET device structure.

surface structure is observed (Figure 1b and high-resolution images in Figure 1d), which denotes the formation of multilayer silicene,11 whereas 3D clustering is observed in the high-GT regime (Figure 1c), herein termed the diamond-like Si phase. The intermediate- and high-GT regimes differ in that the former one incorporates the single-layer silicene as initial coverage settled by the favorable GT (see Figure 1d, which shows the early stages of multilayer silicene growth), whereas the latter one is absent of the single-layer silicene because of temperature-induced dewetting even from the very early stage of growth.8,24,25 Therefore, among the GT regimes scrutinized here, the intermediate one refers to the thermal range where single-layer silicene grows and all the successive topmost layers exhibit the √3 × √3 recontruction. Hereafter, according to the recent literature, multilayer silicene will then refer to the intermediate-GT regime.11 The thickness of the multilayer silicene sample is 24 ML (1 ML is the single-layer silicene on the Ag(111) surface), while for amorphous and diamond-like Si, the equivalent nominal thickness of ∼7 nm has been considered. A deeper insight into the bulky structure of the three different Si nanosheets has been derived by a comparative Raman spectroscopy study enabling a clear-cut discrimination of the nanoscale Si phase as previously deduced for the singlelayer silicene.25,26 Figure 2a shows the Raman spectra of the nanoscale Si samples grown in the three different GT regimes compared to bulk Si(111). The low-GT sample features a broad Raman peak centered at 480 cm−1 consistent with amorphous Si,27 whereas both multilayer silicene and diamondlike Si exhibit a quite sharp Raman peak at 524 cm−1 (according to ref 13) and 521.5 cm−1, respectively. Hence, increasing the GT leads to a red shift in the Raman peak tending to that of bulk Si(111), which is placed at 520.4 cm−1. The same Raman mode is observed in a set of control group silicon-on-insulator commercial samples where the Si region has been reduced down to a thickness of ∼5 nm (see Supporting Information Figure S3), thus ruling out any growth or morphology-induced artifacts in the Raman spectrum detection of the Ag-supported nanoscale Si samples and herein confirming the Raman signature of the multilayer silicene in agreement with recent studies13,28 and with the model previously proposed for the single-layer silicene.25,26 Despite the discrepancy in the Raman mode position, both multilayer silicene and diamond-like Si show a weak but significant shoulder around 485 cm−1. This feature commonly appears in Si-based nano/micromaterials where the crystalline order is reduced and the Raman selection rules are relaxed, and as such, it can be attributed to overlapping the transverse-optical (TO) modes of Si at the L3 point (480 cm−1) and at the W point (490 cm−1) of the first Brillouin zone 3378

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Figure 4. (a) Low-field (Vd = 20 mV) Id versus Vg curve of diamond-like Si device. (b) Comparison between Id versus Vg of 10 ML (red) and 24 ML thick (blue) multilayer silicene FETs. (c) Resistance versus (Vg−VCNP) plot of multilayer silicene (24 ML) device showing the measured transfer characteristics (dots) in good agreement with a widely used ambipolar diffusive transport model37 (red line) and (d) for the 10 ML case.

Table 1. Electrical Measurement of Si Samples

a

sample

charge transport

resistance (Ω)

field-effect mobility (cm2/Vs)

residual carrier density (cm−2)

1 ML intermediate-Ta 10 ML intermediate-T 24 ML intermediate-T 24 ML high-T

ambipolar ambipolar ambipolar pseudolinear

0.2−2.7 × 106 1.5−3.3 × 105 1.5−2.0 × 104 1.0 × 107

∼100 49−63 66−200 N/A

∼8 × 109 ∼1 × 1012 ∼2 × 1012 N/A

Data from ref 9.

The integration of nanoscale Si films into a FET was carried out by means of an encapsulation-free delamination method similar to that used for the single-layer silicene9 (see Methods) and allowed us to probe the electrical transport features in the three different configurations. The process flow is schematically depicted in Figure 3 for the multilayer silicene case and includes the material synthesis as previously detailed9 onto a cleavable epi-Ag(111)/mica substrate, the delamination and handling of the multilayer silicene slice with native Ag, the slice transfer to a SiO2/p++Si platform, and the final realization of a bottom-gate FET with a Ag-free conductive multilayer silicene channel. The same processing has been performed for FET based on lowand high-GT Si nanosheets. It should be emphasized that the single-layer silicene seed is turned upside down in the transfer, therein serving as an effective environmental protection against oxidation of the underlying √3 × √3 layer. Figure 4a,b shows the low-field (Vd = 20 mV) transfer curve measured from the two different nanoscaled Si channels in Figure 1c,b, respectively. A striking difference emerges from the comparative response of the three FET devices. In particular, a-Si and diamond-like Si channels manifest a trivial current−voltage response, namely, open circuit (see Supporting Information Figure S9) and poor conductance (resistance up to 10 MΩ) with no gate modulation (Figure 4a), respectively. On the other hand, the multilayer silicene channel exhibits an ambipolar

behavior of the drain current Id at both sides of the branch bias Vg, distinguishing electron from hole conduction (blue curve in Figure 4b). This fashion is clearly apparent from the resistance plot in Figure 4c, where the peaked shape profile is interpreted as coming from a Dirac-like energy dispersion of the electronic bands in analogy with single-layer silicene9 or multilayer graphene.36 The charge neutrality point (CNP), where a minimum of conductance occurs, ranges between 6 and 8 V with an IOn/IOff ratio up to 1.5×. Fitting the resistance plot with the ambipolar diffusive model conventionally used with graphene FETs37 results in field-effect mobilities between 66 and 200 cm2 V−1 s−1 at room temperature with a residual carrier density (n0) at the CNP of ∼2 × 1012 cm−2. This electronic behavior definitely distinguishes the electrical response of multilayer silicene from that of a-Si and diamondlike Si in the form of nanoscale films. As such, the transport characteristics in the measured devices turn out to be likely driven by the presence or absence of the single-layer silicene seed. A similar ambipolar behavior has also been observed by thinning the multilayer silicene channel down to 10 ML. In a 10 ML thick sample, the CNP is around 3.5 V with an IOn/IOff ratio up to 2.2×, and silicene field-effect mobilities are extracted around ∼56 cm2 V−1 s−1 with n0 of ∼1.1 × 1012 cm−2 (red curve in Figure 4b,d). The main features of Si-based FETs are summarized in Table 1. 3379

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operation is subjected by the morphological nonuniformities) and prove to be stable up to 2 days (see Supporting Information Figure S7), thus boosting the limited stability of single-layer silicene FETs.9 Further potential improvement of transitor stability could be likely achieved by protecting the transistor channel also from the top side. In this light, the realization of a relatively stable multilayer silicene FET can pave the way to a more viable exploitation of dimensionally reduced Si for the quite ubiquitous Si-based applications in nanoelectronics, telecommunications, thermoelectrics, and flexible electronics.5 At additional variance with the single-layer case, for FET fabrication, multilayer silicene and diamond-like Si were not capped with Al2O3.9,34 This procedure exposes the very topmost √3 × √3 layer to oxidation in air, thus preserving the rest of the layers from any chemical degradation (see Supporting Information Figure S10). Hence, the electrical transport of multilayer silicene films may hardly descend either from the last √3 × √3 surface termination layer, which acts as a self-passivation barrier,13 or from the first single-layer silicene seed, which is exposed to air after delamination (see red arrow in Figure 3), but it most likely results from a percolative pathway through the layers that form a continuous channel between the source and drain contacts.

If we compare the multilayer silicene channel performance with that of single-layer silicene, we conclude that the former one shows higher values of the mobility and residual carrier density, but a lower IOn/IOff ratio. The varied IOn/IOff ratio (over 10× for single-layer silicene, ∼1.5× for multilayer silicene) indicates a tunable band gap with the number of layers, pointing to a semimetallic behavior in the multilayer silicene case. These differences intriguingly suggest the possibility to tune the 2D Si electronic properties either by varying the substrate temperature or by controlling the number of Si layers. Nonetheless, we realized that multilayer silicene FETs show performance degradation with thickness below 10 ML (opencircuit response is measured in 3 and 5 ML thick devices). It should be remarked that, below this threshold, the electrical transport is detrimentally affected by the morphological nonuniformities of multilayer silicene (inherent with the terrace-growth mode). Stratification of silicene layers above 10 ML is necessary to create a percolative path for charge carriers to travel through a continuous conducting channel and then yield a gate-modulated FET response, according to our limited experimental survey. Finally, the possible contribution of thin Ag residue to the electrical transport is undoubtedly ruled out by the control group devices (see Supporting Information Figure S8). A prior consideration on the FET response is that the ambipolar behavior appears to be a characteristic feature of the residing semimetallic nature of multilayer silicene. This fact is supported by the comparative study reported in Figures 1, 2, and 4. In addition, we notice that transistors incorporating extrinisically doped nanoscale Si channels, including ultrathin Si ribbons FETs with channel thickness down to below ∼100 nm38 as well as Si nanowire FETs,39 usually exhibit a unipolar character. This suggests a negligible extrinisic doping in multilayer silicene, whereas integrated Si nanowire FETs conversely need slight doping for an asymmetric ambipolar response to show up.40,41 Based on several previous results of linearly dispersed Dirac bands in the multilayer silicene,18,42 one may speculate that, to a first approximation, the ambipolar transport can be associated with the Dirac-like behavior of the √3 × √3 reconstructed Si(111) phase, as recently proposed in the literature.20 Nevertheless, the higher values of drain current sustained in thicker multilayer silicene suggests that the overall ambipolar transport is also affected by bulk-related effects, as shown by comparison between Id of 24 and 10 ML in Figure 4b, where a positive shift of the CNP can likely result from a (p-)doping effect (deduced from n0 values) that can be eventually related to a modified bulk Si structure. From this point of view, more specifically, the ambipolar character can be related to the inplane residual sp2 component of the mixed hybridization that is taking place in each individual plane of the crystal structure, which is likely to retain the covalent nature of the Si bonds. It is possible to speculate that the prevailing sp 2 and sp 3 components of the Si−Si bonds are mostly developed inplane and out-of-plane, respectively. This picture is corroborated by the STM observation of the √3 × √3 termination of each stacked exposed layer, by the characteristic Raman blue shift and by the recently reported in-plane lattice deviation of multilayer silicene with respect to diamond-like Si or Agterminated Si.35 Furthemore, multilayer silicene devices with an ambipolar response have been reproduced on several independently grown samples (more than 20 devices per sample whose

CONCLUSIONS In summary, we demonstrated that tailoring the Si epitaxy on Ag(111) enables us to vary allotropic forms in nanoscaled Si films ranging from a-Si to multilayer silicene and to diamondlike Si. Consistent with recent theoretical prediction,19 the multilayer silicene structure is identified by a growth regime where the seeding single-layer silicene acts as precursor or template for the √3 × √3 reconstruction of the successive layers and by a semimetallic behavior in its electrical response when integrated into a FET device. Notably, the seeding singlelayer silicene does not retain the same properties of single-layer silicene phases after multilayer growth.43 The ambipolar charge transport of the FET and the comparative Raman analysis are distinctive aspects of multilayer silicene at variance with other observed phases, which prove to have a trivial electrical FET response. Moreover, the first integration of multilayer silicene in a FET device represents a substantial advance over the recently exploited single-layer silicene, thus proving a promising avenue for the stabilization of the quickly degrading single-layer silicene FET and for the fabrication of nanoscaled Si-based devices with nontrivial electrical behavior. The easy access to the transport properties of the multilayer silicene also makes it an appealing playground to investigate the quantum properties of Si at the 2D level, such as the quantum interference of Dirac bands from adjacent layers6 or the functionalization via chemical intercalation.44 METHODS Si thin films were grown in two distinct facilities: a ultra-high vacuum (UHV) chamber (base pressure 10−10−10−11 mbar) system equipped with three interconnected chambers for sample processing, chemical analysis, and in situ Omicron STM characterization (Laboratorio MDM, IMM-CNR) and a UHV apparatus (base pressure 10−11 mbar) equipped with two interconnected chambers for sample growth and Auger spectroscopy analysis and low-energy electron diffraction system (ISM-CNR). Cycles of Ar+ ion sputtering (1 keV) were first performed on 300 nm thick Ag(111) films on mica substrates followed by annealing at 530 °C for 30 min. Si films were deposited from a heated crucible in the built-in evaporator or from a piece of Si wafer at a substrate temperature between room temperature and 350 °C with a 3380

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ACS Nano rate of ∼1 ML/h, where 1 ML refers to a single-layer silicene on Ag(111). Hence, the thickness of multilayer silicene samples is reported here as a multiple integer of single-layer silicene growth. Reported temperatures for multilayer silicene samples grown at the IMM-CNR and ISM-CNR units are 230 and 200 °C, respectively. Temperature reading was cross-checked by pyrometer-based calibration of the thermocouple attached under the sample holder. In situ STM with a chemically etched W tip was employed to monitor the structural characterization. Ex situ Raman spectroscopy was performed by using a Renishaw Invia spectrometer equipped with the 2.4 eV/514 nm line of an Ar+ laser line focused on the sample by a 50× and 0.75 NA Leica objective providing a spot diameter of about 0.8 μm. The power at the sample was maintained at 1 mW in order to prevent laserinduced sample heating, and we acquired hundreds of spectra in order to get the highest signal-to-noise ratio. All of the measurements were carried out in a z-backscattering geometry. All of the devices in this study were made with a silicene transfer and back-gate device fabrication process as established in the SEDNE process.9 A 3 M blue tape or polydimethylsiloxane pad was used to cleave the Si/Ag film stack from mica substrates after multiple peelings, followed by floating on buffered oxide etching solution to remove any residual mica layer. The 2D Si thin films, facing downward, were then placed on a device substrate (95 nm thick SiO2 on p++ Si) to have a firm contact with the SiO2 layer for the fabrication of back-gate transistor devices (see ref 9 for details). Device characterization was measured on Cascade probe stations with an Agilent 4156 analyzer under ambient conditions. A well-accepted ambipolar diffusive model37 was used to extract the fieldeffect mobility and residual carrier density from the Id versus Vg curves.

Notes

The authors declare no competing financial interest.

ACKNOWLEDGMENTS This work has been supported by the CNR Grant “Joint Lab” for the project “Silicene Field Effect Transistors (SFET)”, and partially by the CARIPLO-Regione Lombardia grant for the project “Two-dimensional crystals for Quantum-Spin-Hall insulator electronics (Crystel)”, no. 2016-0978. P.D.P. thanks the IMéRA (Aix-Marseille University) for the fellowship supporting her work from September 2015 to July 2016. D.A. acknowledges the TI/Jack Kilby Faculty Fellowship and the Presidential Early Career Awards for Scientists and Engineers (PECASE) Award. The authors acknowledge M. Alia and C. Martella (Laboratorio MDM, IMM-CNR) for technical support and fruitful discussions, respectively. REFERENCES (1) Kim, D. Y.; Stefanoski, S.; Kurakevych, O. O.; Strobel, T. A. Synthesis of an Open-Framework Allotrope of Silicon. Nat. Mater. 2014, 14, 169−173. (2) He, Y.; Li, H.; Sui, Y.; Qi, J.; Wang, Y.; Chen, Z.; Dong, J.; Li, X. Multilayer Hexagonal Silicon Forming in Slit Nanopore. Sci. Rep. 2015, 5, 14792. (3) Hauge, H. I. T.; Verheijen, M. A.; Conesa-Boj, S.; Etzelstorfer, T.; Watzinger, M.; Kriegner, D.; Zardo, I.; Fasolato, C.; Capitani, F.; Postorino, P.; et al. Hexagonal Silicon Realized. Nano Lett. 2015, 15, 5855−5860. (4) Rogers, J. A., Ahn, J.-H., Eds. Silicon Nanomembranes; Wiley-VCH Verlag GmbH & Co. KGaA: Weinheim, Germany, 2016. (5) Akinwande, D.; Petrone, N.; Hone, J. Two-Dimensional Flexible Nanoelectronics. Nat. Commun. 2014, 5, 5678. (6) Li, Z.; Zhuang, J.; Chen, L.; Ni, Z.; Liu, C.; Wang, L.; Xu, X.; Wang, J.; Pi, X.; Wang, X.; et al. Observation of van Hove Singularities in Twisted Silicene Multilayers. ACS Cent. Sci. 2016, 2, 517−521. (7) Vogt, P.; De Padova, P.; Quaresima, C.; Avila, J.; Frantzeskakis, E.; Asensio, M. C.; Resta, A.; Ealet, B.; Le Lay, G. Silicene: Compelling Experimental Evidence for Graphenelike Two-Dimensional Silicon. Phys. Rev. Lett. 2012, 108, 155501. (8) Grazianetti, C.; Cinquanta, E.; Molle, A. Two-Dimensional Silicon: The Advent of Silicene. 2D Mater. 2016, 3, 012001. (9) Tao, L.; Cinquanta, E.; Chiappe, D.; Grazianetti, C.; Fanciulli, M.; Dubey, M.; Molle, A.; Akinwande, D. Silicene Field-Effect Transistors Operating at Room Temperature. Nat. Nanotechnol. 2015, 10, 227− 231. (10) Qiu, J.; Fu, H.; Xu, Y.; Zhou, Q.; Meng, S.; Li, H.; Chen, L.; Wu, K. From Silicene to Half-Silicane by Hydrogenation. ACS Nano 2015, 9, 11192−11199. (11) Vogt, P.; Capiod, P.; Berthe, M.; Resta, A.; De Padova, P.; Bruhn, T.; Le Lay, G.; Grandidier, B. Synthesis and Electrical Conductivity of Multilayer Silicene. Appl. Phys. Lett. 2014, 104, 021602. (12) Chiappe, D.; Grazianetti, C.; Tallarida, G.; Fanciulli, M.; Molle, A. Local Electronic Properties of Corrugated Silicene Phases. Adv. Mater. 2012, 24, 5088−5093. (13) De Padova, P.; Ottaviani, C.; Quaresima, C.; Olivieri, B.; Imperatori, P.; Salomon, E.; Angot, T.; Quagliano, L.; Romano, C.; Vona, A.; et al. 24 h Stability of Thick Multilayer Silicene in Air. 2D Mater. 2014, 1, 021003. (14) Feng, B.; Ding, Z.; Meng, S.; Yao, Y.; He, X.; Cheng, P.; Chen, L.; Wu, K. Evidence of Silicene in Honeycomb Structures of Silicon on Ag(111). Nano Lett. 2012, 12, 3507−3511. (15) Salomon, E.; El Ajjouri, R.; Le Lay, G.; Angot, T. Growth and Structural Properties of Silicene at Multilayer Coverage. J. Phys.: Condens. Matter 2014, 26, 185003.

ASSOCIATED CONTENT S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.7b00762. Additional STM images (Figures S1 and S2); Raman spectra of SOI reference thin films (Figure S3), lowfrequency modes (Figure S4), and ultraviolet SOR spectra (Figure S5), before and after delamination spectra (Figure S6), and aging spectra (Figure S7); control group devices (Figures S8 and S9); and X-ray photoelectron spectroscopy analysis (Figure S10) (PDF)

AUTHOR INFORMATION Corresponding Authors

*E-mail: [email protected]. *E-mail: [email protected]. ORCID

Carlo Grazianetti: 0000-0003-0060-9804 Alessandro Molle: 0000-0002-3860-4120 Present Addresses ⊥

Dipartimento di Fisica, Politecnico di Milano, Piazza L. da Vinci 32, I-20133 Milano, Italy. ∥ Aix Marseille Université, IMéRA, Marseille, FR-13004, France. Author Contributions

C.G., P.D.P., C.Q., and C.O. performed epitaxial growth of multilayer silicene samples. C.G. also grew amorphous and diamond-like Si samples and performed STM characterization. E.C. and L.T. conducted Raman spectroscopy studies of all the samples. L.T. and D.A. devised and conducted the transfer and device fabrication, transport measurements, and analysis of device data. C.G., E.C., and A.M. planned the experiments. All authors contributed to the writing based on the draft written by C.G., E.C., and L.T.D.A., and A.M. coordinated and supervised the research. 3381

DOI: 10.1021/acsnano.7b00762 ACS Nano 2017, 11, 3376−3382

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DOI: 10.1021/acsnano.7b00762 ACS Nano 2017, 11, 3376−3382