Silicon with Columnar-Micro-Porous Architecture for Ultrahigh Total

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Silicon with Columnar-Micro-Porous Architecture for Ultrahigh Total Energy Storage Capacity and With Highly Reversible Lithiation Performance Bhaskar Vadlamani, M. Jagannathan, and K. S. Ravi Chandran ACS Appl. Energy Mater., Just Accepted Manuscript • DOI: 10.1021/acsaem.7b00064 • Publication Date (Web): 16 Feb 2018 Downloaded from http://pubs.acs.org on February 20, 2018

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ACS Applied Energy Materials

Silicon with Columnar-Micro-Porous Architecture for Ultrahigh Total Energy Storage Capacity and With Highly Reversible Lithiation Performance B. Vadlamani, M. Jagannathan and K.S. Ravi Chandran* Department of Metallurgical Engineering, The University of Utah, Salt Lake City, Utah, 84112, USA. *Author for correspondence: [email protected]

Key Words: Li-ion battery, Silicon, Micro-porous, negative electrode, High capacity, Cycling

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Abstract The continuous miniaturization of microelectronic devices places an ever increasing demand on energy storage capacities of on-chip Li-ion batteries. The search for positive electrodes for such batteries, inevitably leads to Si because of its very high mass specific capacity (~4200 mAh/g for Li4.4Si). Although Si thin films and nanowires can provide very high specific capacities, their storage capacities (measured as coulombs per unit area) are, however, very limited. We report here a new Si electrode architecture, having columnar micro-pores, which provides a very high mass specific Li-storage capacity (~1212 mAh/g), and, the highest total Li-storage capacity (~1.21 mAh/cm2) relative to other Si electrodes. These capacities are sustainable for over 200 cycles. It is shown that columnar micro-porous Si architecture can store a greater amount of charge (~250%) than solid-Si, due to the increased surface area provided by the columnar pores. Further, the most exciting finding of this study is that the pore walls of the columnar micro-porous architecture do not appear to crumble even after a large number of cell cycles, mitigating the Si cracking issues. Electron microscopy revealed that the superior performance is due to the accommodation of volume changes, caused by lithiation, within the pores. The present findings reveal a new pathway for architecturing Si electrodes for much larger and highly reversible total charge-storage capacities for on-chip Li-ion cells.


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There have been impressive advances in the technologies of microelectronic devices in recent years, including the development of high-density CMOS memories1, micro-scale actuators or sensors2, drug delivery systems3 implantable heart defibrillators4 and other such devices5. The functional requirements of these devices strictly isolate them in their application environments. Any external supply of power to these devices is not only challenging but could severely limit their functionality6. Therefore, the concept of “the-chip-that-powers-itself,” where on-chip batteries provide the power, is quite appealing because of the tangible gains in efficiencies of power storage and the de-centralized power distribution, without limiting the functionality. For example, the power requirement of a RFID tag is about 10 µW 7. This device would consume about 300 J of energy in a year. To power such a device for a year, using a single layer of Si thin film Li-ion cell electrode (for example, using a 150 nm thick Si electrode with a total capacity of ~80 µAh/cm2), a chip area of 28000 mm2 will be needed. This size requirement is unrealistic, as this is much larger than the size of a typical semiconductor chip. Evidently, there are constraints on the areal footprint, and hence the total capacity (which depends on the thickness dimension) of the electrode, becomes more important than the mass-specific capacity. Additionally, the integration of on-chip-Li-ion-cell is feasible only if the electrode fabrication process is compatible with electronic micro-fabrication processes. Si is thus attractive from the two important considerations: (i) highest theoretical capacity and (ii) compatibility with chip fabrication.

(a) Challenges with Si thin film electrodes Si thin films, although may appear to be very desirable from the point of view of microfabrication compatibility and impressive specific capacities, they in reality possess a relatively low total energy storage capacity. What is meant by total capacity is the total amount of charge that is stored in the volume the electrode, but delivered over an area on demand, and represented 3 ACS Paragon Plus Environment


here as mAh/cm2. The total capacities of Si thin film electrodes are in the range of 0.04 to 0.11 mAh/cm2 8. For example, an amorphous Si thin film (~50 nm thickness) electrode, provided a total capacity ~ 0.04 mAh/cm2 (specific capacity ~3500 mAh/g) for 200 cycles9 at ~1C rate. However, with a 150 nm thick amorphous Si film, the total and specific capacities reduced to ~ 0.08 mAh/cm2 and ~2200 mAh/g, respectively, after ~200 cycles9. A further increase in film thickness degraded the capacity and cyclability even more—the total and the specific capacities of 300 nm thick Si film were ~ 0.11 mAh/cm2 and ~1700 mAh/g, respectively, after 200 cycles10. The power requirement of RFID tag is ~10 µW 7, which requires a total energy of ~300 J per year to operate. The total capacity of 300 nm thick Si thin film, assuming a delivery area of 30 mm2, is ~0.5 J. This is evidently far lower than that required for RFID tag mentioned above. More importantly, the mass specific capacity of Si thin film is a misleading measure of energy storage capacity because the effective total capacity (~0.11 mAh/cm2), achievable without cracking, is quite low. It is also far less than that required to match the total capacity of 50 µm thick LiCoO2 electrode (1.75 mAh/cm2). Meaningful increases in the total capacities of Si thin films, while requiring high reversibility of lithiation, are not possible for two reasons. First is the diffusion limitation (the Li diffusion coefficient, DLi, in amorphous Si film is ~10-11 to 10-13 cm2/s 11) leading to limits on the thickness of Si that can be lithiated fully—at 1C rate, this thickness is about 190 nm. Another reason is the rapid capacity fading with cycles due to cracking of the film (~300% volume change for Li4.4Si or ~180% for amorphous Li2.7Si during lithiation12), the delamination from the substrate, and the consequent loss of electrical contact13. The total capacity cannot be improved without solving the diffusion limitation problem and the cracking problem.


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(b) Challenges with Si thin film electrodes Recognizing the above limitations of Si thin films, recent researches attempted to improve the performance by making nano structured14 Si electrodes with nanoparticles15,16,17,18,19 or nanowires (NWs)20,21,22 or nanotubes23. For example, nanowires (dia.~141 nm, length~10 µm), grown by the vapor-phase method, exhibited a very high capacity, about ~3500 mAh/g, although this lasted for only 20 cycles at C/5 rate17. This result can be deceiving because the total capacity is only 0.7 mAh/cm2 and this is due to the rather low Si mass density (0.2 mg/cm2) in this nanowire electrode. The total capacity, however, can be increased either by increasing the NW diameter or the density of nanowires, both of which would serve to increase the Si mass density. The mass loading density for NWs of 100 nm diameter is about 0.4 mg/cm2 and it could be increased to 1.52 mg/cm2 for nanowires of 500 nm in diameter24. However, NWs with diameters exceeding 300 nm do not cycle well due to premature fracture during lithiation25.

It is quite important to note that the total capacity of 300 nm diameter NW, which could be taken as an upper limit of a practical nanowire electrode, is only 0.3 mAh/cm2. This is, in fact, far lower than that of graphite electrode21, with ~50 µm thickness (~4 mAh/cm2) that is used in commercial Li-ion cells. Further, the NWs, after some cycling, lost electrical continuity with substrate leading to capacity fading—the roots of NWs do not seem to withstand the stresses created by the volume-changing strains. Thus the NWs, although impressive when assessed in terms of specific capacities, actually show a much lower total capacity and are prone to early fracture during lithiation and delithiation cycling26. Porous Si NW electrode made by electrochemical etching of boron-doped Si wafers, showed improved total capacity, of about 0.6 mAh/cm2 (mass specific capacity=2000 mAh/g) for 250 cycles27—presumably due to the pores enhancing electrolyte access and reducing diffusion path lengths to Si. Moreover, the NW 5 ACS Paragon Plus Environment


synthesis processes are not compatible with conventional semiconductor processing, making the practical implementation in on-chip fabrication more challenging.

(c) Prior work on columnar Si electrodes A compilation of electrochemical performance of columnar Si electrodes made till date by electrochemical etching, photolithographic patterning and plasma etching is summarized in Table S1 of the in supporting information document. The performance of columnar Si electrode (No.2) made by Thakur et al28 is very poor, with a total capacity of 0.076 mAh/cm2 (mass specific capacity=76 mAh/g) after only 10 cycles. In the study by Li et al29 (No.3 in Table S1.), electrochemical etching followed by anisotropic etching route was used to create Si columns of ~108 µm depth with 82 % open intercolumnar spacing. This morphology exhibited a total capacity of 4 mAh/cm2 (877 mAh/g) in 87 cycles. Despite creating a columnar depth of 108 µm, the amount of charge per unit volume that could be stored in this electrode was only 238 mAh/cm3, against the maximum possible value of 1501 mAh/cm3. This represents ~16% utilization of Si electrode for lithiation and therefore this approach is not cost effective. In the work by Sun et al30 (No.4 in Table S1.), the cyclability of porous-Si columns, created by ICPplasma etching, with ~25 µm deep columns was evaluated. However, this structure exhibited a total capacity of just 0.1 mAh/cm2 after 15 cycles. The poor cycling performance was attributed to hydrophobic fluorinated groups that get attached to Si walls, after etching. The performance of two other examples in Table S1. (Nos. 5 and 6) are quite poor that it not essential for the present discussion. Nevertheless, the table makes it clear that despite a higher mass loading or deeper Si columns, none of the previous works reached a reversible mass specific capacity of at least 1000 mAh/g beyond about 108 cycles. In contrast, the present work demonstrates superior


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performance with a total capacity of 1.21 mAh/cm2 (mass specific capacity=1212 mAh/g) over 220 cycles on columnar Si created by a simple etching process.

(d) The present work We demonstrate here that micro-porous Si (µp-Si) architecture, fabricated on single crystal Si wafer by a simple electrochemical etching route, can lead to a high specific energy capacity and the highest-to-date total capacity in Si over 200 cycles. The physical limitations of Si thin films and nanowires, as discussed above, suggest that new strategies must be developed to increase the total capacity of Si electrode to the level required for on-chip application. When the footprint area is the principal geometric constraint, the only way to increase energy storage is to go for a three dimensionally (3D) architectured electrode31,32. The 3-D electrodes, owing to a larger surface area for lithiation or delithiation can lead to higher Li storage capability and could perform well at high cycling rates. One way to create the 3D architecture is to use microfabrication methods (photolithographic patterning and reactive-ion etching) to create 3D columnar structures on Si. However, Si columns with the required small enough sizes (< 1 µm) are not only too difficult to create by photolithography, the process is also expensive. Additionally, the typical lithographic columns (1x1 µm2 columns spaced apart by ~1µm, giving 25% area density) are too far apart leading to a relatively low effective mass of Si available for lithiation. Hence this approach will not lead to high total capacities (see the examples in Table S1.).

The objective of the present work, however, is to show that the architecturing of single crystal Si with columnar micro-pores, made possible by the anisotropic etching characteristics of Si33,34, can produce an electrode with impressive cyclic performance and total energy storage capacity. It is also shown that the columnar pores, with a specific architecture, can 7 ACS Paragon Plus Environment


synergistically accommodate a significant part of the volume increase due to lithiation, and reduce the cracking tendency greatly.

The SEM micrographs showing the top and side views of the micro-porous architecture of the Si (µp-Si) electrode, made by electrochemical etching (see Experimental Methods, in supporting information document), are shown in Figure 1a and 1b respectively. The electrode is made of uniformly distributed columnar pores of 1.1 µm in average diameter and 8 µm in average depth, with a continuous Si wall structure (mass loading density ~0.9 mg/cm2) throughout the electrode. The effective surface area of the columnar micro-pores, available for lithiation, was calculated to be ~14 times higher than that of solid-Si.

The potential of µp-Si architecture, to store a relatively higher amount of Li is first explored through cyclic voltammetric (CV) experiments. The CV data for solid-Si and µp-Si are shown in Figure 2a-c and 2d-f respectively. The most striking result is that the total capacities, as revealed in the lithiation and delithiation currents of µp-Si (Figure 2d), are several times higher than that for solid-Si (Figure 2a). The variations in the total capacities during each cycle, obtained by integrating the CV curve, are shown in Figure 2g. For both Si electrodes, the total capacities increase at first and subsequently reach a plateau. The steady-state total lithiation capacity of µp-Si is ~375 µAh/cm2, which is 250% of that of solid-Si (150 µAh/cm2). This increase in total charge storage capacity can be solely attributed to increased surface area in the columnar pore architecture.

The specific electrode surface reactions, upon lithiation, were also analyzed by evaluating the peak positions. For both solid-Si (Figure 2b) and µp-Si (Figure 2e), the first cycle differs significantly from rest of the cycles. This difference is believed to be due to the formation of film 8 ACS Paragon Plus Environment

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on the electrode during the first lithiation cycle, as explained in Ref. 35. All the lithiation curves exhibit a strong peak at ~0 V (labeled A) and this corresponds to the formation of Li22Si536. An additional lithiation peak (labeled B) starts to evolve at 155 mV in cycle 2 and it progressively shifts toward a lower voltage with further cycling, eventually overlapping with the peak A after 15 cycles. The formation of peak B and its gradual shift to peak-A-position is likely to correspond to the formation of a-LixSi in cycle 2, and its enrichment with Li in subsequent cycles. This enrichment of a-LixSi surface layer with lithiation cycles will naturally make its composition to reach Li4.4Si (or Li22Si5), at ~0 V eventually. This is also evident from the increased peak currents of LixSi and Li4.4Si with cycling. However, it is also possible that the enrichment discussed above may also correspond to Li15Si4, given that the voltage at which Li15Si4 is about 70 mV. The nature of delithiation in µp-Si (and in solid-Si for reference) can be understood by tracking the two peaks labeled C and D, shown in Figure 2c and 2f. The peak C originates at 362 mV in the first cycle and shifts to a higher voltage (430 mV) in subsequent cycles. This may correspond to the formation of Li13Si4 (or Li3.25Si) phase because the final peak is close to 428 mV, which corresponds to the equilibrium potential of Li13Si4 phase37. Similarly, the peak D occurs at 536 mV in the first cycle and progressively shifts to 620 mV in fifteen cycles. This might correspond to Li12Si7 (or Li1.71Si) formation because this peak is close to 582 mV, which is the equilibrium potential of Li12Si7 phase37. Since the peaks in the CV data occur at similar potentials for both solid-Si and µp-Si, it is evident that the columnar micro-pores did not fundamentally alter the mechanism of phase transitions in Si upon lithiation or delithiation. The trends in the CV data for Si and µp-Si are also in agreement with that observed for Si nanowires20, pillars arrays on Si substrate35 or other micro-columnar Si38 morphologies. Further, based on the diffusivity of Li in Si (taken as 10-13 cm2/sec, from literature39), for an example 9 ACS Paragon Plus Environment


period of 1 hr, the depth of lithiation will be ~0.19 µm whereas the average column halfthickness is about 0.6 µm. On this basis, as well as SEM observations where we find the Si columns are intact, it can be concluded that the columns, while lithiated, are not mechanically destroyed in the CV experiments.

The galvanostatic cycling performance of µp-Si electrode and the corresponding variation in specific capacity with cycles are shown in Figure 3a and 3b, respectively. The performance of solid-Si, tested at same current density as the µp-Si electrode, is presented in Figure 3c and 3d. The calculations of mass specific capacities are detailed in section S.II. of the Supporting Information Available. The µp-Si morphology was lithiated to a capacity of 3580 mAh/g during the first cycle. The subsequent delithiation, however, occurred only to a capacity of ~3300 mAh/g. These capacities diminished with further cycling. Nevertheless, it can be seen that µp-Si exhibits an excellent cycling behavior with the specific capacity stabilizing at ~1212 mAh/g after ~220 cycles (test 1). In a duplicate experiment (test 2), µp-Si attained capacity of ~1500 mAh/g after 100 cycles (Figure 3b), which confirms the excellent repeatability of the galvanostatic result. Clearly, this performance is much better than that of solid-Si (Figure 3d) where the specific capacity drops to a low value of ~500 mAh/g in about 33 cycles, after which the cell is an open circuit. The total capacity of the specific Li-storage capacity (~1212 mAh/g), and, the highest total Li-storage capacity (~1.21 mAh/cm2) relative to other Si electrodes. The total Li-storage capacity exhibited by µp-Si electrode, corresponding to a specific capacity of ~1212 mAh/g, is the highest relative to that reported for other Si electrodes. The coulombic efficiencies for both µp-Si and solid-Si are greater than 96% for most of the cycling. However, for an electrode to be used in full cell, a coulombic efficiency of ~99.8% or higher is likely to be needed. 10 ACS Paragon Plus Environment

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To explain the relatively large cyclable total capacity, the structural changes in the microporous electrode were investigated by SEM. The structure of µp-Si electrode after 220 lithiation/delithiation cycles is illustrated in Figure 4(a-f). A regular and stable cracking pattern, resembling tessellated islands of contiguous pore walls (~ 70 x70 µm2; Figure 4a and 4e), is observed in the µp-Si electrode (Figure 4a). The cracks are nearly perpendicular to each other and are perpendicular to electrode edges, which are parallel to (110) planes. This suggests that the cracks are parallel to directions. Such a cracking pattern was also observed by He40 et al. and Maranchi13 et al. in lithiation/delithiation cycling of 500 nm Si thin film. The fact that the (110) plane has a relatively lower fracture toughness41, may explain the observed cracking pattern in µp-Si. Clearly, the formation of the tessellated islands by crystallographically oriented cracks, seem to have helped in relieving the stresses created during lithiation and delithiation cycles. The enlarged SEM micrographs of a representative island are shown in Figure 4b and 4c. Within the island, the residual porosity after 220 cycles is ~11% (Figure 4c) whereas the electrode was ~50% porous prior to lithiation (Figure 1a). This clearly demonstrates that a part of the pore volume (~39%) is filled up by the lithiated phase.

The most remarkable finding of this work is the evidence that (Figure 4e and 4f) almost all of the tessellated islands in the µp-Si are fully intact with substrate, maintaining electrical contact, even after 220 cycles. The detachment of some of the islands (Figure 4f) is due to the cleaning step involved in the preparation of the electrode for SEM. In contrast, the solid-Si is found to crack severely in 33 cycles (Figure 4g and 4h). The extensive delamination and curling of the lithiated layer, followed by the loss of electrical contact with substrate, is clearly is the reason for its poor cycling behavior. On the other hand, the cracking pattern itself cannot sufficiently explain the accommodation of volume change in µp-Si upon lithiation. It is very 11 ACS Paragon Plus Environment


likely that the volume expansion is accommodated principally by the porous structure of µp-Si, largely due to growth of the lithiated phase into the pores. The growth of lithiated phase into pores was observed by FIB imaging in regions marked 1 and 2 in Figure 4f (this is discussed in detail in the supporting information available). Thus, the exceptionally goods cycling performance of µp-Si electrode can be attributed to the unique micro-porous architecture, and this arises from: (i) the increased Si surface area for lithiation, (ii) effective accommodation of volume change within the pore walls and (iii) the preservation of electrical contact at the base of the cracked islands (Figure 4e and 4f) and (iv) the preservation of the columnar structure even after a large number of cycles.

To understand the lithiation processes within the pore walls, the structure of lithiated µpSi was investigated by transmission electron microscopy (Figure 5). The FIB-cut thin slice for TEM imaging is shown in Figure 5a-5c. The lithiation in µp-Si occurred to a depth of about 380 nm from the wall surface, which can be seen as the dark annular region around each pore (indicated by white arrow in Figure 5c). The lattice image (Figure 5e) obtained in a region next to the pore surface (Figure 5d) confirms the formation of amorphous structure (a-LixSi) during lithiation. This is also confirmed by the absence of spots in the corresponding FFT image (Figure 5f) and Kikuchi lines in the CBED pattern (Figure 5g). Moving further into the lithiated region, the amorphous structure transitions to amorphous+crystalline structure, (Figure 5h), where the amorphous matrix is found to contain crystalline islands of Si ~6 nm2 in size, embedded in aLixSi (Figure 5i). This is similar to the formation of amorphous+crystalline structure in NWs20 upon lithiation. Figures 5j through 5k illustrate the NBD patterns confirming the progressive transition of the structure of the lithiated region from amorphous to crystalline Si. The two-phase structure, in the middle of the lithiated region, is characterized by spot and diffuse rings present 12 ACS Paragon Plus Environment

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in the NBD patterns (Figure 5j and 5k). The HRTEM image obtained outside of the annular region shows a fully crystalline Si structure, which is additionally confirmed by FFT (inset) with spots (Figure 5m).

The energy storage capacity of an electrode is truly reflected in terms of its total capacity, as opposed to the conventionally used measure, which is the mass specific capacity. This is illustrated by comparing the variation of specific capacities and total capacities with cycle number, in Figure 6a and 6b respectively, for various forms of Si. The data for µp-Si is from the present work, and the data for Si thin film, nanowire and particle morphologies, taken from literature, are all included. In terms of specific capacity, the thin film (50 nm thick) morphology shows the highest reversible capacity due to a relatively shorter Li diffusion length (thickness). However, when the data are plotted in terms of total capacity (mAh/cm2), the performance of Si thin film is quite poor and this is due to the limited thickness for charge storage. The µp-Si exhibits the highest total capacity (mAh/cm2) amongst all the morphologies considered—this is principally due to a much higher surface area afforded by the columnar micro-porous architecture, which provides for efficient and reversible storage of a relatively higher amount of Li. The µp-Si electrode morphology therefore has the potential to succeed in technological applications such as on-chip batteries.

The present work has demonstrated that µp-Si electrodes can be architectured to produce a high degree of energy storage and with good cell cyclability. In particular, the present work helps to dislodge some negative impressions about the potential of µp-Si that arise from the examination of results in previous works38,42,30,43. For instance, Thakur et al28 reported that their µp-Si provided a specific capacity of only about 500 mAh/g in first cycle, which decreased to 76 mAh/g in the tenth cycle. After modifying the electrode with a gold coating that was deposited 13 ACS Paragon Plus Environment


by evaporation, the specific capacity, although increased in initial cycles, came down to ~1400 mAh/g after 108 cycles. The reason for this good performance, but only with an evaporated gold coating, was not explained. Perhaps due to these factors, the previous works did not generate sufficient enthusiasm about the potential of µp-Si as an electrode for Li-ion battery till date. The present results, on the other hand, convincingly demonstrate the great promise of µp-Si for practical high capacity energy storage electrodes.

In summary, it has been demonstrated that µp-Si, with a columnar architecture, can perform as an electrode material with superior mass-specific capacity as well as total capacity for energy storage in Li-ion cells. An exceptionally high, and, record total capacity of ~1.21 mAh/cm2 (1212 mAh/g) over 220 cycles, for µp-Si, during galvanostatic cycling has been observed. This is comparable to the total storage capacity of LiCoO2 negative electrode (which is about 1.75 mAh/cm2 for 100 µm thick LiCoO2 electrode) in Li-ion cells. The superior performance of µp-Si is attributed to (i) the increased Si surface area for lithiation, (ii) effective accommodation of volume change within the pore walls and (iii) the preservation of electrical contact at the base of tessellated islands and, more importantly, (iv) the preservation of the columnar structure of the pores even after the large number of cycling.


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List of Figures (b)

(a)

3 µm

3 µm

Figure 1. The morphology of µp-Si electrode made by electrochemical etching. (a) top view and (b) side view of the electrode.



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(a)

(c)

(b)

(d)

(f)

(e)

(g)

Figure 2. Cyclic Voltammetric data of µp-Si and solid-Si. Figures (a-c) illustrate the CV data for solid-Si obtained with a scan rate of 0.5 mV/s, with (b) and (c) showing the enlarged portions of lithiation and delithiation. Figures (d-f) illustrate the CV data for µp-Si, also obtained with a scan rate of 0.5 mV/s, with (e) and (f) showing the enlarged portions of lithiation and delithiation 16 ACS Paragon Plus Environment

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peaks. The numbers in Figures (b,d,e,f) indicate the cycle numbers. The letters A,B,C,D in these figures identify the peaks in the CV and are explained in main text. Figure (g) summarizes the total capacities realized during the CV cycles.



(a)

(b)

(c)

(d)

(e)

Figure 3. Galvanostatic cycling performance of µp-Si and solid-Si. Figures (a & b) show the voltage-versus-capacity curves during cell cycling, and the specific capacity values, as a function of cycle for µp-Si. Figures (c &d) show the voltage-versus-capacity curves during cycling, and the specific capacity values, as a function of cycle for solid-Si. Figure (e) shows the coulombic efficiencies as a function of cycle, for both µp-Si and solid-Si. 18 ACS Paragon Plus Environment

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Figure 4. Morphologies of µp-Si and solid-Si electrodes after the 220 and 33 galvanostatic cycles respectively. Figures (a-f) are the SEM micrographs for µp-Si morphology and (g-h) are for solid-Si. The µp-Si shows a regular tessellated cracking pattern in (a) with the micro-pore walls being intact within the islands as shown in (b). The accommodation of volume change by the expansion of lithiated phase within the pore space is seen in (c) with the pore walls being remarkably intact even after cycling for 220 cycles as shown in (d). The tessellated islands in (a) are largely seen to be bonded to the substrate as seen in (e,f) despite the tessellated cracking pattern. On the other hand, a more extensive cracking and curling of lithiated layer in solid-Si is seen in figures (g) and (h). FIB analysis was done on the regions marked 1 and 2 in Figure 4f.



Figure 5. Structure evolution in µp-Si (100) during lithiation. The figures show (a) a section of µp-Si electrode, (b) the FIB cutting of the Si electrode sample, (c) the sample with the LixSi annular regions around pore (indicated by white arrow in (d)), (d) the magnified image of a pore from ‘c’ showing the locations at which NBD patterns were collected and (e) lattice image showing amorphous structure next to the pore surface, which is confirmed by the FFT image in (f). Figure (g) is a CBED pattern from an area of ~46x46 nm2 next to the pore surface showing the amorphous structure. Figure (h) is a low magnification image of the structure next to the pore wall. The image in figure (i) is taken from a location that is ~20 nm from pore surface which shows the amorphous structure embedded with crystalline domains. Figures (j) , (k) and (l) illustrate the NBD patterns, which are collected from regions 1, 2 and 3 in Figure (d) 20 ACS Paragon Plus Environment

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respectively, confirming the progressive transition of the structure of the lithiated region from amorphous to crystalline Si. Figure (m) is a lattice image taken from the unlithiated Si region (with the spot FFT image shown in inset) confirming its crystallinity.



(a)

(b)

Figure 6. Evaluation of the performance of µp-Si architecture against the other forms of Si including thin films, nanowires and nanoparticle electrodes. Figure (a) is in terms of massspecific-capacity (mAh/g) as a function of cycle and Figure (b) is in terms of the total energy storage capacity (defined as mAh/cm2) as a function of cycles. The remarkably superior performance of µp-Si is evident from the comparison made in terms of total capacity.


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Experimental Methods Electrode Preparation: The µp-Si used in this work was fabricated from (100) oriented and p-doped single crystal wafers (obtained from University Wafers, MA, USA) of about 150 mm in diameter. The surface of the wafer was first cleaned with 48% HF to remove any native oxide layer. Electrochemical etching to create porous structure was carried using a home-made etching cell, constructed out of Teflon. A platinum counter electrode and an electrolyte of composition: HF:DMF=1:10 were used for etching. The etching was carried out at a current density of 3 mA/cm2 using KEITHLEY, 2601B Source-meter. The µp-Si electrode produced by the etching was thoroughly rinsed with methanol and dried in flowing nitrogen. Electrochemical Measurements: The electrochemical experiments were performed by assembling the µp-Si electrode and the counter electrode in Swagelock cells made out of Teflon. A lithium foil (750 µm thick) was used as the counter electrode. The electrolyte used was of the composition: 1M LiPF6 in EC:DEC=1:1 (Novolyte Technologies, BASF). The cyclic voltammetric (scan rate of 0.5 mV/sec) and galvanostatic measurements (C/10 rate) were made using the Gamry Potentiostat (Reference 3000). The electrode assembly and the electrochemical and cycling experiments were performed inside an Ar-filled glove box where the levels of H2O and O2 were maintained below 0.1 ppm.

For columnar Si electrode, a current density of 0.33 mA/cm2 was used. This was calculated using the following equation. []. []

Specific capacity (in mAh/g) = [].[].[].[]

(1)



where i is the current in mA, A is the planar area of the electrode (5.7x3.2 mm2), ρ is density of Si (2.33 g/cm3), t is time, and h is the average depth of lithiation (8.275 µm), and f is the area fraction of Si (0.5) in the electrode. With the specific capacity taken as 3580 mAh/g (corresponding to Li15Si4), the current density for cycling comes out as 0.33 mA/cm2. The true current density for cycling, based on the true exposed are of Si in the columnar structure (including column walls and pore bottom), is then 0.022 mA/cm2. Hence, for solid-Si, the current density of 0.022 mA/cm2 was used in the cycling experiments.

The mass specific capacity for µp-Si was calculated based on the regions affected by lithiation, which includes the entire mass of Si columns and a depth of 275 nm below the pores (Supporting Information Available, section S.4). However, for calculating the capacity of solid Si, one needs to assume some lithiated composition in order to estimate the thickness of the original Si that was lithiated. It seems reasonable to assume the lithiated phase to be amorphous with capacity of ~1000 mAh/g with a volume expansion of ~100 %. Based on this the lithiation thickness of Si, in solid Si, comes to be ~0.28 µm (from measurements on FIB sections, see supporting information available, section S.4). Microscopy Analysis: The µp-Si electrodes after cycling were thoroughly cleaned, to remove the electrolyte residue, by shaking the electrodes in DMC for 20 min inside the glove box. The structure of the µp-Si electrode and the pores were examined using SEM (FEI Quanta 600 FEG). The sample for TEM analysis was prepared using the FIB technique using Ga+ ion. Highresolution transmission electron microscopy (HRTEM) imaging and nano beam diffraction (NBD) were conducted using JEOL JEM 2800. The NBD patterns were obtained from an area of 320x320 nm2 in the [0 0 1] zone axis. The CBED patterns were obtained from an area of 46x46 nm2 near the pore surface. 24 ACS Paragon Plus Environment

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Supporting Information Available The supporting information provides a compilation of prior work on electrochemical performance of columnar Si electrodes for Li-ion batteries. Also it provides the verification of the calculation of specific capacity for columnar microporous Si and solid-Si.

Acknowledgment The research was supported by DoE-BES grant DE-FG02-12ER46891. The authors thank DOE-BES Neutron Scattering program for the support and encouragement.



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Graphical Abstract


Silicon with Columnar-Micro-Porous Architecture for Ultrahigh Total

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