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Solution-Processed Carbon Nanotube True Random Number Generator William A Gaviria Rojas, Julian J McMorrow, Michael L Geier, Qianying Tang, Chris H. Kim, Tobin J. Marks, and Mark C Hersam Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.7b02118 • Publication Date (Web): 03 Jul 2017 Downloaded from http://pubs.acs.org on July 6, 2017

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Solution-Processed Carbon Nanotube True Random Number Generator Authors: William A. Gaviria Rojas1*, Julian J. McMorrow1*, Michael L. Geier1, Qianying Tang3, Chris H. Kim3, Tobin J. Marks1,2, and Mark C. Hersam1,2,4 Affiliations: 1

Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois

60208, USA. 2

Department of Chemistry, Northwestern University, Evanston, Illinois 60208, USA.

3

Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN

55455, USA. 4

Department of Electrical Engineering and Computer Science, Northwestern University,

Evanston, Illinois 60208, USA. *These authors contributed equally to this work Correspondence should be addressed to M.C.H. ([email protected])

KEYWORDS: thin-film transistor; printed electronics; Internet of Things; encryption; cybersecurity

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TABLE OF CONTENTS GRAPHIC:

ABSTRACT: With the growing adoption of interconnected electronic devices in consumer and industrial applications, there is increasing demand for robust security protocols when transmitting and receiving sensitive data. Towards this end, hardware true random number generators (TRNGs), commonly used to create encryption keys, offer significant advantages over software pseudo-random number generators. However, the vast network of devices and sensors envisioned for the Internet of Things will require small, low-cost, and mechanically flexible TRNGs with low computational complexity. These rigorous constraints position solution-processed semiconducting single-walled carbon nanotubes (SWCNTs) as leading candidates for nextgeneration security devices. Here, we demonstrate the first TRNG using static random access memory (SRAM) cells based on solution-processed SWCNTs that digitize thermal noise to generate random bits. This bit generation strategy can be readily implemented in hardware with minimal transistor and computational overhead, resulting in an output stream that passes standardized statistical tests for randomness. By using solution-processed semiconducting SWCNTs in a low-power, complementary architecture to achieve TRNG, we demonstrate a promising approach for improving the security of printable and flexible electronics.


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MAIN TEXT: The proliferation of networked physical devices, such as wearable technologies and embedded electronic systems, has enabled unprecedented levels of data collection, exchange, and analysis.1,

2

As more interconnected devices are developed to manage personal and sensitive

information, there is a growing need for robust security primitives. Random number generators are of paramount importance in these security applications since they are commonly combined with other primitives to generate encryption keys.3-5 While software-based pseudo-random number generators are often employed for this purpose, they are inherently non-random in nature with outputs that can be reproduced if the initial seed is known. In contrast, hardware-based true random number generators (TRNGs) use natural phenomena (e.g., thermal noise) to produce outputs that can be truly random, thus enabling superior encryption. The emerging Internet of Things would thus greatly benefit from the enhanced security of integrated TRNGs.1, 2, 6 Portable networked devices further require small-scale and low-cost security hardware components. In addition, emerging wearable technologies often demand low-power computing elements that are ultra-thin and mechanically flexible.7, 8 As a result, existing hardware-based TRNG implementations based on conventional rigid semiconductor substrates and processing methods have found limited utility in flexible electronics applications. For example, optical TRNGs require integrated lasers, photon detectors, and substantial computational overhead to generate random bit streams.9-11 Similarly, small-scale TRNGs based on crystalline semiconductors are not inherently flexible and require expensive processing.12,

13

In contrast,

semiconducting single-walled carbon nanotubes (SWCNTs) are promising candidates for nextgeneration security devices due to their solution-processability, chemical stability, and superlative electronic properties.14-16 With these attributes, semiconducting SWCNTs have been successfully employed in a series of high-performance,17,

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printed,19,

20

and/or flexible electronic

applications.17, 21 To date, SWCNT-based security device demonstrations have been limited to 3 ACS Paragon Plus Environment

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physically unclonable functions (PUFs) that create static, chip-unique cryptographic keys.22 However, in contrast to TRNGs, the demonstrated PUFs are unable to perform critical tasks commonly used in encryption protocols, such as dynamically generating secure keys, cryptographic nonces, and random padding bits. Here, we demonstrate the first TRNG based on a solution-processed semiconductor by employing low-power, complementary SWCNT static random access memory (SRAM) cells.23 This approach requires minimal computational overhead to produce highly random bit streams as confirmed through a series of rigorous tests including the National Institute of Standards and Technology (NIST) randomness statistical test suite (STS)24 and the TestU01 battery tests.25 This work thus presents a promising methodology for improving security in the rapidly growing global network of interconnected electronic and sensing devices. Previous SWCNT thin-film transistor (TFT) efforts have resulted in the realization of complex complementary circuits, such as SRAM cells, with reliable operation and performance.23, 26 Building from that precedent, Figures 1a and 1b show an optical micrograph of a SWCNT TFT-based complementary SRAM cell and its corresponding circuit-level diagram, respectively. The SRAM cell is composed of two p-type (highlighted orange) and two n-type ഥ) (highlighted green) TFTs that correspond to two cross-coupled inverters with output (Q and Q and supply (VDD and GND) terminals. Two access p-type TFTs (highlighted blue) are controlled through the wordline (WL) terminal and tie the bitline (BL and തതതത BL) terminals with the inverter output terminals. A TFT channel length of 20 μm and a 2:1 width ratio (300 μm:150 μm) between the p-type pull-up and n-type pull-down TFTs are used to achieve optimal performance. The SRAM cell arrays were fabricated using previously reported methods.26-28 As can be seen in the cross-sectional schematic of a SWCNT TFT shown in Figure 1c, the fabricated devices employ a local backgate geometry with sorted, semiconducting SWCNTs (99% purity) as 4 ACS Paragon Plus Environment

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the semiconducting channel. As shown by atomic force microscopy in Figure 1d, the SWCNT channel exhibits a random network morphology with a linear density of approximately 10 SWCNTs/μm. After doping the semiconducting channel, a 50 nm Al2O3 encapsulation layer is deposited to ensure dopant stability and thus long device lifetime under ambient conditions. All of the fabrication steps can be performed on polymer substrates,29-31 enabling SRAM fabrication for mechanically flexible applications. Additional fabrication details are summarized in the Supporting Information. In a typical SRAM cell, a single bit is stored within the cross-coupled inverters while power is supplied. When the wordline access transistors are turned on, the bitlines are used to perform read or write operations on the stored bit. However, when power is initially supplied to an SRAM cell, its binary memory state is unknown because symmetry of its cross-coupled inverters leads to a metastable state. This metastability is resolved when thermal noise fluctuations in the transistors drive the system into a stable “0” or “1” voltage level, leading to digitization of the thermal fluctuations. We leverage this digitization of inherently random physical noise to generate a sequence of truly random bits. Figure 2a summarizes how SRAM cells are operated as TRNGs using this principle. During the initialization step, wordline access p-type transistors are turned on (WL = 0 V), both bitlines are biased to VDD (BL = തതതത BL = 1.5 V), and the cross-coupled inverters are powered off (GND = VDD = 1.5 V). In the resolve step of an initialized cell, power is supplied to its cross-coupled inverters (GND = 0 V) while wordline access transistors are turned off (WL = ഥ ) to be randomly driven toward a VDD = 1.5 V), causing the output of each inverter (Q and Q stable complementary binary state by thermal noise fluctuations. A sample output of the resulting ഥ are both in a high state SRAM cell bit generation is shown in Figure 2b. As expected, Q and Q during the initialization step, but exhibit complementary behavior during the resolve step. The measured voltage output of Q during each resolve step is then translated into a binary bit (i.e., 5 ACS Paragon Plus Environment

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high voltage = ‘1’; low voltage = ‘0’). Because the WL and GND voltage inputs act like complementary clock signals, this approach allows multiple SRAM cells to be operated synchronously,32 enabling scalable bit generation throughput. Further testing details are provided in the Supporting Information. Figure 3a shows a representative sample (136 initialization and resolve steps) of WL and Q voltages for a simulated (top) and measured (bottom) SRAM cell operating as a TRNG with a skew towards a logical high state of Q. In particular, a voltage offset between BL and തതതത BL is chosen such that Q resolves to a logical high state for ~95% of the generated bits. On the other തതതത hand, Figure 3b shows simulated and measured outputs for the same SRAM cell with a BL-BL voltage offset such that it operates with no skew (i.e., a fair and balanced distribution). These results exhibit good agreement between simulation and experiment, confirming the validity of the circuit modeling. Further details regarding how annealing affects TRNG performance and how to control TRNG skew can be found in the Supporting Information and prior literature.26 Using this experimental procedure, a total of 61,376 bits were collected from multiple തതതത voltage offsets were chosen for each SRAM cell to SRAM cells. For this bit stream, the BL-BL maximize the randomness of the post-processed output using the well-established von Neumann algorithm.33 The von Neumann algorithm was chosen since it can be easily implemented in hardware and is widely used in traditional TRNGs. Importantly, the SWCNT SRAM cell requires no additional post-processing or active feedback to be implemented as a TRNG. Further details on bit collection are shown in Table S1 of the Supporting Information. To visualize the effectiveness of this random bit generation and post-processing scheme, Figure 3c shows 75 × 75 bitmaps for sample raw (left) and post-processed (right) bit sequences. The bitmaps are created by populating two 75 × 75 matrices in reading order (left-to-right, top-tobottom) with their corresponding bit sequences, where each element in the array corresponds to a 6 ACS Paragon Plus Environment

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pixel, and the value of the pixel indicates its color (‘0’ corresponds to white, ‘1’ corresponds to blue or green). While the bitmap for the raw data is skewed and contains long streaks, no identifiable patterns can be distinguished in the post-processed data bitmap, qualitatively suggesting a high degree of randomness. For a more quantitative assessment of randomness, a histogram of binned data can be compared with the expected theoretical distribution for a random bit sequence. All of the postprocessed bits (“Balanced”) and a representative sample of raw bits of equal length (“Skewed”) are divided into 20-bit segments. The segments are then binned according to the average bit values of their constituent bits. The histograms in Figure 3d represent the frequency of bit values for each corresponding data set. Because a truly random bit sequence is equivalent to the sequence of independent Bernoulli trials for a fair coin, we compare our results with an appropriately scaled binomial probability density function (“Binomial”). The post-processed bit sequence closely matches the expected binomial distribution, again suggesting a high degree of randomness, whereas the raw bit sequence shows a higher mean and lower standard deviation than expected. To further quantify the level of randomness, the post-processed bit stream was subjected to the National Institute of Standards and Technology (NIST) randomness statistical test suite (STS).24 For statistically significant results, the post-processed bit stream was divided into 56 sequences (i.e., the tests were performed 56 times on individual 1096-bit long sequences). Figure 4 shows the results from four of the NIST STS randomness tests. In the frequency test, bits are assigned a value of +1 or -1, and cumulative sums are calculated for each sequence. Figure 4a illustrates the frequency test, where individual plot lines correspond to the running sums of the sequences tested. Evidently, the plot lines are clustered within the expected region for a random sequence.


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We further tested for randomness with the longest run of ones in a block test, which partitions the bit sequence into M-bit blocks, determines the length of the longest consecutive run of “1” bits in each block (“Balanced”), and compares the resulting run occurrences with what would be expected from a random sequence (“Expected”). Figure 4b shows the results of this test using a block size of M = 8 bits. The bar height and superimposed error bars represent the average and standard deviation of the results, respectively, for the 56 sequences tested. The experimental results again show clear agreement with the expectations for a random sequence. A balanced sequence can still fail to be random if the output is skewed towards specific m-bit patterns. Thus, the serial test counts the frequency of all possible overlapping 2m m-bit patterns in a sequence. Figure 4c illustrates the results of the serial test using m = 4 bits. The expected results for a random sequence, which has a uniform distribution, are also plotted in Figure 4c and confirm that the experimental bit stream passes the serial test of randomness. To expose possible periodic features, the spectral output of the discrete fast Fourier transform (FFT) test is shown in Figure 4d. The FFT test calculates the percentage of sequence peak values below the 95% peak value threshold expected for a random sequence. Periodic components are likely to be present if the calculated percentage significantly deviates from 95%. Each plot line corresponds to a sequence, and the percentages on the right of the figure indicate the proportion of peaks below or above threshold. The experimental value of 94.99% agrees well with the 95% expectation for a truly random sequence. Equivalent figures using sample raw data (Figure S1) and further details on the NIST tests are provided in the Supporting Information. The full results of the NIST STS randomness tests are summarized in Table 1. In all cases, the post-processed bit stream is found to be random.24 As an additional check, the postprocessed bit stream was further examined and affirmed to be random by the Rabbit and Alphabit tests from the Test U01 software suite25 (Table S2). Overall, these results show that appropriately 8 ACS Paragon Plus Environment

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designed and biased SWCNT SRAM cells produce highly random bit streams and thus serve as effective TRNGs. In conclusion, we have demonstrated a TRNG using SRAM cells based on solutionprocessed semiconducting SWCNTs. By appropriately biasing the SRAM cells into a metastable state, thermal noise fluctuations are digitized to generate random bit streams. The demonstrated bit generation and post-processing strategy can be readily implemented in hardware and requires minimal transistor and computational overhead. Furthermore, the randomness of the resulting bit stream was rigorously confirmed using a comprehensive panel of established statistical tests. By using solution-processed SWCNTs and circuit architectures that are compatible with large-scale manufacturing methods, this work provides a pathway for the development of low-cost, ultrathin, and mechanically flexible security devices that can be adopted in next-generation portable and wearable electronics.


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Figure 1. SWCNT complementary SRAM cell. (a) Optical micrograph of a fabricated SWCNT complementary SRAM cell, showing labeled contact terminals, p-type inverter pull-up TFTs (orange), n-type inverter pull-down TFTs (green), and bitline access TFTs (blue). (b) Corresponding circuit-level diagram of the SRAM cell shown in part (a). (c) Cross-sectional diagram of a SWCNT TFT fabricated using a semiconducting SWCNT channel, p-type or n-type dopant layer, and Al2O3 encapsulation layer. (d) Atomic force microscopy image of the SWCNT channel showing a random network morphology.


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Figure 2. SRAM operation as a bit generator. (a) Gate-level diagram showing SRAM cell biases during the initialization and resolve steps of bit generation. When the wordline access transistors are turned off and the power to the cross-coupled inverters is turned on, the inverter outputs (Q ഥ ) resolve to a complementary binary state dependent on thermal noise fluctuations. The and Q third terminal in each inverter represents the GND supply terminal. (b) Sample input (WL) and ഥ ) voltages for multiple initialization/resolve steps. The stable analog output output (Q and Q voltage level during each resolve step is interpreted into a single bit, resulting in complementary ഥ. bit sequences for Q and Q


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Figure 3. TRNG output control and initial randomness testing. (a) Simulated (top) and measured തതതത voltage offset (bottom) output from an SRAM cell functioning as a TRNG where the BL-BL creates a skew towards a logical high state for Q. (b) Simulated (top) and measured (bottom) തതതത voltage offset such that it operates output from the same SRAM cell as in part a but with a BL-BL with minimal skew. (c) Bitmaps for sample raw, skewed (blue) and post-processed, balanced (green) bit streams are created by populating two 75 × 75 matrices in reading order (left-to-right, top-to-bottom) with their corresponding bit sequences. A white or colored bit corresponds to a ‘0’ or ‘1’ bit, respectively. (d) Histograms of average bit values when the raw (“Skewed”) and balanced (“Balanced”) bit streams are divided into 20-bit segments. The expected binomial probability distribution function is also shown for comparison.


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Figure 4. NIST STS randomness testing on balanced bits. (a) Illustration of the frequency test, where bits are assigned values of -1 or +1 and each plot line represents the cumulative sum of each bit sequence. The highlighted range represents passing sum values. (b) Illustration of the longest run of ones test, where the lengths of the longest consecutive runs of “1” bits of M-bit blocks in the sequences are counted. The error bars represent the standard deviation of the sequences tested. The expected distribution for a random sequence (“Expected”) is also shown. (c) Illustration of the serial test, which calculates the frequency of m-bit patterns in a sequence. The expected uniform distribution for a random bit sequence is also shown. (d) Illustration of the fast Fourier transform (FFT) test, showing the spectra for all sequences tested. A random bit sequence is expected to have 95% of its peaks below the indicated threshold.


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Table 1. Summary of NIST STS Results NIST statistical testa

p-value

proportion

resultb

Frequency

0.007694

56/56

PASS

Block Frequency

0.350485

56/56

PASS

Cumulative Sums

0.153763

56/56

PASS

Runs

0.085587

53/56

PASS

Longest Run of Ones

0.935716

56/56

PASS

Rank

0.956003

1/1

PASS

Discrete Fourier Transform

0.002374

55/56

PASS

Approximate Entropy

0.236810

54/56

PASS

Serial

0.455937

56/56

PASS

a

With the exception of the Rank test, these tests were performed using 56 sequences of 1,096 bits each, such that only the first 61,376 collected bits were tested.

b

A p-value > 0.001 and a proportion > 53/56 are required for a test to pass.

Supporting Information. Methods; SWCNT SRAM TRNG skew control; table of bits collected from SWCNT SRAM devices following post-processing; brief overview of select NIST statistical tests; table of TestU01 results; figures of NIST STS randomness testing on a representative sample of raw bits.

Acknowledgments. This work was supported by the Office of Naval Research MURI Program (N00014-11-1-0690) and the National Science Foundation (DMR-1121262 and CCF-0845605). A National Science Foundation Graduate Research Fellowship (W.A.G.R.), and a NASA Space Technology Research Fellowship (J.J.M.) are also acknowledged. The device fabrication was performed at the NUFAB clean room facility at Northwestern University. 14 ACS Paragon Plus Environment

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Author Information. Correspondence should be addressed to M.C.H. ([email protected]). Conflict of Interest Disclosure. The authors declare no competing financial interest.

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