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Temperature dependent border trap response produced by a defective interfacial oxide layer in AlO/InGaAs gate stacks 2

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Kechao Tang, Andrew C. Meng, Ravi Droopad, and Paul C McIntyre ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b10402 • Publication Date (Web): 19 Oct 2016 Downloaded from http://pubs.acs.org on October 26, 2016

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ACS Applied Materials & Interfaces

Temperature dependent border trap response produced by a defective interfacial oxide layer in Al2O3/InGaAs gate stacks Kechao Tang,† Andrew C. Meng, † Ravi Droopad,# and Paul C. McIntyre*,† †

Department of Materials Science and Engineering, Stanford University, Stanford, California

94305, USA #

Ingram School of Engineering, Texas State University, San Marcos, Texas 78666, USA

KEYWORDS: InGaAs, Al2O3, border traps, interlayer, atomic layer deposition, MOSCAP

ACS Paragon Plus Environment

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ABSTRACT: Intentional oxidation of an As2-decapped (100) In0.57Ga0.43As substrate by additional H2O dosing during initial Al2O3 gate dielectric atomic layer deposition (ALD) increases the interface trap density (Dit), lowers the band edge photoluminescence (PL) intensity, and generates Ga-oxide detected by x-ray photoelectron spectroscopy (XPS). Aberrationcorrected high resolution transmission electron microscopy (TEM) reveals formation of an amorphous interfacial layer which is distinct from the Al2O3 dielectric and which is not present without the additional H2O dosing. Observation of a temperature dependent border trap response, associated with the frequency dispersion of the accumulation capacitance and conductance of metal-oxide-semiconductor (MOS) structures, is found to be correlated with the presence of this defective interfacial layer. MOS capacitors prepared with additional H2O dosing show a notable decrease (~20%) of accumulation dispersion over 5 kHz to 500 kHz when the measurement temperature decreases from room temperature to 77 K, while capacitors prepared with an abrupt Al2O3/InGaAs interface display little change (< 2%) with temperature. Similar temperaturedependent border trap response is also observed when the (100) InGaAs surface is treated with a previously-reported HCl(aq) wet cleaning procedure prior to Al2O3 ALD. These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III-V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface.


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1. INTRODUCTION For future highly-scaled n-channel metal-oxide-semiconductor (MOS) devices, In0.53Ga0.47As and atomic layer deposited high-k dielectrics, like Al2O3, HfO2, and ZrO2, are among the candidate channel and dielectric materials respectively.1-6 To achieve high performance in practical logic devices, however, a longstanding issue for III-V/high-k structures is the presence of interfacial charge traps that may induce Fermi level pinning.7-11 In recent years, electrically active charge trapping defects in the oxide layer, called the border traps, have also gained increasing attention.12-14 In multi-frequency capacitance-voltage (C-V) measurements, border traps produce substantial frequency dispersion in accumulation, an energy range at which a carrier trap response from interface defects cannot be measured at typical C-V testing frequencies.15-16 In contrast to the interface trap response in the inversion region, a very weak temperature dependence of the border trap response in accumulation is frequently observed.17-20 However, several recently published works on InGaAs/high-k gate stacks show accumulation dispersion that decreases by more than 50% when the C-V measurement temperature is lowered from room temperature (RT) to 77 K.21-22 This discrepancy has prompted different interpretations of the trap mechanism19,

21-23

and thus complicates the understanding of border traps in InGaAs/high-k

devices. In this report, we investigate the origins of the varying temperature dependence of the dispersive trap response measured in accumulation, and find that variations in the temperature dependence of this response reported in the literature may be a consequence of differences in the abruptness of the InGaAs/high-k interface. One important distinction between the InGaAs/high-k samples in prior reported border trap studies is the substrate surface preparation used before ALD gate dielectric deposition. In Ref. 21, air-exposed (100) InGaAs surfaces are treated with aqueous hydrochloric acid solution and


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then rinsed with de-ionized (DI) water before loading into the ALD chamber. The initial air exposure, acid clean and DI water rinsing process exposes the InGaAs surface to contaminants, etchants and oxidants whose effects on the surface are difficult to predict, but may produce a defective mixed InGaAs oxide on which the subsequent dielectric deposition takes place. Regarding the final DI water rinse step, high interface trap densities associated with surface oxide formation have been detected in previous studies, when either an unprotected InGaAs surface24-25 or InGaAs coated with a thin (~1.2 nm) Al2O3 layer26 is exposed to H2O. In contrast to Ref. 21, the pre-ALD sample preparation used in Ref.’s 17 and 18 employed an in-situ As2 decapping procedure, the details of which can be found in the methods section of this report and in Ref. 27. In this procedure, the as-grown InGaAs surface is protected by an As2 cap layer from exposure to atmosphere prior to loading the substrate into a load-locked, high vacuum base pressure ALD reactor. Exposure to O2 and H2O is minimized as the As2 layer is thermally desorbed in-situ under vacuum, immediately prior to the start of Al2O3 ALD on the InGaAs surface.27 In-situ decapping produces a generally smaller dispersive interface trap feature in capacitance-voltage measurements compared to that reported in Ref. 21.13 Direct comparison of the Dit values reported25 for ALD-Al2O3 MOS capacitors on InGaAs (100) substrates prepared by HCl(aq) cleaning treatment used in Ref. 21 and those obtained in this study using in-situ As2 decapping28 may not be reliable, due to the different Dit extraction methods applied in these two works. However, applying the same full interface state Dit model15 employed in the present study to analyze capacitance-voltage data for HCl(aq) cleaned InGaAs samples reported in Ref. 25 gives a significantly higher Dit distribution compared to the in-situ As2 decapped samples28 over the entire InGaAs band gap (Figure S1 and S2 of the Supporting Information). Therefore, different surface preparation schemes are expected to produce local composition and structure


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differences near the InGaAs/high-k interface that may produce variations in border trap response and its measurement temperature dependence. In this work, we investigate this hypothesis by comparing the Al2O3/InGaAs gate stacks prepared by a standard in-situ As2 decapping procedure followed immediately by Al2O3 ALD to samples treated with extra H2O exposure in a portion of the initial stage of ALD. Extra H2O dosing is not meant to re-create the ex-situ wet cleaning process, but serves as a well-established approach26 to degrade the interface quality by subcutaneous oxidation of the InGaAs substrate surface. Quantitative interface trap density (Dit) analysis15 using multi-frequency C-V measurement, and photoluminescence (PL) spectroscopy are employed to evaluate the electrical quality of the interface. We also use x-ray photoelectron spectroscopy (XPS) and aberrationcorrected high resolution transmission electron microscopy (TEM) cross-sectional imaging to characterize composition and structural changes at the interface resulting from additional H2O dosing. With these characterization results, multi-temperature C-V measurement from RT to 77 K are performed on these two sets of samples, to check the relationship between the temperature dependence of border trap response on the abruptness of the InGaAs/high-k interface. 2. MATERIALS AND METHODS Epitaxial n-type In0.53Ga0.47As (100) wafers with Si doping (1×1017 cm-3) were covered with an amorphous As2 capping layer that condenses on the InGaAs channel during post-growth cooling in the molecular beam epitaxy chamber. The As2 cap prevents surface oxidation during air exposure of the substrates prior to loading in the ALD chamber. Before the initiation of Al2O3 ALD, the As2 cap was thermally desorbed at a pressure of ~ 10-6 Torr and a temperature of ~350°C in-situ in the ALD chamber. As a control sample, approximately 4.5 nm of Al2O3 was


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deposited with 60 cycles of alternating trimethylaluminum (TMA) and H2O pulses at 270°C. The pulse duration was 3 s for TMA and 4 s for H2O, corresponding to an estimated dose per cycle of 900 L and 1200 L, respectively. The chamber pressure during ALD was maintained at 0.68 Torr by continuous flow of dry N2 into the chamber. For the test sample with additional water dosing, a total of 60 cycles of ALD was performed, but 20 pulses of additional H2O vapor were inserted after the first 15 cycles of Al2O3 ALD, which produces an Al2O3 layer of ~ 1.1 nm thickness. The extra H2O dosing was not performed immediately after As2 decapping due to the concern that the dosing procedure might alter the initiation of the Al2O3 ALD, thus inducing additional differences in the Al2O3 film quality close to the interface, and complicating further analysis. The additional H2O dosing was performed at the same substrate temperature (270°C), and the total additional dose was approximately 6,000 L. After Al2O3 deposition, 40 nm thick Pd (circular, 50 – 125 µm radius) top gates and 100 nm Al back contacts were deposited on both sets of samples by thermal evaporation. Further details of the experimental methods can be found in Ref. 27. The fabricated Pd/Al2O3/InGaAs MOS capacitors were then annealed after metallization in forming gas (5%H2/95%N2) at 400°C for 30 minutes in a quartz tube furnace. For initial electrical characterization, multi-frequency C-V curves were measured in the 1 kHz to 1 MHz frequency range at RT in the dark, using a HP4284A LCR meter. Multitemperature C-V measurements ranging from RT to 77 K were carried out in a Janis cryogenic vacuum probe station, with the data collected by Keithley 4200-SCS assembly. As an additional method to evaluate the interface quality of Al2O3/InGaAs stacks, photoluminescence (PL) spectra were obtained with a 532 nm laser source at an intensity of ~ 100 W/cm2 on the sample surface. PL signals were detected using strained InGaAs (1000 nm – 2000 nm) photo detector.


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XPS measurements were performed using a PHI VersaProbe Scanning XPS Microprobe with Al k-α radiation (1486 eV) in a high vacuum environment of ~5×10-8 Torr pressure and xray incidence angle 45°. High resolution TEM images of cross-section samples were taken with an FEI Titan transmission electron microscope equipped with a spherical aberration image corrector operating at 300 kV. Cross-section TEM samples were fabricated using an FEI Helios Nanolab 600i DualBeam focused ion beam (FIB)/scanning electron microscope (SEM). In this procedure, an amorphous carbon (a-C) protection layer was deposited by electron beam to prevent damage to the TEM samples. Prior TEM and electron diffraction studies indicate that ALD-Al2O3 layers deposited and annealed under the conditions employed in these studies are amorphous.29 3. RESULTS AND DISCUSSION Figure 1 (a) and (b) show C-V data of samples prepared with the standard procedure and those with additional H2O dosing at the initial stage of ALD, respectively. For the RT measurement, both samples display similar degrees of frequency dispersion in accumulation, and identical values of border trap density (Nbt) of 1.0 × 1020 cm-3eV-1 at E – EC = 0.5 eV were extracted for both samples using the border trap model in Ref. 23. Regarding the interface quality, the Al2O3 InGaAs stacks with added H2O dosing exhibit a notable increase in the size of the dispersive inversion feature compared to the standard process, coinciding with consistently higher Dit values extracted using the full interface state model15 across the InGaAs band gap (Figure 1 (c)). This result indicates generation of additional traps at the interface due to H2O dosing, consistent with previous literature24-26. The degradation of the interface is also supported by the PL data in Figure 1 (d). The peak of the PL spectra is detected at 1660 nm, corresponding to band-edge luminescence of In0.53Ga0.47As (0.75 eV).30 Lower PL intensity around the peak was detected for


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gate stacks prepared with additional H2O dosing during ALD, suggesting an increase in nonradiative recombination of photo-generated carriers31 at the larger density of interface charge traps present in these samples.

Figure 1. (a) and (b) Multi-frequency (1 kHz – 1 MHz) C-V curves for Pd/Al2O3/InGaAs samples prepared with the regular ALD procedure and with additional H2O dosing, respectively. (c) Extracted Dit energy distribution for the above two samples (d) PL spectra for 4.5 nm Al2O3/InGaAs without and with additional H2O dosing. XPS was employed to check for the chemical change of the interface after the extra H2O dosing. To increase the surface sensitivity, Ga 2p3 core level spectra were measured. The high binding energy of electrons in these states allows for detection of photoelectrons emitted from only the top few atomic layers of the sample. Accordingly, both the standard sample and the added H2O dose sample were coated with a particularly thin Al2O3 layer (~1.1 nm) for this XPS measurement. The standard sample has only 15 cycles of Al2O3 ALD on InGaAs, and the H2O dosed sample has 15 cycles of Al2O3 ALD plus 20 cycles of H2O dosing, identical to that in Figure 1 (b). From the XPS spectra in Figure 2, the added H2O dose sample clearly exhibits a


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Ga-oxide feature at a binding energy of 1118.6 eV, while this feature is not detected at the Al2O3/InGaAs interface prepared without added H2O dosing. This result is clear evidence of subcutaneous oxidation of the InGaAs substrate during added H2O dosing, which coincides with the larger post-forming gas interface trap dispersion observed in Figure 1.

Figure 2. Ga 2p3 peak measured by XPS for 1.1 nm Al2O3/InGaAs without (a) and with (b) H2O dosing, respectively. The background signal was subtracted and the intensity was normalized. To further characterize the structural differences that result from added H2O dosing, aberration corrected high resolution TEM was used to image the Al2O3/InGaAs interface in cross-section. Figure 3 shows low-magnification and high-magnification (inset) images of two samples. Under InGaAs (110) zone-axis imaging, lattice fringes in the crystalline InGaAs substrate and the amorphous structure of the Al2O3 layer are clearly distinguished. The Al2O3 layer appears brighter in the image due to its weaker atomic number contrast: Al and O atoms scatter the electron beam more weakly than In, Ga, and As, thus producing higher bright field transmitted beam intensity. Careful examination of the high-magnification image of the sample with added H2O dosing reveals a thin (~0.8 nm) but clear amorphous interlayer between Al2O3 and the InGaAs substrate (Figure 3(b)). In contrast, no such interlayer appears in the control gate stacks using the standard ALD process (Figure 3(a)). Considering the XPS data in Figure 2 (b), observation of this amorphous interlayer coincides with oxidation of the InGaAs surface that


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results from the additional oxidant dosing used in depositing this sample. Another difference between the two samples evidenced by the TEM images is the ~ 20% smaller total Al2O3 layer thickness when additional H2O dosing is used in the ALD process. The reduced oxide thickness may be related to the interruption of Al2O3 ALD by the H2O dosing treatment, which could affect the re-initiation of ALD in the second segment of Al2O3 deposition. This difference in oxide layer thickness coincides with a slightly higher maximum capacitance for the H2O dosing treated sample in Figure 1.

Figure

3.

Aberration

corrected

high

resolution

TEM

cross-sectional

imaging

for

Pd/Al2O3/InGaAs gate stacks without (a) and with (b) H2O dosing, respectively. Combining the results of these varied characterization methods, it is evident that additional H2O dosing produces a partially- oxidized and defective interfacial layer that exhibits a higher interface state density (Fig. 1) than do Al2O3/InGaAs gate stacks prepared with the standard ALD process. The effect of these two very different interface structures on the temperature dependence of border trap response was tested using multi-frequency and multi-temperature C-V measurements (Figure 4). Each figure includes the percent accumulation dispersion per decade of frequency variation at Vg = 2.0 V, which was obtained by linear-log fitting of the capacitance with respect to frequency at that gate bias. The dispersion can be quantified simply using the following formula:


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=

− 1 × log ( / )

(1)

in which D is the frequency dispersion, fhigh and flow are the highest frequency and lowest frequency respectively, while Chigh and Clow are the capacitance at these frequencies. For each set of C-V curves in Figure 4, measurements on at least three different gate sizes were performed, and the accumulation dispersion value was highly reproducible (deviation < 0.1% in absolute dispersion). For the gate stacks made with the standard ALD process, the accumulation dispersion was almost unchanged when the measurement temperature decreased from 300 K to 77 K (Figure 4 (a) and (b)), consistent with our previous measurement results on Al2O3/InGaAs gate stacks prepared with the same fabrication process. On the other hand, for those prepared with added H2O dosing, a small but notable decrease in the frequency dispersion was detected (Figure 4 (c) and (d)). The relative decrease of frequency dispersion is ~20% and is reproducible, indicating a fundamental difference compared to the samples without added H2O dosing. Therefore, by inserting additional H2O dosing that leads to formation of an oxidized interlayer between Al2O3 and InGaAs, the accumulation dispersion of the sample goes from being effectively temperature independent to being temperature dependent. Combined with the fact that, in Ref. 21, the InGaAs channel surface is unavoidably in contact with H2O as a result of wet cleaning before Al2O3 ALD, these results point to the fact that the temperature dependence of the border trap dispersion may result from InGaAs surface oxidation and formation of a defective interfacial layer at the InGaAs/high-k interface.


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Figure 4. (a) and (b) C-V curves measured at room temperature (300 K) and 77 K, respectively, for Pd/Al2O3/InGaAs with regular procedure (no H2O dosing). (c) and (d) C-V curves measured at room temperature and 77 K, respectively, for Pd/Al2O3/InGaAs with H2O dosing. The dispersion per decade of frequency at accumulation region is extracted through linear fitting of C-f at Vg = 2 V. To further test this hypothesis, we performed another experiment in which the wet cleaning recipe in Ref. 21 was inserted into our gate stack fabrication process. For this set of samples, after the As2 decapping, the InGaAs substrate was removed from the chamber and was treated with a 2M HCl(aq) solution as in Ref. 21, and then reloaded in the chamber for 60 cycles of Al2O3 ALD. The transfer time between the sample coming out of the HCl(aq) solution and pumping down in the chamber was minimized to ~ 3 mins. A control set of samples following our standard process was deposited with 60 cycles of Al2O3 ALD, immediately after the in-situ As2 decapping. The metallization process was the same as that described in the methods section, except forming gas anneal (FGA) was not done here, due to increased gate leakage measured for the samples with wet cleaning after FGA. By comparing the C-V curves measured for these two sets of samples in Figure 5 (a) and Figure 5 (c), an increase of the Dit feature in inversion is


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evident after inserting the wet clean process and higher Dit values are extracted, as shown in Figure 5 (g). In Figure 5 (e) and 5 (f), XPS spectra were collected from in-situ As2 decapped and HCl solution cleaned InGaAs surfaces coated by 1.1 nm thick Al2O3, similar to the comparison used in Figure 2. While the in-situ As2 decapped sample shows no evidence of a Ga-oxide feature, the one with HCl solution cleaning is distinguished by a clear Ga-oxide peak. This result, together with the increase of Dit, indicates degradation of the interface due to oxidation of the InGaAs, which can be attributed to this pre-ALD HCl(aq) wet cleaning procedure, which is the only significant difference between the two samples.


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Figure 5. (a) and (b) C-V curves measured at room temperature (300 K) and 77 K, respectively, for Pd/Al2O3/InGaAs with regular insitu As2 decapping procedure. (c) and (d) C-V curves measured at room temperature and 77 K, respectively, for Pd/Al2O3/InGaAs treated with preALD wet clean by HCl solution. (e) and (f) Ga 2p3 peak measured by XPS for 1.1 nm Al2O3/InGaAs with insitu As2 decapping and HCl(aq) treatment, respectively. (g) Extracted Dit energy distribution for the above two samples. Importantly, when the C-V measurement temperature was lowered to 77 K, a clear decrease of accumulation dispersion from 7.4% to 5.4% is detected for the wet clean sample, but the As2 decapped control sample (Figure 5 (a)-(d)) exhibits an almost athermal accumulation dispersion. This control experiment indicates that, similar to the situation for added H2O dosing during the early stages of Al2O3 ALD, the wet clean procedure reported in Ref. 21 produces a defective surface oxide at the InGaAs/Al2O3 interface that both increases the interface defect density and increases the temperature dependence of the accumulation dispersion compared to the situation for MOS capacitors in which in-situ As2 decapping only was used prior to the start of ALD. It is important to mention that the above conclusion does not imply a universal problem of oxidation and defect generation in all ex-situ surface preparations of InGaAs (100) substrates, compared to in-situ surface treatments.


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Figure 6. Schematic band diagram for Al2O3/InGaAs gate stacks with (a) an abrupt interface and (b) presence of a defective interlayer. The experimental results shown in Figures 1 - 5 and reported results in the literature indicate a correlation between channel surface preparation methods that result in formation of defective interlayer oxide and a temperature dependence of the accumulation capacitance frequency dispersion of high-k/InGaAs gate stacks.

The relatively athermal behavior exhibited by

Al2O3/InGaAs MOSCAPs with abrupt interfaces is a consequence of elastic tunneling of carriers between the majority band of InGaAs and defect states in the Al2O3 (Figure 6(a)). When a defective interlayer is present (Figure 6(b)), additional charge trapping processes can occur. A thermally activated pathway via interlayer defects (Figure 6(b)) provides a possible explanation for the temperature dependence of the border trap response in the case of an interfacial layer. Apart from directly tunneling into traps in the gate oxide layer, the majority carriers can also initially be trapped in the defective interlayer, a process that may be thermally activated, and then tunnel into the border traps in the Al2O3 layer. At room temperature, the trapping time constant of the defective interlayer is much lower compared to that for tunneling through the Al2O3 layer. Consequently, the defective interlayer is constantly trapping electrons from the nInGaAs substrate and acts as a source of electrons that then tunnel into the near-surface Al2O3 layer. The border trap response is still controlled by the depth and energy distributions of traps in the Al2O3, which accounts for the similar Nbt value extract at room temperature regardless of the presence of an interfacial layer (Figure 1). Decreasing temperature will slow thermally activated processes, such as carrier hopping and trapping at gap states associated with interlayer defects. This will greatly increase the time constant of such processes. Thermally activated mechanisms will freeze out at very low temperatures, causing direct tunneling through the entire layer


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structure to become dominant. As a result, the defective interlayer increasingly acts as an insulator at low temperatures. The electrical response of border traps, in the presence of such a defective interlayer, should decrease at very low temperatures and the magnitude of the response may be less than that of an abrupt interface because of the longer tunneling distances required. Carrier trapping via defects in the interlayer produced by InGaAs substrate oxidation may be analogous to trapping by disorder induced gap states (DIGS). As reported in previous work on high-k/InGaAs,32 DIGS charge trapping is also associated with a defective interface and is dependent on temperature.33 4. CONCLUSION Exposure of the InGaAs (100) surface to either added H2O dosing during the early stages Al2O3 ALD or to a standard pre-ALD HCl(aq) wet cleaning procedure produces similar increases in interface trap density compared to otherwise identical MOS capacitors prepared using in-situ As2-decapping of the InGaAs immediately prior to Al2O3 ALD. This interface defect generation is correlated directly to growth of an interlayer by partial oxidation of the InGaAs surface. Formation of this defective interlayer coincides with an increase in the temperature dependence of the accumulation dispersion, or border trap response, detected in capacitance-voltage measurements. This dispersion is almost temperature-independent for an abrupt InGaAs/Al2O3 interface, indicating that quantum tunneling of carriers across this interface is responsible for the accumulation dispersion for such simple interfaces.

Samples with a defective interlayer

interposed between the Al2O3 and InGaAs evidently possess other, thermally-activated, pathways for carrier trapping in the oxide, thus reducing the dispersion measured at low temperatures. With further understanding of these pathways, measurements of temperature-dependent


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accumulation dispersion may provide a simple means of checking for the presence of such an interlayer using C-V analysis at varying temperatures. AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] (P.C.M.).

ACKNOWLEDGMENT The authors acknowledge support from Semiconductor Research Corporation through the NonClassical CMOS Research Center (Task ID 1437.008), the Stanford Initiative in Nanoscale Materials and Processes (INMP), and the US-Israel Binational Science Foundation. Part of this study was performed at the Stanford Nano Shared Facilities (SNSF).

Supporting Information. Figure S1: Comparison of Dit for the Al2O3/InGaAs samples with HCl (aq) clean treatment as reported in Ref. 25 and those with in-situ As2 decapping treatment in Ref. 28, using the same full interface state model. Figure S2: Illustration for the digitalization procedures of the data plot in Ref. 25.


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16. Lin, D.; Alian, A.; Gupta, S.; Yang, B.; Bury, E.; Sioncke, S.; Degraeve, R.; Toledano, M. L.; Krom, R.; Favia, P.; Bender, H.; Caymax, M.; Saraswat, K. C.; Collaert, N.; Thean, A., Beyond Interface: The Impact of Oxide Border Traps on InGaAs and Ge n-MOSFETs, IEEE Int. Electron Devices Meet. 2012, 28.3.1-28.3.4. 17. Kim, E. J.; Chagarov, E.; Cagnon, J.; Yuan, Y.; Kummel, A. C.; Asbeck, P. M.; Stemmer, S.; Saraswat, K. C.; McIntyre, P. C., Atomically Abrupt and Unpinned Al2O3/In0.53Ga0.47As Interfaces: Experiment and Simulation. J. Appl. Phys. 2009, 106, 124508. 18. Chen, H.-P.; Ahn, J.; McIntyre, P. C.; Taur, Y., Effects of Oxide Thickness and Temperature on Dispersions in InGaAs MOS C-V Characteristics. J. Vac. Sci. Technol. B 2014, 32, 03D111. 19. Zhang, C.; Xu, M.; Ye, P. D.; Li, X., A Distributive-Transconductance Model for Border Traps in III-V/High-k MOS Capacitors. IEEE Electron Device Lett. 2013, 34, 735-737. 20. Lind, E.; Niquet, Y.-M.; Mera, H.; Wernersson, L.-E., Accumulation Capacitance of Narrow Band Gap Metal-Oxide-Semiconductor Capacitors. Appl. Phys. Lett. 2010, 96, 233507. 21. Vais, A.; Lin, H.-C.; Dou, C.; Martens, K.; Ivanov, T.; Xie, Q.; Tang, F.; Givens, M.; Maes, J.; Collaert, N.; Raskin, J.-P.; DeMeyer, K.; Thean, A., Temperature Dependence of Frequency Dispersion in III–V Metal-Oxide-Semiconductor C-V and the Capture/Emission Process of Border Traps. Appl. Phys. Lett. 2015, 107, 053504. 22. Dou, C.; Lin, D.; Vais, A.; Ivanov, T.; Chen, H.-P.; Martens, K.; Kakushima, K.; Iwai, H.; Taur, Y.; Thean, A.; Groeseneken, G., Determination of Energy and Spatial Distribution of Oxide Border Traps in In0.53Ga0.47As MOS Capacitors from Capacitance–Voltage Characteristics Measured at Various Temperatures. Microelectron. Reliab. 2014, 54, 746-754. 23. Yuan, Y.; Yu, B.; Ahn, J.; McIntyre, P. C.; Asbeck, P. M.; Rodwell, M. J. W.; Taur, Y., A Distributed Bulk-Oxide Trap Model for Al2O3 InGaAs MOS Devices. IEEE Trans. Electron Devices 2012, 59, 2100-2106. 24. Shin, B.; Clemens, J. B.; Kelly, M. A.; Kummel, A. C.; McIntyre, P. C., Arsenic Decapping and Half Cycle Reactions During Atomic Layer Deposition of Al2O3 on In0.53Ga0.47As(001). Appl. Phys. Lett. 2010, 96, 252907. 25. Ameen, M.; Nyns, L.; Sioncke, S.; Lin, D.; Ivanov, T.; Conard, T.; Meersschaut, J.; Feteha, M. Y.; Van Elshocht, S.; Delabie, A., Al2O3/InGaAs Metal-Oxide-Semiconductor Interface Properties: Impact of Gd2O3 and Sc2O3 Interfacial Layers by Atomic Layer Deposition. ECS J. Solid State Sci. Technol. 2014, 3, N133-N141. 26. Ahn, J.; McIntyre, P. C., Subcutaneous Oxidation of In0.53Ga0.47As(100) through UltraThin Atomic Layer Deposited Al2O3. Appl. Phys. Lett. 2013, 103, 251602. 27. Ahn, J.; Shin, B.; McIntyre, P. C., In Situ As2 Decapping and Atomic Layer Deposition of Al2O3 on n-InGaAs(100). ECS Trans. 2012, 45, 183-188. 28. Ahn, J.; Kent, T.; Chagarov, E.; Tang, K.; Kummel, A. C.; McIntyre, P. C., Arsenic Decapping and Pre-Atomic Layer Deposition Trimethylaluminum Passivation of Al2O3/InGaAs(100) Interfaces. Appl. Phys. Lett. 2013, 103, 071602. 29. Ahn, J.; Geppert, I.; Gunji, M.; Holland, M.; Thayne, I.; Eizenberg, M.; McIntyre, P. C., Titania/Alumina Bilayer Gate Insulators for InGaAs Metal-Oxide-Semiconductor Devices. Appl. Phys. Lett. 2011, 99, 232902. 30. Tell, B.; Nahory, R. E.; Leheny, R. F.; De Winter, J. C., Native Grown Plasma Oxides and Inversion Layers on InGaAs. Appl. Phys. Lett. 1981, 39, 744-746.


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Table of Content (TOC) Figure


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Temperature Dependent Border Trap Response ... - ACS Publications

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