Letter pubs.acs.org/NanoLett
Three-Terminal Nanoelectromechanical Field Effect Transistor with Abrupt Subthreshold Slope Ji-Hun Kim,† Zack C.Y. Chen,† Soonshin Kwon,‡ and Jie Xiang*,†,‡ †
Department of Electrical and Computer Engineering and ‡Materials Science and Engineering Program, University of California, San Diego, 9500 Gilman Dr., La Jolla, California 92093-0407, United States S Supporting Information *
ABSTRACT: We report the first experimental demonstration of a three-terminal nanoelectromechanical field effect transistor (NEMFET) with measurable subthreshold slope as small as 6 mV/dec at room temperature and a switching voltage window of under 2 V. The device operates by modulating drain current through a suspended nanowire channel via an insulated gate electrode, thus eliminating the need for a conducting moving electrode, and yields devices that reliably switch on/off for up to 130 cycles. Radiofrequency measurements have confirmed operation at 125 MHz. Our measurements and simulations suggest that the NEMFET design is scalable toward sub-1 V ultrahigh-frequency operation for future low-power computing systems. KEYWORDS: Nanoelectromechanical systems, mechanical switch, steep subthreshold slope device, semiconductor nanowires
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design was also explored and demonstrated, however the fourterminal device can only be switched in a flip-flop manner with no continuous FET operation available.21 Our NEMFET design, on the other hand, is based on the ultrashort length and ultrasmall mass of a suspended NW which exhibits mechanical resonance of ultrahigh-frequency (UHF) and beyond.22 Conduction through these semiconductor NW channels has also demonstrated extremely high performance as near-ballistic field effect transistors (FETs).23 Employing a thin NW as the conduction channel and utilizing its nanoelectromechanically movement-coupled surface potential, we will demonstrate near zero transistor SS and a high operational speed at the very high-frequency (VHF) range. Figure 1a illustrates the operation modes of a NEMFET.24 The NW channel is suspended above a gate electrode with an initial air gap thickness xgap and connected to source/drain (S/D) electrodes both mechanically and electrically. The NEMFET remains a three-terminal device with the S/D current being modulated by a gate electrode and requires no electrical contact between the gate and the moving NW channel. Due to hole gas accumulation in Ge-core/Si-shell interface,25 the channel is normally on at zero gate voltage (Vg). With Vg increasing, x reduces as the NW is pulled down by the electrostatic attraction force until a point when the electrostatic force can no longer be balanced by the mechanical restoration force of the bent NW, and it abruptly comes to be in contact with the gate. This mechanical motion is called ‘pull-in’, and the threshold gate voltage Vpi. Figure 1b shows a simulated displacement x vs Vg plot for a device with 1.3 μm long, 20 nm diameter p-doped
tatic power consumption has become one of the key limiting factors on the shrinkage of feature size in computer circuits.1 One major reason for high static power consumption is the off-state subthreshold leakage current of the transistor. At room temperature, the subthreshold slope (SS), the steepest transition rate for turning off the transistor, is thermodynamically limited to 60 mV/decade (kBT/q), a limit that is not scalable with reduced dimensions. Recently new switching and amplification mechanisms have been proposed with prototypical devices demonstrated to overcome such limit using band-to-band tunneling,2,3 impact ionization,4 or nanoelectromechanical (NEM) switches5−8 in order to achieve steep SS NEM switches utilize the mechanical degree of freedom and have recently garnered strong interest as alternative low-power computing solutions.5−8 Studies have demonstrated abrupt on/ off switching and steep SS with a movable gate or channel using materials such as metal,9−11 carbon nanotube,12,13 silicon carbide,14 Si nanowire (NW),15,16 or graphene.17,18 However these studies on NEM switches all suffer from a fundamental design limitation that their current on/off performances depend heavily on the nature of the two mechanical contacts which is still not well understood,19 resulting in poor conductivity and reliability,8 with switches failing within a few cycles. Here we report the first experimental demonstration of a three-terminal nanoelectromechanical field effect transistor (NEMFET). Previously, in microscale electromechanical systems (MEMS), three terminal suspended gate FETs have been configured using a traditional transistor with voltage from a movable gate electrode used to tune the current from source to drain. However the large-sized metal suspended gates7,20 have limited operational speed to several MHz due to their heavy moving mass. More recently an integrated NEMS-finFET © 2014 American Chemical Society
Received: February 18, 2014 Published: February 25, 2014 1687
dx.doi.org/10.1021/nl5006355 | Nano Lett. 2014, 14, 1687−1691
Nano Letters
Letter
virtually vertical turn-off of Id when Vg reaches Vpi (top arrow), resulting in zero SS. The 60 mV/dec SS of a conventional MOSFET is also plotted in comparison. The device is switchedon abruptly at Vpo = 0.64 V when Vg sweeps back to zero (bottom arrow). We choose Ge/Si core/shell NWs for experimental demonstration due to their high hole mobility and ease to make ohmic contacts to the hole carrier gas.23 Figure 1d is the schematic diagram of a NEMFET with suspended NW (see Figure S2 for fabrication details). We used multiple electronbeam lithography, metal deposition, and lift-off process steps to form the Au gate and S/D electrodes. A crucial challenge to a NEMS switch operation has been the precise fabrication of a nanometer-sized air gap between the movable parts in order for the device to pull-in at a reasonably small voltage.8 Here we use differential heights between the gate and S/D electrodes to control the initial air gap xgap which can be readily controlled to angstrom resolution by adjusting Au deposition time in an electron beam evaporator. The NW was grown in a low pressure chemical vapor deposition system (ET2000, CVD Corp.) and transferred to predefined electrode arrays by rubbing the growth wafer with the receiving substrate in a perpendicular direction. Mechanical support and electronic contacts are made by deposition of Ni S/D anchors. Finally, a conformal coating of HfO2 film was deposited via atomic layer deposition (ALD) as gate oxide and passivation covering the entire NW surface. The use of ALD HfO2 has several significant impacts on our device design. First, the HfO2 layer both on top of the Au gate electrode and bottom of the NW channel serves to reduce the final air gap thickness further. Figure 1e is an scanning electron microscope (SEM) image of an actual device with initial air gap thickness 55 nm, initial total NW diameter 25 nm, HfO2 thickness 10 nm, resulting in a final air gap thickness xgap of 35 nm. The use of ALD deposition therefore provides precise control over xgap and, in turn, over the Vpi and Vpo parameters.12 Second, the high break down voltage (>20 V) from the HfO2 layer eliminates gate leakage current after the NW is pulled down in contact with the gate electrode. Third, the entire NW channel is encapsulated with the thin ALD HfO2, increasing its total diameter d to 45 nm which in turn will increase its flexural resonant frequency (fo∝ d), thus improving its operational speed. The HfO2 layer also serves as passivation for our NEMFET channels (Figure S3). Figure 2 shows the first demonstration of an operating NEMFET. The main panel shows measured transfer characteristics Id−Vg of the device in Figure 1e. At Vg < 17.8 V, Id slightly decreases from a maximum on current of 2 μA with increase of Vg, consistent with a p-type accumulation mode transistor. The weak gate dependence of Id in the on state is expected and due to the existence of an air gap between the channel and gate electrode. At pull-in Vpi = 17.8 V, Id turns off abruptly; Id then turns back on at Vpo = 16.2 V during pull-out. While the pull-in transition has no measurable data point, the apparent SS is 11.7 mV/dec and only limited by our data sampling interval. Inset to Figure 2 shows another device of the same dimension with SS of 6 mV/dec. Importantly, the gate leakage current Ig stays at equipment measurement limit (
