Two-Mode MoS2 Filament Transistor with Extremely Low Sub

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Two-Mode MoS Filament Transistor with Extremely Low Sub-Threshold Swing and Record High On/Off Ratio Xue-Feng Wang, He Tian, Yanming Liu, Shuhong Shen, Zhaoyi Yan, Ningqin Deng, Yi Yang, and Tian-Ling Ren ACS Nano, Just Accepted Manuscript • DOI: 10.1021/acsnano.8b08876 • Publication Date (Web): 29 Jan 2019 Downloaded from http://pubs.acs.org on January 30, 2019

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Two-Mode MoS2 Filament Transistor with Extremely Low Sub-Threshold Swing and Record High On/Off Ratio Xue-Feng Wang1,†, He Tian1,† ,*, Yanming Liu,1 Shuhong Shen1, Zhaoyi Yan1, Ningqin Deng1, Yi Yang1*, and Tian-Ling Ren1* 1Institute

of Microelectronics and Beijing National Research Center for Information Science and

Technology (BNRist), Tsinghua University, Beijing 100084, China * Corresponding author. Email: [email protected], [email protected], tianhe88@tsi nghua.edu.cn. †These

authors contributed equally to this work.

ABSTRACT: With rapid development of integrated circuits, urge requirements for transistor with lower sub-threshold swing (SS) and better contact properties, are needed. To optimize the SS and contact issues, we propose a concept of molybdenum disulfide (MoS2) filament transistor with two-mode. We successfully fabricated the proposed devices in a wafer-scale. Mode I can enable the device with extremely low SS down to 2.26 mV/dec by switching contact filament between on and off while mode II can realize record high on/off ratio 2.6×109 by using filament as quasi-zero dimensional (quasi-0D) contact. Compared to conventional three dimensional (3D) contact, quasi0D contact using conductive filament improves the current density nearly 50 times. We also built spice model to simulate the electrical behaviors and successfully predict proposed transistor owns extremely low SS in mode I (using abrupt filament formation/rupture) and excellent quasi-0D contact in mode II. The two-mode MoS2 filament transistor can significant improve the SS and contact comparing to those of the state-of-the-art transistors, which has the great potential to boost the development of next generation mainstream transistors. KEYWORDS: molybdenum disulfide, filament transistor, sub-threshold swing, quasi0D contact, on/off ratio,

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Due to the number of transistors in a single chip is increasing exponentially according to the Moore’s law,1,2 the power consumption per transistor is required to decrease to maintain the total power consumption in an acceptable range. Making the transistors work in sub-thresthold region becomes an important solution on that issue. In order to achieve fast switching between ‘0’ and ‘1’ state in digital circuit. The sub-threshold swing (SS) is needed to be as low as possible. However, for traditional silicon-based transistor, the theoretical limit is around 60 mV/dec at room temperature.3,4 To break through the minimum limit of silicon and further reduce sub-threshold (SS) swing to meet requirements for low operation voltage and power consumption, many types of transistors with SS lower than 60 mV/dec have been explored, such as tunneling field effect transistor (FET),5,6 negative capacitance FET7,8 and back-gate graphene filament transistor.9 However, the SS of these transistors are not low enough despite they are all successfully below 60 mV/dec. For suspended-gate FET, although its SS can reduce to 2.16 mV/dec,10 it’s very hard to achieve circuit integration due to the suspended-gate structure. On the other hand, as the traps and defects exists at channel/electrode interface, the surface level will be generated at the contact, which will cause the Fermi level for metal to be pinned at certain surface level and impede the contact resistance from reduction by merely choosing metals with different work function.11 Therefore, how to improve contact and increase driving capability by other methods for scaling FET is becoming a tight problem. Among the published solutions, reducing contact dimension can be an effective method to improve contact properties, such as two dimensional (2D) contact,12 edge contact13,14 and one dimensional (1D) contact.15,16 2D contact (eg. Graphene-molybdenum disulfide (MoS2) contact) shows good contact improvement with ultrathin vertical height. However, it exists some problems currently. The contact obtained by mechanical exfoliation is not suitable to wafer-scale fabrication. Although high quality wafer-scale 2D materials such as graphene and MoS2 can be obtained by chemical vapor deposition (CVD), the multiple transfer of 2D thin films to form the 2D contact can introduce the contamination at the interface due to the polymethyl


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methacrylate (PMMA) residue. Despite 1D can effectively reduce contact resistance, the device with contact dimension lower than 1D to further optimize contact performance has rarely been investigated so far. Here, in order to explore an effective method to solve both lower SS and better contact issues, we propose a concept of two-mode MoS2 filament transistor. In mode I, by changing the direction of Vg sweep and polarity of Vd bias, the Ag conductive filament (CF) in HfOx layer between drain and channel can be formed and ruptured,17,18 which leads to extremely low SS during the moment of CF state change (Figure 1a). In mode II, the CF is first made to bridge across drain and channel by Vd sweep at fixed gate bias, then the quasi-0D contact can be formed as the cross section of filament is at nano-scale (Figure 1b).19 Using abrupt filament formation / rupture and filament contact, extremely low SS and quasi-zero dimensional (quasi-0D) contact can be obtained in mode I and mode II separately. By applying the different external electrical stimulation, this two modes can mutual switchable. The mode I means that the device operate between the on- and off- state of the filament. While the mode II means the device only operate at the on-state of the filament. So when the device is in mode II, it can either always work in mode II or switch to mode I. We have also fabricated wafer-scale MoS2 filament transistor and built the spice models to verify these two modes. The achievement of extremely low SS (2.26 mV/dec) in mode I and record high on/off ratio (2.6×109) not only validate the proposed two-mode operation concept but also exhibits huge potential on solving the contact and SS issue in transistor in next generation.

RESULTS AND DISCUSSION In order to experimentally achieve two-mode MoS2 filament transistor in a wafer-scale and own the potential to be compatible with standard complementary metal oxide semiconductor (CMOS) process. The MoS2 grown by chemical vapor deposition (CVD) is utilized. Figure 2a shows 2 inches wafer-scale devices with MoS2 zone 15 mm×15 mm, exhibiting the potential of mass production ability by CVD MoS2 thin film. The yellow zone contains 5×5 cells and each cell includes 5×5 devices unit (Figure 2b). The scanning electron microscope (SEM) image of single device is shown as Figure 2c with


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2 um channel length and 2 um electrode length both for Ag and Ti/Pt. The Raman spectra of MoS2 thin film is presented as Figure 2d. The E21 g (384.8 cm-1) and A1g (406.1 cm-1) feature peaks of MoS2 can be clearly observed. The difference between these two peak is over 20 cm-1, which indicates the MoS2 is few-layer MoS2.20,21 The thickness of MoS2 film is also measured by AFM with 1.4 nm, which implies the 2D channel is bilayer MoS2 thin film (Figure 2e and 2f).22 Besides, the photoluminescence (PL) spectra of MoS2 film used in proposed device is also measured (Figure S1), which is consistent with previous reported bilayer MoS2 thin film.23 According to the prediction by Figure 1, we first measured the proposed device operated in mode I, which focuses on low SS caused by the filament forming and rupture. From off to on state, we forwarded sweeping the gate voltage (1 V  3 V) with fixed drain bias (0.5 V), which can generate the positive electrical field in HfOx resistive switching layer between drain electrode and MoS2 channel to induce the filament forming. The transfer curve with extremely low SS 2.5 mV/dec can be observed (Figure 3a). At Ti/MoS2 contact side, when positive drain bias applied on Ti, band diagram (inset of Figure 3a) shows Ohmic contact at Ti/MoS2 interface,24 which indicates the Ti/MoS2 contact side plays a small role in lowering on current in positive drain bias. The phenomenon of Vt and SS modulated by drain bias is observed (Figure 3b). The Vt and SS are changing from 3.3 mV/dec to 2.26 mV/dec and 1.26 V to 1.03 V under the drain bias from 0.4 V to 0.6 V respectively (Figure 3c). It’s because different drain bias can affect the magnitude of electrical field in resistive switching layer. As the set voltage for control CBRAM is around 0.34 V (Figure S2), the drain bias lower to it (0.3 V) will not own the ability to form the CF across the drain electrode and MoS2 channel. For drain bias over the set voltage, before the filament formed, larger drain bias can generate higher electrical field, which make the filament grow faster25,26 (Equation (8) in supporting information) and achieve filament forming in relatively smaller gate voltage. Thus, the threshold voltage is lower when increasing drain bias. On the other hand, larger drain bias can also lead to higher on current after the filament formation, which makes the SS lower when the off current is nearly the same in these drain biases


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cases. On the other hand, the negative drain bias and reverse gate sweep were applied to rupture the filament and pull the device from on-state back to off-state. The SS can reach to 4.0 mV/dec despite the reduction of on current due to the existence of Schottky barrier (Figure 3d). Meanwhile, the SS and Vt for reverse sweep can also be modulated by drain bias. As the reset voltage for CBRAM part is relatively large (~ -0.90 V), drain bias lower than it cannot make the filament rupture (Vd = -0.8 V). Similar to the case for positive sweep, due to higher inner electrical field in HfOx resistive switching layer and larger drain current before CF rupture generated by larger drain bias, the increase of absolute value of Vd can also lead to the global tendency of lower SS and less Vg sweep range for CF broken. (Figure 3e), which causes the Vt right shift. (Figure 3f) The gate leakage both for forward and reverse sweep in mode I are measured (Figure S3). The leakage level is around pA and shows good gate leakage property of proposed device. Owing to the utilization of positive drain bias to make CF forming and negative drain bias to make CF rupture, the bipolar Vd operation in mode I is slight complex to achieve low SS for proposed device, but it can be improved in the future by using the CBRAM which can present the unipolar resistive switching behavior.27 Besides, the cycling test of mode I is conducted. The results of on current, off current and SS are presented and discussed in the part 4 of supporting information, which indicates during 50 cycling tests, the proposed device shows little vibration and good stability. Next, we explored electrical property of the fabricated device operated in mode II to verify the quasi-0D concept mentioned in the introduction part. It’s noticed that in this mode, the Ag atom conductive filament across the HfOx resistive switching layer as the quasi-0D contact is needed to be formed. Therefore, before the proposed device operates in mode II, the Id-Vd sweep was conducted to achieve CF forming (Figure S6). The device contains Ag/HfOx/MoS2 structure, which can be regarded as a conductive bridging random access memory (CBRAM). Typically, the cross-section of Ag atom CF is with diameter of sub-10 nm,19 which is extremely small comparing to the whole drain area. Therefore it can be regarded as “point” or quasi-0D contact between the channel and drain to some degree. Combined with bilayer MoS2 sizable bandgap, the record high 2.6×109 on/off ratio is achieved with relative small gate sweep voltage (-3


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V~11 V) and drain bias 6 V (Figure 4a). The utilization of buried-gate structure has a well control on gate leakage as well as lowers gate operation voltage. In order to compare with traditional Ag 3D contact, the control device without HfOx layer is fabricated. The fabrication process of control device is totally same with that of proposed device except for not depositing HfOx resistive switching layer. Under the same measurement condition, the quasi-0D Ag CF contact transistor shows the on current nearly 50 times increase (Figure 4b), exhibiting good contact property for quasi0D structure. It’s because for the quasi-0D contact, the existed CF will formulate the current flow path between the drain and channel and reduce the electrons from scattering in the inner layer and interlayer. Moreover, the proposed filament transistor owns good uniformity and stability. For 500 cycling Id-Vg sweeps (Figure 4c), the on/off ratio and on current (Vg = 9 V) are both distributed in a very stable region (Figure 4d), and over 109 on/off ratio can maintain very well. Stability for on current and off current is excellent, after 1350 h, both of them almost no change (Figure 4e). Besides, we also examine the device-to-device variation. After testing on 10 devices, an average of 1.5×109 on/off ratio can be obtained, showing good reliability of our proposed transistor (Figure 4f). The mode I and mode II are switchable to each other under the certain conditions. Once Ag filament is formed by sweeping Vd under large Vg bias (Figure S6), the proposed device can be operated in quasi-0D contact as mode II. On the contrary, if the initial state of the proposed device is mode II, when filament is ruptured and back to off state by external electrical stimulation such as negative large Vd sweep under high Vg bias, the proposed device can change to mode I. As the proposed concept of two-mode MoS2 filament transistor cannot be simulated by conventional transistor or other device models, we built the model for our proposed device. In order to comprehensively explore the mechanism of the proposed device in both two modes, the spice model is built. According to the structure of proposed device, three mainly parts are split. For MoS2 channel with buried-gate, the conventional MoS2 transistor model is used. Since the drain electrode utilized the metal of Ag and is adjacent to HfOx layer. The behavior of Ag migration and Ag CF forming


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and rupture across the HfOx layer induced by electrical field can be described with CBRAM model. The detailed description of this two models is in support information. In order to model the quasi-0D contact and 3D contact at the interface, the transmission line model28,29 is used. This model regards the total contact resistance Rc as resistive network which consists of two mainly part: (1) The vertical injected current (rv) and (2) MoS2 channel segmented resistance ct2D (Figure 5a).

When the number of segment

goes to infinity, the Rc can be approximately calculated by Equation (1).

Rc  lc LT ct2 D coth(

ct2 D LT

)

(1)

Where Rc is the contact resistance. lc is the total length of interface contact,

LT is the effectively transfer length of electrons, which is relevant to electron scattering.

ct2D is the resistivity of MoS2 film in contact part. For traditional 3D and quasi-0D contact, the lc and LT are different, which the value of lc is thousands time of the later’s. Figure 5b shows the simulation result extracted from Equation (1) comparing with the experimental data, indicating the quasi-0D contact can effectively reduce the electrons scattering and in turn greatly reduce the contact resistance. In the simulation of mode I, the initial filament length in HfOx resistive switching layer is 0 and for simplification, the diameter of CF cross-section is fixed (sub-10 nm) during the Vg sweep. While in the simulation of mode II, as the filament has already been formed, the length of it keeps constant equal to the thickness of HfOx layer throughout the whole simulation process. Figure 5c and 5d show the simulation result for the proposed transistor in mode I and mode II respectively by using spice model discussed above. For mode I, the SS can as low as 1.09 mV/dec theoretically (Figure 5c), which is much smaller than the experimental result (2.26 mV/dec) and exhibits huge space of experimental SS reduction in the future. The suddenly change of electrical potential at HfOx/MoS2 interface (Figure S9) during the Vg sweep reflects the process of filament forming in CBRAM part, which is the direct reason for abrupt change of channel current. For mode II, this model shows the “on” drain current of quasi-0D contact can increase


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nearly 56 times than that of traditional 3D contact, which shows good consistence between theoretical prediction and actual device measurement. The whole simulation process is shown in Figure S10. We analyze the structure of proposed device, extract three sub-models according to the corresponding structures and verify the models by comparing to the experimental results. As the key to achieve low SS in mode I and quasi-0D contact in mode II is resistive switching layer (7 nm HfOx), other p-type 2D materials such as WSe230 replacing MoS2 in our device structure, also owns the ability to achieve both modes from the spice simulation (Part 7.4 in supporting information). In order to explore the dynamic migration of Ag atoms during the proposed device under the sweep of voltage, the Monte Carlo simulation is used, which the Ag oxidation, cathode electron emission and migration of cations and electrons are considered, the concrete step is described in support information in detail. Figure 5e, 5f show the Ag atom distribution and electrical field amplitude of the resistive switching layer in proposed device under the filament growing state (Figure 5e) and the filament forming state (Figure 5f). From the simulation we can see that, if the voltage applied across the resistive switching layer, the Ag atom in Ag electrode (purple part) anode will be oxidized (green point) and move to the cathode under the effect of electrical field. When the Ag ions reach the cathode, they will capture the electrons from the cathode and be reduced to Ag atom (yellow part). It’s noticed that the top of Ag atom from cathode will owns the relatively higher electrical field amplitude (Figure 5e), which makes the Ag ion from anode more likely to be reduced on the top of those from cathode and filament shape of Ag in resistive switching layer can be generation after multi-iteration. If the Ag from the anode and cathode touched, the Ag CF bridge across the resistive switching layer can be formed (Figure 5f) and the electrical filed amplitude along the formed filament will be dropped down, which from another view proves the contact between the drain and channel is quasi-0D contact (filament contact). In order to demonstrate good performance of our device in mode I and mode II respectively, we compared other published devices with our work. For our device in low SS mode, compared to other kinds of steep-slope transistors, the abrupt state change of filament in HfOx layer makes the proposed device own lower SS than previous NC


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FET and tunneling FET (Table I).9,10,31-33 Moreover, the utilization of buried-gate structure allows the thinner gate dielectric layer to be deposited, which can result in much smaller gate voltage and lower SS comparing with back-gate graphene filament transistor. Meanwhile, most of published MoS2 transistors are with contact dimension in 3D or 2D contact, which the current on/off ratio is not optimized. For the proposed quasi-0D contact structure, combined with buried gate, it owns recorded on/off ratio with relatively small Vg sweep (Table II),34-41 exhibiting excellent contact properties when the dimension of contact reduced. Besides, as the bandgap of bilayer MoS2 (~1.52 eV) is smaller than monolayer (~1.83 eV),42 if monolayer MoS2 is used in our proposed concept, even higher current cut-off property can be achieved, which owns the potential to make the on/off ratio further improved.

CONCLUSIONS In summary, we propose the concept of two-mode (low SS and quasi-0D contact) filament MoS2 transistor. By comprehensively utilizing MoS2 transistor compact model, contact resistance transmission line model and CBRAM compact model to build and simulate I-V behaviors of proposed transistor, the theoretical extremely low SS (down to 1.09 mV/dec) in mode I and contact improvement by quasi-0D structure (~56×) in mode II can be well predicted. In experiment, the devices is able to be fabricated in a large scale and owns extremely low SS as 2.26 mV/dec in mode I and recorded high on/off ratio over 2.6×109 in mode II, which can well verify the proposed two-mode filament MoS2 transistor concept and performance prediction from the simulation. Over 50 times contact improvement is achieved. The proposed transistor provides promising solution on both lowering SS and improving contact property and owns huge potential to become mainstream transistor in next generation.

METHODS Device fabrication. The device was fabricated on the Si substrate with 300 nm SiO2. The CVD MoS2 was purchased from 6Carbon Technology Corporation, which was synthesized on sapphire substrate by chemical vapor deposition. The 99.999% purity


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MoO3 and 99.999% purity S were placed in two separate temperature zone of the tube with the growth temperature of 650 ̊C for MoO3 and 180 ̊C for S under the Ar atmosphere. First lithography and 14 nm thickness Pt deposition were conducted to finish the gate electrode fabrication. Then 20 nm thickness HfOx was deposited to use as gate dielectrics by atomic layer deposition (ALD). The precursors are Tetrakis (ethylmethylamido) hafnium (IV) [TEMAH; Hf(NCH3C2H5)4] and water with 200 ℃ reaction temperature and total cycle number is 200. Wet transfer method same as the previous reported43 was used to make MoS2 transferred above the dielectric layer and MoS2 pattened by plasma etching was followed. Source electrode was obtained by third lithography and 10 nm/ 20 nm Ti/Pt deposition with magnetron sputtering. After that, 7 nm HfOx was deposited by ALD with the same reaction parameters as gate dielectrics deposition except cycle number is 70. Then the forth lithography and magnetron sputtering were utilized to fabricate 35 nm Ag electrode. Finally, the fifth lithography and the window etching above the gate pad were used to remove the unwanted HfOx. Raman and PL measurement. The Raman and PL spectrum were performed by LabRAM HR Evolution with 532 nm laser with the 25% filter. The acquisition time for Raman was 20 s and PL was 10 s. SEM image. The SEM imaged was captured by QUANTA FEG 450 with the 2.5 um laser spot and 10 kV high voltage. AFM measurement. The AFM images were captured using a Bruker DimensionIcon FastScan system and analyzed by NanoScopeAnalysis software. Electrical Measurements. All the electrical characterizations were carried out using Agilent B1500A parameter analyzer. The measurement was performed at room temperature under atmospheric pressure.

ASSOCIATED CONTENT The authors declare no competing financial interest. Supporting Information. This material is available free of charge via the Internet at http://pubs.acs.org. Additional figures S1-S12 and model building for MoS2 filament transistor.


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AUTHOR INFORMATION Corresponding Author *Email: [email protected] *Email: [email protected] *Email: [email protected] Author Contributions †X.-F.

Wang and H. Tian contributed equally to the work.

ACKNOWLEDGMENT This work was supported by National Key R&D Program (2016YFA0200400), National Basic Research Program (2015CB352101) of China, National Natural Science Foundation (61874065, 51861145202, 61574083, 61434001) and Beijing Natural Science Foundation (4184091). He Tian thanks for the support from Young Elite Scientists Sponsorship Program by CAST (2018QNRC001). The authors are also thankful for the support of the Start-up Funding from Tsinghua University (533306001), Research Fund from Beijing Innovation Center for Future Chip, the Independent Research Program of Tsinghua University (2014Z01006) and Shenzhen Science and Technology Program (JCYJ20150831192224146).

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Material. Science 2013, 342, 614-617. 15. Qi, P.; Javey, A.; Rolandi, M.; Wang, Q.; Yenilmez, E.; Dai, H., Miniature Organic Transistors with Carbon Nanotubes as Quasi-One-Dimensional Electrodes. J. Am. Chem. Soc. 2004, 126, 11774-11775. 16. Léonard, F.; Talin, A. A., Electrical Contacts to One-and Two-Dimensional Nanomaterials. Nat. Nanotechnol. 2011, 6, 773. 17. Kund, M.; Beitel, G.; Pinnow, C.-U.; Rohr, T.; Schumann, J.; Symanczyk, R.; Ufert, K.; Muller, G. In Conductive Bridging RAM (CBRAM): an Emerging Non-Volatile Memory Technology Scalable to Sub 20 nm, 2005 IEEE Int. Electron Devices Meet., Dec 5-7, 2005; 2005; pp 754-757. 18. Ielmini, D. In Filamentary-Switching Model in RRAM for Time, Energy and Scaling Projections, 2011 IEEE Int. Electron Devices Meet., Dec 5−7, 2011; 2011; pp 17.2. 1-17.2. 4. 19. Wang, Z.; Joshi, S.; Savel’ev, S. E.; Jiang, H.; Midya, R.; Lin, P.; Hu, M.; Ge, N.; Strachan, J. P.; Li, Z., Memristors with Diffusive Dynamics as Synaptic Emulators for Neuromorphic Computing. Nat. Mater. 2017, 16, 101. 20. Li, H.; Zhang, Q.; Yap, C. C. R.; Tay, B. K.; Edwin, T. H. T.; Olivier, A.; Baillargeat, D., From Bulk to Monolayer MoS2: Evolution of Raman Scattering. Adv. Func. Mater. 2012, 22, 1385-1390. 21. Lee, C.; Yan, H.; Brus, L. E.; Heinz, T. F.; Hone, J.; Ryu, S., Anomalous Lattice Vibrations of Single-and Few-Layer MoS2. ACS Nano 2010, 4, 2695-2700. 22. Wang, H.; Yu, L.; Lee, Y.-H.; Shi, Y.; Hsu, A.; Chin, M. L.; Li, L.-J.; Dubey, M.; Kong, J.; Palacios, T., Integrated Circuits Based on Bilayer MoS2 Transistors. Nano Lett. 2012, 12, 4674-4680. 23. Wang, X.; Feng, H.; Wu, Y.; Jiao, L., Controlled Synthesis of Highly Crystalline MoS2 Flakes by Chemical Vapor Deposition. J. Am. Chem. Soc. 2013, 135, 5304-5307. 24. Yuan, H.; Cheng, G.; You, L.; Li, H.; Zhu, H.; Li, W.; Kopanski, J. J.; Obeng, Y. S.; Hight Walker, A. R.; Gundlach, D. J., Influence of Metal–MoS2 Interface on MoS2 Transistor Performance: Comparison of Ag and Ti Contacts. ACS Appl. Mater. Inter. 2015, 7, 1180-1187.


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25. Lin, S.; Zhao, L.; Zhang, J.; Wu, H.; Wang, Y.; Qian, H.; Yu, Z. In Electrochemical Simulation of Filament Growth and Dissolution in Conductive-Bridging RAM (CBRAM) with Cylindrical Coordinates, 2012 IEEE Int. Electron Devices Meet., Dec 10-13, 2012; 2012; pp 26.3. 1-26.3. 4. 26. Yu, S.; Wong, H.-S. P., Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM). IEEE T. Electron Dev. 2011, 58, 1352-1360. 27. Liu, T.; Verma, M.; Kang, Y.; Orlowski, M. K., Coexistence of Bipolar and Unipolar Switching of Cu and Oxygen Vacancy Nanofilaments in Cu/TaOx/Pt Resistive Devices. ECS Solid State Lett. 2012, 1, Q11-Q13. 28. Allain, A.; Kang, J.; Banerjee, K.; Kis, A., Electrical Contacts to Two-Dimensional Semiconductors. Nat. Mater. 2015, 14, 1195. 29. Berger, H., Models for Contacts to Planar Devices. Solid-State Electron. 1972, 15, 145-158. 30. Zhou, C.; Zhao, Y.; Raju, S.; Wang, Y.; Lin, Z.; Chan, M.; Chai, Y., Carrier Type Control of WSe2 Field-Effect Transistors by Thickness Modulation and MoO3 Layer Doping. Adv. Func. Mater. 2016, 26, 4223-4230. 31. Ionescu, A. M.; Riel, H., Tunnel Field-Effect Transistors as Energy-Efficient Electronic Switches. Nature 2011, 479, 329. 32. Si, M.; Su, C.-J.; Jiang, C.; Conrad, N. J.; Zhou, H.; Maize, K. D.; Qiu, G.; Wu, C.T.; Shakouri, A.; Alam, M. A., Steep-Slope Hysteresis-Free Negative Capacitance MoS2 Transistors. Nat. Nanotechnol. 2018, 13, 24. 33. McGuire, F. A.; Lin, Y.-C.; Price, K.; Rayner, G. B.; Khandelwal, S.; Salahuddin, S.; Franklin, A. D., Sustained Sub - 60 mV/decade Switching via the Negative Capacitance Effect in MoS2 Transistors. Nano Lett. 2017, 17, 4801-4806. 34. Radisavljevic, B.; Radenovic, A.; Brivio, J.; Giacometti, i. V.; Kis, A., Single-Layer MoS2 Transistors. Nat. Nanotechnol. 2011, 6, 147. 35. Wu, W.; De, D.; Chang, S.-C.; Wang, Y.; Peng, H.; Bao, J.; Pei, S.-S., High Mobility and High On/Off Ratio Field-Effect Transistors Based on Chemical Vapor Deposited Single-Crystal MoS2 Grains. Appl. Phys. Lett. 2013, 102, 142106. 36. Yoon, J.; Park, W.; Bae, G. Y.; Kim, Y.; Jang, H. S.; Hyun, Y.; Lim, S. K.; Kahng,


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Y. H.; Hong, W. K.; Lee, B. H., Highly Flexible and Transparent Multilayer MoS2 Transistors with Graphene Electrodes. Small 2013, 9, 3295-3300. 37. Lee, G.-H.; Yu, Y.-J.; Cui, X.; Petrone, N.; Lee, C.-H.; Choi, M. S.; Lee, D.-Y.; Lee, C.; Yoo, W. J.; Watanabe, K., Flexible and Transparent MoS2 Field-Effect Transistors on Hexagonal Boron Nitride-Graphene Heterostructures. ACS Nano 2013, 7, 7931-7936. 38. Illarionov, Y. Y.; Smithe, K. K.; Waltl, M.; Knobloch, T.; Pop, E.; Grasser, T., Improved Hysteresis and Reliability of MoS2 FETs with High-Quality CVD Growth and Al2O3 Encapsulation. IEEE Electron Device Lett. 2017. 39. Xie, L.; Liao, M.; Wang, S.; Yu, H.; Du, L.; Tang, J.; Zhao, J.; Zhang, J.; Chen, P.; Lu, X., Graphene-Contacted Ultrashort Channel Monolayer MoS2 Transistors. Adv. Mater. 2017, 29, 1702522. 40. Yang, Z.; Liu, X.; Zou, X.; Wang, J.; Ma, C.; Jiang, C.; Ho, J. C.; Pan, C.; Xiao, X.; Xiong, J., Performance Limits of the Self-Aligned Nanowire Top-Gated MoS2 Transistors. Adv. Func. Mater. 2017, 27, 1602250. 41. Zhu, Y.; Li, Y.; Arefe, G.; Burke, R. A.; Tan, C.; Hao, Y.; Liu, X.; Liu, X.; Yoo, W. J.; Dubey, M., Monolayer Molybdenum Disulfide Transistors with Single-AtomThick Gates. Nano Lett. 2018. 42. Chu, T.; Ilatikhameneh, H.; Klimeck, G.; Rahman, R.; Chen, Z., Electrically Tunable Bandgaps in Bilayer MoS2. Nano Lett. 2015, 15, 8000-8007. 43. Wang, X. F.; Tian, H.; Zhao, H. M.; Zhang, T. Y.; Mao, W. Q.; Qiao, Y. C.; Pang, Y.; Li, Y. X.; Yang, Y.; Ren, T. L., Interface Engineering with MoS2-Pd Nanoparticles Hybrid Structure for a Low Voltage Resistive Switching Memory. Small 2018, 14, 1702525.


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Figure 1. The concept of two-mode MoS2 filament transistor: (a) low SS mode (Mode I), (b) quasi-0D contact mode (Mode II). In mode I, extremely low SS is achieved by the conductive filament (CF) forming and rupture in resistive switching layer. In mode II, once the CF formed, the quasi-0D contact between the drain and channel is generated, which can improve the current on-off ratio compared to 3D contact.


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ACS Nano

Figure 2. The characteristics of the MoS2 thin film and proposed device: (a) The optical image of devices array in a wafer scale. (b) The SEM image of single 5x5 devices array. (c) The SEM of single device in 10 um scale. (d). The Raman spectra of MoS2 thin film. The difference between two peaks is over 20, indicating the MoS2 is multilayer. (e) The AFM image of interface between MoS2 thin film and substrate. (f) The height along the yellow dash line in (e), the step at the interface is around 1.4 nm, which shows the bilayer of MoS2.


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Figure 3. The electrical measurement of the proposed device in mode I. (a) The forward sweep of Id-Vg curve with positive drain bias 0.5 V. Inset is the band structure along the channel and contact with positive Vd. (b) The forward Vg sweep of Id-Vg curve in mode I under different drain biases. (c) The SS and Vt changing with drain bias for Vg positive sweep, both of them are deceased when Vd increasing. (d) The reverse sweep of Id-Vg curve with negative drain bias -1 V. Inset is the channel band structure with negative Vd. (e) The reverse Vg sweep of Id-Vg curve in mode I under different drain biases. (f) The SS and Vt changing with drain bias for Vg reverse sweep. The global tendency for them is decreased when absolute value of Vd increased.


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ACS Nano

Figure 4. The electrical properties of proposed device in mode II with Quasi-0D contact. (a). The Id-Vg sweep and gate leakage after the quasi-0D contact formed. (b) The on current comparison between the traditional 3D contact and quasi-0D contact. (c) The cycle Id-Vg test of single proposed quasi-0D contact. (d) The accumulated probability of current on/off ratio and on current, which indicates good uniformity during the cycle test. (e) The retention time of on current and off current in quasi-0D contact. (f) Current on/off ratio in 10 devices.


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ACS Nano

Figure 5. The model and simulation of proposed devices both in mode I and mode II. (a) The transmission line model of quasi-0D contact. (b) The contact resistance versus contact length both in simulation (red line) and experiments (blue star). (c) The simulation result of Id-Vg curve in low SS mode under Vd bias of 0.4 V, 0.45 V and 0.6 V, which is corresponding to theoretically SS of 1.17 mV/dec, 1.13 mV/dec and 1.17 mV/dec. (d) The simulation result of Id-Vg transfer curve with quasi-0D contact and traditional 3D contact, which shows the quasi-0D contact can improve contact property near 50 times. (e) The Monte Carlo simulation of Ag atom distribution and corresponding electrical field distribution in the filament growing state. (f) The Monte Carlo simulation of Ag atom distribution and corresponding electrical field distribution in the filament formed state.


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Table I. The comparison between proposed transistor in mode I and other steep slope transistors. Device Type

Mechanism

Tunneling FET

Band-to-band tunneling

Negative

Ferroelectricity of

Capacitance FET

Hafnium zirconium oxide

Negative

Ferroelectricity of

Capacitance FET

Hafnium zirconium oxide

Suspended-Gate

Electrostatic attraction by

MOSFET

suspended gate

Bilayer Graphene

Filament forming/rupture

filament FET

by gate

Buried-gate MoS2

Filament forming/rupture

filament FET

by gate

Subthreshold

Vt

On/Off

Swing(SS)

(ABS*)

ratio

42 mV/dec

~0.5 V - 1.0 V

~105

Nature31

52.3 mV /dec

~0.6 V - 1.0 V

~106

Nat. Nanotechol.32

6.07 mV/dec

~10.5 V

~105

Nano Lett.33

2.16 mV/dec

~9 V

~103

IEDM10

4.6 mV/dec

~5.5 V - 13.8 V

2.26 mV/dec

1.03 V ~ 1.25 V

Note: *: ABS means the absolute value. **: This on/off ratio is extracted from Figure 3a.


~103 106 ~106**

Reference

Adv. Electron. Mater.9

This work

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Table II. The comparison between proposed transistor in mode II and other MoS2 transistors. MoS2 type

Contact dimension and materials

Exfoliated

3D contact

(1L)

(Au)

CVD

3D contact

(2L)

(Cr/Pd)

Exfoliated

2D contact

(ML)

(Graphene)

Exfoliated

3D contact

(1L)

(Ti/Au)

CVD

3D contact

(1L)

(Au)

Exfoliated

2D contact

(1L)

(Graphene)

Exfoliated

3D contact

(ML)

(Ni/Au)

CVD

3D contact

(1L)

(Ni/Au)

CVD

Quasi-0D contact

(2L)

(Ag CF)

Vg sweep range

On/Off Ratio

Reference

-4 V ~ 4 V

~108

Nat. Nanotechol.34

-100 V ~ 100 V

~ 108

Appl. Phys. Lett.35

-40 V ~ 20 V

~ 5×104

Small36

-2 V ~ 5 V

~ 105

ACS Nano37

-12 V ~ 15 V

~ 1×109

IEEE EDL38

-2 V ~ 2 V

~ 106 – 108

Adv. Mater.39

-3 V ~ 1 V

~ 5×108

Adv. Func. Mater.40

0.3 V ~ 1.2 V

~ 107

Nano Lett.41

-2 V ~ 11 V

2.6×109

This work


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For table of contents only 78x39mm (300 x 300 DPI)


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Two-Mode MoS2 Filament Transistor with Extremely Low Sub

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