Vertical Silicon Nanowire Thermoelectric Modules with Enhanced

Subscriber access provided by Iowa State University | Library

Communication

Vertical silicon nanowire thermoelectric modules with enhanced thermoelectric properties Seungho Lee, Kihyun Kim, Deok-Hong Kang, Meyya Meyyappan, and Chang-Ki Baek Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.8b03822 • Publication Date (Web): 13 Jan 2019 Downloaded from http://pubs.acs.org on January 13, 2019

Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.

is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.

Page 1 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

Vertical silicon nanowire thermoelectric modules with enhanced thermoelectric properties Seungho Leea, Kihyun Kimb, *, Deok-Hong Kangc, M. Meyyappand and Chang-Ki Baeka, b a

Department of Electrical Engineering, Pohang University of Science and Technology

(POSTECH), Pohang 37673, Republic of Korea b

Department of Creative IT Engineering and Future IT Innovation Lab., Pohang University of

Science and Technology (POSTECH), Pohang 37673, Republic of Korea c

Research Institute of Industry Science & Technology (RIST), Pohang 37673, Republic of

Korea d

NASA Ames Research Center, Moffett Field, California 94035, USA

Abstract Thermoelectric modules based on silicon nanowires (Si-NWs) have recently attracted significant attention as they show improved thermoelectric efficiency due to a decrease in thermal conductivity. Here, we adopt a top-down fabrication method to dramatically reduce the thermal conductivity of vertical Si-NWs. The thermal conductivity of vertical Si-NW is significantly suppressed with increasing surface roughness, decreasing diameter, and increasing doping concentration. This large suppression is caused by enhanced phonon scattering, which depends on phonon wavelength. The boron and phosphorus doped rough SiNWs with diameter of 200 nm and surface roughness of 6.88 nm show the lowest thermal conductivity of 10.1 and 14.8 W∙m-1∙K-1, respectively, which are 3.4 and 2.4 fold lower than that of smooth intrinsic nanowire and 14.8 and 10.1 fold lower than that of bulk silicon. A thermoelectric module was fabricated using these doped rough Si-NW array and its thermoelectric performance is compared with previously reported Si-NW modules. The fabricated module exhibits excellent performance with an open circuit voltage of 216.8 mV·cm-2 and a maximum power of 3.74 W·cm-2 under a temperature difference of 180 K, the highest reported for Si-NW thermoelectric modules.

ACS Paragon Plus Environment

1

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 2 of 36

KEYWORDS: Vertical silicon nanowire, Top-down technique, Phonon scattering, thermal conductivity, surface roughness, thermoelectric module

* Corresponding Author: [email protected] Almost 90% of the world’s energy is generated by fossil fuel combustion with an efficiency of 30-40% and the rest wasted into heat. As the world energy consumption continues to rise, thermoelectric energy harvesting, i.e. electricity generation from waste heat, has attracted much attention as a green technology1,2. Bulk Bi2Te3 and its alloys are the most widely used commercial thermoelectric materials due to their high conversion efficiency. However, they are not suitable for large-scale energy recovery applications due to the high material cost, insufficient supply and a manufacturing method that is not suitable for mass production3-6. In contrast, silicon has the advantages of low material cost, abundant earth reserves and matured manufacturing technology for mass production; nevertheless, it has not been used as a thermoelectric material due to its high thermal conductivity7,8. Thermal conductivity of a thermoelectric material is an important factor determining the conversion efficiency, as seen from the dimensionless figure-of-merit (ZT=S2σT/κ), where S is the Seebeck coefficient, σ is the


2

Page 3 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

electrical conductivity, κ is the thermal conductivity and T is the absolute temperature, respectively. The conversion efficiency increases with decreasing thermal conductivity. Silicon nanowires (Si-NWs) have recently attracted much attention for chemical and biological sensors9, photovoltaic cells10-11 and many other applications due to their small cross sectional area, large surface-to-volume ratio and attractive transport properties. They have also been considered as a strong candidate to enhance the conversion efficiency of thermoelectric modules by reducing the thermal conductivity while maintaining the electrical properties such as the Seebeck coefficient and the electrical conductivity of the bulk Si12,13. Most thermal energy within silicon is transported by the lattice vibration rather than by electrons and holes; thus the thermal conductivity of the Si-NWs is effectively suppressed by phonon scattering. Several studies have achieved thermal conductivity suppression by tuning phonon scattering through the control of diameter, doping concentration and surface roughness of the Si-NWs grown by the vapor-liquid-solid (VLS) method13-16 or by electroless etching (EE)12,17-19. The VLS-grown nanowires with a diameter of several tens of nanometers show about 100 times better ZT than bulk Si. When the NW cross-section shrinks, the thermal conductivity decreases due to phononboundary scattering. The VLS method can easily produce NWs with smaller diameter but it is not suitable for mass production since an additional transfer process is required to fabricate the


3

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 4 of 36

thermoelectric device. Si-NWs with rough surface, produced by the EE method, can have further reduced thermal conductivity compared to VLS grown Si-NWs12,20. The surface roughness plays a critical role to suppress thermal conductivity by generating additional phonon scattering12,

20-22.

As the concentration of impurities increases, the thermal conductivity

decreases and the electrical conductivity is enhanced. However, the Seebeck coefficient degrades at extremely high doping concentration. Therefore, the optimal doping concentration, not too high doping concentration, can improve the performance of Si-NW thermoelectric modules. Increasing the doping concentration of Si-NW or the reaction time significantly in the EE process in order to reduce the thermal conductivity can degrade the electrical conductivity and prevent the formation of reproducible electrical contacts12,23-25. In contrast to the shortcomings of the VLS and EE techniques, the top-down method, that is fully compatible with the current state-of-the art CMOS technology, can solve the above problems. A well-developed top-down technique provides excellent design flexibility and mass production capability, while allowing precise control of the doping concentration. Therefore, high performance Si-NW thermoelectric modules can be manufactured by alternately arranging p and n doped Si-NW arrays with high density in a chip.


4

Page 5 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

In this paper, we have used a top-down technique to suppress the thermal conductivity of vertical Si-NWs, additionally aided by a theoretical investigation. Specifically, the thermal conductivity of vertical Si-NW was controlled for the first time by adjusting the surface roughness using dry etching, which has advantages of high reproducibility and mass production. In addition, the diameter and doping concentration were also controlled to further reduce the thermal conductivity. The NW thermal conductivity was measured using differential 3ω method and the effect of diameter, surface roughness, doping concentration and temperature was theoretically analyzed through phonon-Boltzmann transport equation and various phonon scattering processes. Finally, a thermoelectric module was fabricated using p- type and n-type vertical Si-NW legs connected in series and its power generation performance (open circuit voltage and power) was assessed.

Effect of diameter and surface roughness on thermal conductivity. Vertical Si-NWs with different diameters and surface roughness were prepared using the topdown method to investigate the thermal conductivity. The surface roughness was controlled by tuning the pressure and gas flow in the inductively coupled plasma reactive ion etching (ICPRIE) reactor. Figure 1 shows the scanning electron microscope (SEM) and high-resolution transmission electron microscope (HR-TEM) images of the 200 nm diameter vertical Si-NWs


5

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 6 of 36

with three different surface morphologies. The SEM images for the 350 nm diameter samples are included in supplementary information (Fig. S1). Two parameters were defined to quantify the surface roughness. One is the root-mean-square of the roughness (η) and the other is the average distance between two rough features (L, i.e. correlation length). The vertical Si-NWs fabricated by three different etching conditions here have η of 2.28, 4.29, and 6.88 nm, respectively, but they show the similar L value of about 14.3 nm, as seen in the TEM images (Fig. 1(b)–(d)). This confirms the successful control of the NW surface roughness using the topdown technique. We measured the thermal conductivity of six different NW samples (two diameters and three surface roughness values) using differential 3ω method. The experimental set-up for measuring the thermal conductivity is illustrated in Fig. S2. First, we measured the thermal conductivity of various film samples (SiO2, spin-on-glass (SOG), and polyimide (PI)) and compared these values with reported data in the literature to confirm the accuracy of our measurement method. The measured values are 1.34, 0.38 and 0.21 W ∙ m-1 ∙ K-1 for SiO2, SOG and PI, respectively, which are consistent with previous reports26,29 (Fig. S3) and confirm the high accuracy and reliability of our measurement method. The thermal conductivity of a vertical Si-NW (𝑘𝑆𝑖𝑁𝑊 ) can be calculated using28


6

Page 7 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

𝑘𝑆𝑖𝑁𝑊 = (𝑘𝑐𝑜𝑚𝑝 ― (1 ― 𝑥) ∙ 𝑘𝑆𝑂𝐺) ∙ 𝑥 ―1

(1)

where 𝑥 is the area density of the Si-NW, 𝑘𝑐𝑜𝑚𝑝 is the thermal conductivity of the composite sample, and 𝑘𝑆𝑂𝐺 is the thermal conductivity of the SOG. The composite sample consists of the vertical Si-NWs and the SOG film surrounding the nanowires. The areal density of the vertical Si-NWs was obtained from the top-view SEM image (inset of Fig. 1 (a) and Fig. S1 (b)). Figure 2 (a) and (b) show the measured thermal conductivity of various vertical Si-NWs with different diameters and surface roughness values. Previously reported data for the VLS-grown Si-NWs are also added in Fig. 2 (a). The thermal conductivity is suppressed with decreasing diameter or increasing roughness; for example, it decreases by about 25.5% for a rough surface (η = 6.88 nm) compared with a NW with smooth surface (η = 2.28 nm). In addition, when the diameter shrinks from 350 nm to 200 nm, the thermal conductivity decreases by 27.5 %. Especially, the vertical Si-NW with diameter of 200 nm and η of 6.88 nm has lower thermal conductivity than that of VLS-grown Si-NWs with diameter of 115 nm. That is, a vertical rough Si-NW fabricated by our etching recipe can have smaller thermal conductivity than the VLS-grown case even though the diameter is larger.


7

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 8 of 36

The effect of diameter and surface roughness on phonon scattering can be analyzed using phonon-Boltzmann equation, boundary scattering rate ( τ b-1) and Umklapp scattering rate ( τ u-1). The scattering rate is given by: τ-1 = τb-1 + τu-1. The boundary scattering rate is defined as21,30,31

𝜏𝑏―1

𝑣𝑏

= 𝐷𝑁𝑊(1 ― 𝑝),

𝑝=𝑒

―

16𝜋2𝜂2 cos2 𝜃 𝜆2

(2)

where 𝑣𝑏 is the sound velocity, 𝐷𝑁𝑊 is nanowire diameter, 𝑝 is the specular parameter, λ is the wavelength and θ is the incident angle of the phonon at the surface. The parameter p represents the fraction of specularly scattered phonons from the surface with a value generally between 0 and 1. The purely specular scattering (p = 1) is an ideal case in which the phonons are specularly reflected at the surface without loss of momentum. When p = 1, the boundary scattering does not affect the thermal conductivity due to τb-1 = 0. The surface is very rough for

p = 0 and phonon scattering is purely diffusive32. Therefore, p = 0 significantly suppresses the thermal conductivity. The value of p can be calculated using eq. (2) and the nanowire surface roughness (η) measured by TEM, assuming that θ = 0. Figure S4 shows p as a function of the reciprocal of phonon wavelength for the vertical Si-NWs with η = 2.28, 4.29, and 6.88. It can be seen that p decreases with increasing surface roughness over the entire wavenumber range. Since p is dependent on the phonon wavelength as well as surface roughness (Fig. S4 (a)), we define a phonon wavelength-independent p (called p*) and use this parameter for intuitively evaluating the effect of surface roughness on the thermal conductivity of the nanowire. The p* is defined as the area of the p normalized by the area assuming p = 1


8

Page 9 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

within cut-off frequency calculated by Mingo31,43, as shown in Fig. S4 (b). The parameter p* depends on the surface roughness of the nanowire but is independent of the phonon wavelength. The vertical Si-NWs with η of 2.28, 4.29, and 6.88 nm have p* of 0.41, 0.30, and 0.03, respectively. In Fig. 2 (a) and (b), the vertical Si-NW with η of 6.88 nm has the lowest thermal conductivity at the same diameter because p* is close to 0. The solid line indicates the thermal conductivity calculated by substituting p* instead of p in eq. (2). The solid lines are in good agreement with the measured thermal conductivities, thus confirming the validity of our calculation. By using p* instead of p in calculating thermal conductivity, the thermal conductivity of rough Si-NW according to the surface roughness can be easily predicted. Using the scattering model with p, we can calculate the phonon mean free path and cumulative thermal conductivity at room temperature shown in Fig. 2 (c) and (d) as a function of reciprocal of phonon wavelength. As the surface becomes rougher, the wavelength of the core phonons carrying heat (corresponding to 20-80% of the cumulative thermal conductivity) shifts to shorter phonon wavelength, and the mean free path of phonons with long wavelength are significantly reduced. The surface roughness dominantly reduces the mean free path of phonons with larger wavelength, resulting in suppression of thermal conductivity. The surface roughness causes additional phonon scattering, which can reduce the mean free path, for phonons with larger wavelength33-35. The phonon mean free path is reduced with shrinking NW diameter in the entire wavelength range. When the diameter decreases, phonon scattering becomes stronger in all wavelength ranges and their mean free path is suppressed; these contribute to the reduction of


9

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 10 of 36

thermal conductivity, as shown in Fig. 2 (d). The temperature dependence of thermal conductivity for vertical Si-NWs (η = 2.28 and 6.88 nm) was investigated in the temperature range of 300-500 K (Fig. 3 (a)). The calculated thermal conductivity of bulk Si is also added as solid line for comparison. Unlike the bulk Si, the vertical Si-NWs show negligible change in thermal conductivity in the temperature range of 300-500K because the phonon mean free path is hardly affected by the temperature (Fig. 3 (b)). In contrast, the thermal conductivity changes in the all temperature ranges when changing the diameter or the surface roughness. This means that τb-1 is significantly dominant compared to τu-1 in the scattering rate of vertical Si-NW (τ-1 = τb-1 + τu-1). Therefore, even if the surface roughness increases or the diameter decreases, the influence of temperature change on the phonon mean free path is negligible (Fig. S5).

Effect of doping concentration on thermal conductivity Addition of dopants within the Si crystalline lattices is an effective method for suppression of thermal conductivity12,36,37. Figure 4 (a) shows the measured thermal conductivity for intrinsic, boron doped (B-doped) and phosphorus doped (P-doped) vertical Si-NWs for η = 2.28 and 6.88 nm. The doping concentrations of boron and phosphorus are 2.3 x 1019 and 1.4 x 1019 cm-3, respectively, and the intrinsic Si-NW has a doping concentration of 1015 cm-3. Regardless of the


10

Page 11 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

diameter and roughness, the B-doped and P-doped vertical Si-NWs tend to have a lower thermal conductivity compared to the intrinsic Si-NW. More specifically, the boron ion further contributes to the decrease in thermal conductivity of the Si-NW than the phosphorous ion. When the rough nanowires with DNW = 200 nm are doped with boron and phosphorus ion, respectively, the thermal conductivity of doped nanowires is 71.5% and 58.4% less than the intrinsic rough nanowire, respectively. The B- doped and P-doped vertical rough Si-NWs (DNW = 200 nm and η = 6.88 nm) exhibit the lowest thermal conductivity of 10.1 and 14.8 W ∙ m-1 ∙ K1,in

,respectively, which are about 14.8 and 10.1 fold lower than that of bulk Si (150 W∙m-1∙K-1)6.

In particular, the B-doped rough Si-NW (DNW = 200 nm and η = 6.88 nm) exhibits the lowest thermal conductivity. It is well-known that when the doping concentration is less than about 1020 cm-3, the thermal conductivity is suppressed with increasing doping concentration due to the phonon scattering between the host atom and the impurity atom36,37. Figure 4 (b) and (c) show the phonon mean free path and cumulative thermal conductivity vs. reciprocal of phonon wavelength for the B-doped and P-doped rough nanowire with DNW = 200 and 350 nm, as calculated using the combined scattering rate as: τ -1 = τ b-1 + τ u-1 + τ i-1 where τ i -1 is the impurity scattering rate given by ―1 ―1 = 𝜏𝑖―1 = 𝜏𝛿𝑚 + 𝜏𝛿𝑟

𝑛𝑉2

𝛿𝑀 2 4 𝑀

( )𝜔

4𝜋𝑣𝑏3

+

2𝑛𝑉2𝑄02𝛾2 𝛿𝑅 2 4 𝑅 𝜔 𝜋𝑣𝑏3

( )

(3)


11

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 12 of 36

―1 ―1 where 𝜏𝛿𝑚 is mass-difference impurity scattering rate, 𝜏𝛿𝑟 is radius-difference impurity

scattering rate, 𝑛 is the volumetric concentration, 𝑉 is the crystal volume of host atom, 𝑀 is the mass of host atom, and δM is the difference of mass, 𝑄0 is how the nearest and further-out linkages combine in the scattering matrix, 𝛾 is Grüneisen constant, R is the radius of the host atom, and δR is the difference of radius. The phonon-impurity scattering is dominantly caused 𝛿𝑀

𝛿𝑅

by the difference in mass ( 𝑀 ) and radius ( 𝑅 ) between the host atom and impurity atoms. 𝛿𝑀

𝛿𝑅

Previously reported ( 𝑀 ) and ( 𝑅 ) values for B-doped and P-doped Si were used here36,37. The phonon mean free path in the short wavelength is further reduced than that in the long wavelength since the injected ions (boron and phosphorus) mainly cause the additional scattering of short wavelength phonons (Fig. 4 (b) and (c)). Therefore, the phonons with short wavelength significantly contribute to the reduction in thermal conductivity. Impurity scattering is further enhanced when the vertical rough Si-NW is implanted with boron ions (dose of 2.3 x 1019 cm-3) rather than phosphorus ions with a dose of 1.4 x 1019 cm-3. Boron and phosphorous ions 𝛿𝑀

𝛿𝑀

implanted in Si show a relationship of ( 𝑀 ) ≈ 6( 𝑀 ) 𝐵

𝑃

𝛿𝑅

𝛿𝑅

and ( 𝑅 )𝐵 ≈ 4( 𝑅 )𝑃36. At the same

doping concentration, the B-doped Si-NW has lower thermal conductivity since the mass and radius scattering coefficients of boron are larger than those of phosphorus due to the large


12

Page 13 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

difference in mass and radius between the Si and boron ion. It is known that the change in the thermal conductivity due to the change in doping concentration is negligible, when the doping concentrations is higher than 1018 cm-3 at room temperature36. Therefore, we can see that the Bdoped rough Si-NW has lower thermal conductivity than P-doped Si-NW due to large mass and radius scattering coefficient, not high doping concentration. Ion implantation is one of the effective methods to reduce the thermal conductivity of vertical Si-NWs and the type of dopant contributes strongly to the reduction of thermal conductivity.

Demonstration of thermoelectric generator Si-NWs fabricated by the EE method have very low thermal conductivity comparable to amorphous SiO2 and high ZT12,16,20. However, it is difficult to make the thermoelectric module with a large number of electrical series connections between p-type and n-type Si-NWs because they cannot be precisely formed at the desired position using the EE method. Here, we have fabricated a thermoelectric module with many connections between the p-type and n-type rough Si-NW legs using the top down approach and demonstrated its thermoelectric power generation performance. The thermoelectric modules were fabricated on a 8-inch SOI wafer (p-type, 1-10 Ω∙cm) using B-doped and P-doped vertical Si-NW structures (η = 6.88 nm, DNW = 200 nm, pitch


13

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 14 of 36

of 750 nm, and height of 2m). The main fabrication process flow is shown in Fig. 5 (a) and the detailed fabrication process is described in the Methods section. The thermoelectric device with a size of 1 cm x 1 cm was successfully fabricated and then the vertical rough Si-NW thermoelectric module was made by attaching the ceramic substrate to both sides of the thermoelectric device chip (Fig. 5(a)). The open circuit voltage, short circuit current (ISC) and generated power of the thermoelectric modules were measured using an in-house measurement system built with a commercial heater plate and heat sink consisting of a commercial Peltier cooler and a fan (Fig. S6). The temperature on the hot side was adjusted via a PID controller unit driving the heater plate. In contrast, the temperature of the Peltier cooler was not controlled by feedback of the actual temperature data measured by the temperature sensor. The temperature on the cold side was set by applying a specific current to the cooler. The heater temperature was increased from 273K to 473K at 10K intervals while the cooler temperature was always set at 273K. The temperature difference was calculated from the experimental setting values of the hot and cold sides. In order to eliminate the effect of the module size, the open circuit voltage per unit area (VOC) was defined by dividing the open circuit voltage by the module area. Figure 5(b) shows the measured VOC of the thermoelectric modules according to the temperature difference, showing a linear increase with


14

Page 15 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

the temperature difference. The results for various thermoelectric modules are also included in Fig. 5 (b) for comparison

38-41.

A VOC of 216.8 mV·cm-2 is observed when the temperature difference

across the whole experimental set-up is 180K. Although the rough Si-NW thermoelectric module has a larger diameter and smaller number of legs per unit area than other Si-NW modules, it exhibits at least 1.5 times higher VOC than the rest (Table S1). The generated maximum power (PMAX) increases with the temperature difference (Fig. 5 (c)). The module shows a PMAX of 3.74 μW and

ISC of 63 μA under a temperature difference of 180 K. This PMAX is higher than that of a previously reported Si-NW thermoelectric generator41. When the surface roughness increases from 2.28 to 6.88 nm, the rough Si-NW shows about 40% reduction in the thermal conductivity compared to the smooth Si-NW. The lower thermal conductivity can generate a larger temperature difference within the nanowire structure at a given heat flux, leading to increased

VOC and PMAX. To clarify the reason for the improved thermoelectric performance (VOC and PMAX), the effect of surface roughness on the Seebeck coefficient and the electrical conductivity was also investigated using the P-doped Si-NW legs with DNW = 200 nm and η = 2.28 and 6.88 nm (Fig. S7). The vertical Si-NWs with η of 2.28 and 6.88 nm showed Seebeck coefficients of 266 and 298 V/K, respectively. The rough Si-NW shows 15% improvement in the Seebeck coefficient


15

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 16 of 36

and a negligible reduction in the electrical conductivity compared to the smooth Si-NW. The Bdoped Si-NWs are expected to show a similar trend to P-doped Si-NWs. Based on these results, the improved power generation performance (VOC and PMAX) of the rough Si-NW module is attributed to the low thermal conductivity and high Seebeck coefficient of the rough Si-NW. In particular, a significant reduction in thermal conductivity (~ 40 %) has the greatest effect on improving thermoelectric performance. In conclusion, we have dramatically reduced the thermal conductivity of vertical Si-NWs by controlling the surface roughness, diameter, and doping concentration using a top-down fabrication. The vertical Si-NW with smaller diameter, rougher surface and higher doping concentration can lead to more phonon scattering, resulting in lower thermal conductivity. This thermal conductivity reduction was theoretically analyzed by applying various scattering models to phonon-Boltzmann equation. The boundary scattering becomes stronger as the surface roughness increases or the diameter decreases, resulting in suppression of thermal conductivity. When the dopant is implanted into intrinsic Si-NW, the phonons with short wavelength are strongly scattered due to impurity scattering and cause a drop in thermal conductivity. The impurity scattering is maximized when the difference in mass and radius between the Si atom and the dopant becomes larger. Whereas the thermal conductivity of bulk Si decreases with


16

Page 17 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

increasing temperature due to phonon scattering at short wavelengths, the vertical Si-NWs show almost no change in thermal conductivity due to temperature change. The B-doped and Pdoped rough Si-NWs (DNW = 200 nm and η = 6.88 nm) exhibit low thermal conductivity of 10.1 and 14.8 W·m-1·K-1, respectively, which are 5.1 and 3.6 fold lower than undoped smooth Si-NW (DNW = 200 nm and η = 2.28 nm). These vertical rough Si-NWs with low thermal conductivity were used to fabricate a thermoelectric module, which exhibited an excellent open circuit voltage of 216.8 mV·cm-2 and a power of 3.74 W·cm-2 under a temperature difference of 180K. The improvement in thermoelectric performance comes from the rough Si-NW structure with a significant reduction in thermal conductivity through a control of the surface roughness, diameter and doping concentration. Our topdown fabrication method can provide a route towards the efficient and cost-effective fabrication of thermoelectric modules for generating power from waste heat.

METHODS Sample preparation for measuring thermal conductivity. The starting material was an 8-inch (100) Si wafer (p-type, 1-10 Ω∙cm), which corresponds to a doping concentration of about 1015 cm-3. A 400 nm thick SiO2 layer was thermally grown on the Si wafer using wet oxidation process. For the formation of vertical Si-NW, circular patterns with diameters of 200 and 350 nm at a pitch of 750 nm were defined on the SiO2 layer using KrF scanner. The SiO2 layer used as a hard mask was first etched using the ICP-RIE. For the formation of Si-NW, the Si wafer was then etched to a depth


17

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 18 of 36

of 2 m using the ICP-RIE with a mixture of SF6, O2, and He gases. The roughness of the vertical SiNW was controlled by the chamber pressure and the flow rates of SF6 and O2. SF6 serves to etch Si and the O2 provides sidewall protection during the etching process. Thus, as the flow rate of SF6 and pressure increase, the surface of the vertical Si-NW becomes rougher. In contrast, a smooth surface is formed by increasing the flow rate of O2. The surface roughness of three different cases was realized by using three kinds of etching conditions. To remove surface damage by the plasma, a 4 nm thick SiO2 was thermally grown as a sacrificial oxide, followed by immersing in diluted HF solution. In addition, doped Si-NW samples were also prepared to investigate the effect of doping concentration on the thermal conductivity. Boron or phosphorus ions with a dose of about 1019 cm-3 were implanted into different Si-NW samples using tilted ion implantation technique, followed by annealing at 1000 ℃ for 90 minutes. The tilted implantation was performed to uniformly distribute the implanted ions within the entire nanowire and the tilted angle was defined by considering the pitch, diameter and height of the nanowire. Through 3-dimensional atom probe tomography (3D APT), we confirmed that the doping concentrations for B-doped and P-doped Si-NWs were 2.3 x 1019 and 1.4 x 1019 cm-3, respectively. The gaps between the vertical Si-NWs were filled with SOG, which has a low thermal conductivity. This sample is called the composite sample. A 30 nm thick SiO2 film was deposited for electrical isolation, and


18

Page 19 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

then the π-shaped metal line serving as a heater and a thermometer were finally formed on the SiO2 film using lift-off technique, as shown in Fig. S8 (a). SiO2, SOG, and PI samples were also prepared to confirm the accuracy of our measurement system.

Thermal conductivity measurement. The differential 3ω technique is a well-known method for measuring the thermal conductivity of a thin film using a π-shaped metal line26,42. Figure S8 (b) shows a schematic of the measurement principle. When an AC current of the ω frequency is applied to the metal line, a temperature oscillation of T2ω is generated due to the Joule heat and the electrical resistance of the metal line is modulated, resulting in the generation of a voltage drop at a frequency 3ω (V3ω). The V3ω was measured using an in-house built measurement system consisting of a vacuum probe station with chuck temperature controller, a signal processing circuit and a lock-in-amplifier (SR830), as shown in Fig. S2 (a). The T2ω is determined by the V3ω, and the thermal conductivity of the thin film is given by26

𝑃ℎ𝑒𝑎𝑡𝑒𝑟 ∙ 𝑡𝑓𝑖𝑙𝑚

𝑘𝑓𝑖𝑙𝑚 = 𝑤 ∙ 𝑙 ∙ Δ𝑇𝑓𝑖𝑙𝑚

(4)

where 𝑃ℎ𝑒𝑎𝑡𝑒𝑟 is the power generated from the metal line, 𝑡𝑓𝑖𝑙𝑚 is the thickness of thin film, 𝑤 and 𝑙 are the width and length of the metal line respectively, and 𝛥𝑇𝑓𝑖𝑙𝑚 is the difference of T2ω between the thin film samples. To extract the thermal conductivity of the vertical Si-NW, the thermal conductivity of the


19

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 20 of 36

fabricated composite film (i.e. vertical Si-NW array filled with SOG film) and SOG film samples was obtained by measuring the V3ω in the frequency range of 100 Hz - 1 kHz. Computational analysis of thermal conductivity. The computational analysis was carried out using the phonon-Boltzmann transport equation to theoretically study the thermal conductivity of the vertical Si-NW. The phonon-Boltzmann equation can generally be used for analyzing heat transport and is given by45,46:

𝑘4𝐵𝑇3

ℏ𝜔𝑐 𝑒𝑦 𝑘𝐵𝑇 𝜏(𝑇,𝑦)𝑦4 𝑦 2𝑑𝑦 (5) (𝑒 ― 1)

𝜅 = 2𝜋2𝑣 ℏ3∫0 𝑏

where 𝜅 is thermal conductivity, 𝑘𝐵 is Boltzmann’s constant, ℏ is Planck’s constant, 𝜔𝑐 is cutoff frequency for Si, 𝑣𝑏 is the phonon group velocity for Si, T is the temperature, 𝜏 is the phonon lifetime, and 𝑦 ≡ ℏ𝜔 𝑘𝐵𝑇. The thermal conductivity can be theoretically analyzed by various models proposed by Callaway, Holland, and Mingo43,45,46. Among them, Mingo’s model, which is based on linearized dispersion with fitting parameters, has been widely utilized because this model has shown good agreement with the measured thermal conductivity of the Si-NWs wider than 35 nm21,33,43.

The parameters used in the calculation are from Mingo et al31,43. The

temperature, surface roughness and impurity can lead to additional phonon scattering mechanisms in nanostructures to affect the heat transport. Therefore, it is necessary to consider the anharmonic (Umklapp), boundary and impurity scattering in theoretical calculations to


20

Page 21 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

accurately analyze their effects on the thermal conductivity of Si-NW. All scattering processes can be taken into account using Mathiessen’s rule. Therefore, the combined scattering rate (τ-1) is written as follows: τ-1 = τb-1 + τu-1 + τi-1. Fabrication of thermoelectric module. An 8-inch (100) SOI wafer (p-type, 1-10 Ω∙cm) with a top silicon thickness of 5 m and buried oxide thickness of 500 nm was used as the starting substrate. The thermoelectric device is designed to have 160 x 160 legs in an area of 1 cm x 1 cm and each leg is located apart with a gap of 10 m. Each leg consists of 50 x 50 nanowires with η of 6.88 nm, diameter of 200 nm, height of 2 m and pitch of 750 nm. The main fabrication process flow is shown in Fig. S9. The vertical Si-NW legs comprising of a Si-NW array were formed using conventional KrF lithography and ICP-RIE. The vertical rough nanowires were uniformly fabricated over the large area (Fig. S10). The thermoelectric module is generally designed such that the p-type and n-type semiconductors are arranged to be thermally parallel and electrically in series. The p-type and n-type legs were therefore defined by selectively tilted ion implantation of boron and phosphorus ions so that they were alternately placed. Ion implantation was performed under the same conditions (concentration and tilted angle) as for the samples for measuring thermal conductivity described earlier. During the formation of p-type legs, the regions of n-type legs were protected from ion implantation of boron using photoresist, and vice


21

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 22 of 36

versa for the formation of n-type legs. After ion implantation, the bottom electrode was formed by a selective cobalt silicidation process to connect the p-type and n-type legs in series (Fig. S10 (a)). For the selective cobalt silicidation, a 30 nm thick SiO2 film was grown on the entire wafer surface using the wet oxidation process to prevent the silicide formation by blocking the reaction between the Si and cobalt. Next, only the SiO2 film at the position where the cobalt silicide is to be formed was selectively removed using optical lithography and ICP-RIE. Anisotropic etching was done so that the SiO2 film on the sidewalls of Si-NW was not etched. Next, a 50 nm thick cobalt was deposited on the wafer surface, followed by annealing at 800 °C for the formation of cobalt silicide. Unreacted cobalt over the SiO2 film was subsequently removed by immersing the wafer in a heated piranha solution (H2SO4:H2O2). 3D APT measurements confirmed the doping concentrations for B-doped and P-doped Si-NWs to be 2.3 x 1019 and 1.4 x 1019 cm-3, respectively, which are the same as samples for measuring thermal conductivity described earlier. The polyimide was coated and cured at 400 °C to fill the gaps between vertical Si-NWs, and the top of the vertical rough Si-NWs was then exposed using O2 plasma etching. A 20 nm thick titanium (Ti) layer and a 200 nm thick gold (Au) layer were deposited and patterned using a lift-off method to electrically connect the p-type and n-type legs. After deposition of SiO2 as passivation layer, the thermoelectric devices were diced into 1


22

Page 23 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

cm×1 cm. Finally, the ceramic plates were attached to both the front and back sides of the thermoelectric device chip using thermal interface paste to make the thermoelectric module.

ASSOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publications website. Additional figures for thermal conductivity measurement, thermal conductivity analysis, device fabrication step, SEM images of fabricated device, thermoelectric module measurement, Seebeck coefficient, and electrical conductivity. Table for open circuit voltage comparison of SiNW modules.

AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] ORCID Kihyun Kim: 0000-0001-7578-7977

Notes


23

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 24 of 36

The authors declare no competing financial interest.

AUTHOR CONTRIBUTIONS S.L. carried out fabrication and characterization of thermoelectric device, analyzed the data and wrote the paper. K.K. conceived the idea, designed the experiments, fabrication and characterization of thermoelectric device, analyzed the data and wrote the paper. D.K. supported design and measurement of thermoelectric module. M.M. and C.B. supported the research and provided experimental advice. All authors discussed the results and contributed to the writing of the manuscript.

ACKNOWLEDGMENTS We acknowledge the financial support from the MSIT (Ministry of Science and ICT), Korea, under the “ICT Consilience Creative program” (IITP-2018-2011-1-00783) supervised by the IITP (Institute for Information & communications Technology Promotion), the “Development of highly sensitive Si photodetector and optimization technique of its characterization of Nd:YAG laser” (No.2018-0-01283) supervised by the IITP, the “Smart Industrial Energy ICT Convergence Consortium” (NIPA-C1601-17-1007) supervised by the NIPA(National IT Industry Promotion


24

Page 25 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

Agency), and the “Nano·Material Technology Development Program” (2009-0082580) supervised by the NRF (National Research Foundation of Korea).

REFERENCES 1. Kim, F.; Kwon, B.; Eom, Y.; Lee, J. E.; Park, S.; Jo, S.; Park, S. H.; Kim, B.-S.; Im, H. J.; Lee, M. H.; Min, T. S.; Kim, K. T.; Chae, H. G.; King, W. P.; Son, J. S., 3D printing of shape-conformable thermoelectric materials using all-inorganic Bi2Te3based inks. Nature Energy 2018, 3 (4), 301-309. 2. Avery, A. D.; Zhou, B. H.; Lee, J.; Lee, E.-S.; Miller, E. M.; Ihly, R.; Wesenberg, D.; Mistry, K. S.; Guillot, S. L.; Zink, B. L.; Kim, Y.-H.; Blackburn, J. L.; Ferguson, A. J., Tailored semiconducting carbon nanotube networks with enhanced thermoelectric properties. Nature Energy 2016, 1, 16033. 3. Bell, L. E., Cooling, heating, generating power, and recovering waste heat with thermoelectric systems. Science 2008, 321 (5895), 1457-1461. 4. Poudel, B.; Hao, Q.; Ma, Y.; Lan, Y.; Minnich, A.; Yu, B.; Yan, X.; Wang, D.; Muto, A.; Vashaee, D., High-thermoelectric performance of nanostructured bismuth antimony telluride bulk alloys. Science 2008, 320 (5876), 634-638. 5. Yazawa, K.; Shakouri, A., Cost-efficiency trade-off and the design of thermoelectric power generators. Env. Science Technol. 2011, 45 (17), 7548-7553. 6. LeBlanc, S.; Yee, S. K.; Scullin, M. L.; Dames, C.; Goodson, K. E., Material and manufacturing cost considerations for thermoelectrics. Renewable and Sustainable

Energy Reviews 2014, 32, 313-327. 7. Tang, J.; Wang, H.-T.; Lee, D. H.; Fardy, M.; Huo, Z.; Russell, T. P.; Yang, P., Holey silicon as an efficient thermoelectric material. Nano Lett. 2010, 10 (10), 42794283.


25

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 26 of 36

8. Curtin, B. M.; Codecido, E. A.; Krämer, S.; Bowers, J. E., Field-effect modulation of thermoelectric properties in multigated silicon nanowires. Nano Lett. 2013, 13 (11), 5503-5508. 9. Kim, K.; Park, C.; Kwon, D.; Kim, D.; Meyyappan, M.; Jeon, S.; Lee, J.-S., Silicon nanowire biosensors for detection of cardiac troponin I (cTnI) with high sensitivity.

Biosensors and Bioelectronics 2016, 77, 695-701. 10. Ko, M.-D.; Rim, T.; Kim, K.; Meyyappan, M.; Baek, C.-K., High efficiency silicon solar cell based on asymmetric nanowire. Sci. Rep. 2015, 5, 11646. 11. Garnett, E.; Yang, P., Light trapping in silicon nanowire solar cells. Nano Lett. 2010,

10 (3), 1082-1087. 12. Hochbaum, A. I.; Chen, R.; Delgado, R. D.; Liang, W.; Garnett, E. C.; Najarian, M.; Majumdar, A.; Yang, P., Enhanced thermoelectric performance of rough silicon nanowires. Nature 2008, 451 (7175), 163-167. 13. Boukai, A. I.; Bunimovich, Y.; Tahir-Kheli, J.; Yu, J.-K.; Goddard Iii, W. A.; Heath, J. R., Silicon nanowires as efficient thermoelectric materials. Nature 2008, 451 (7175), 168. 14. Peng, K.-Q.; Wang, X.; Li, L.; Hu, Y.; Lee, S.-T., Silicon nanowires for advanced energy conversion and storage. Nano Today 2013, 8 (1), 75-97. 15. Li, D.; Wu, Y.; Fan, R.; Yang, P.; Majumdar, A., Thermal conductivity of Si/SiGe superlattice nanowires. Appl. Phys. Lett. 2003, 83 (15), 3186-3188. 16. Lee, J.; Lee, W.; Lim, J.; Yu, Y.; Kong, Q.; Urban, J. J.; Yang, P., Thermal transport in silicon nanowires at high temperature up to 700 K. Nano Lett. 2016, 16 (7), 41334140. 17. Xu, B.; Khouri, W.; Fobelets, K., Two-sided silicon nanowire array/bulk thermoelectric power generator. IEEE Electron Device Lett. 2014, 35 (5), 596-598. 18. Weisse, J. M.; Marconnet, A. M.; Kim, D. R.; Rao, P. M.; Panzer, M. A.; Goodson, K. E.; Zheng, X., Thermal conductivity in porous silicon nanowire arrays. Nanoscale

Res. Lett. 2012, 7 (1), 554. 19. Feser, J. P.; Sadhu, J. S.; Azeredo, B. P.; Hsu, K. H.; Ma, J.; Kim, J.; Seong, M.; Fang, N. X.; Li, X.; Ferreira, P. M., Thermal conductivity of silicon nanowire arrays with controlled roughness. J. Appl. Phys. 2012, 112 (11), 114306.


26

Page 27 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

20. Lim, J.; Hippalgaonkar, K.; Andrews, S. C.; Majumdar, A.; Yang, P., Quantifying surface roughness effects on phonon transport in silicon nanowires. Nano Lett. 2012, 12 (5), 2475-2482. 21. Malhotra, A.; Maldovan, M., Impact of phonon surface scattering on thermal energy distribution of Si and SiGe nanowires. Sci. Rep. 2016, 6, 25818. 22. Moore, A. L.; Saha, S. K.; Prasher, R. S.; Shi, L., Phonon backscattering and thermal conductivity suppression in sawtooth nanowires. Appl. Phys. Lett. 2008, 93 (8), 083112. 23. Bouaïcha, M.; Khardani, M.; Bessais, B., Evaluation of the electrical conductivity of nano-porous silicon from photoluminescence and particle size distribution. Mater.

Sci. Eng.: B 2008, 147 (2-3), 235-238. 24. Zhang, T.; Wu, S.; Xu, J.; Zheng, R.; Cheng, G., High thermoelectric figure-of-merits from large-area porous silicon nanowire arrays. Nano Energy 2015, 13, 433-441. 25. Hochbaum, A. I.; Gargas, D.; Hwang, Y. J.; Yang, P., Single crystalline mesoporous silicon nanowires. Nano Lett. 2009, 9 (10), 3550-3554. 26. Lee, S.-M.; Cahill, D. G., Heat transport in thin dielectric films. J. Appl. Phys. 1997,

81 (6), 2590-2595. 27. Costescu, R. M.; Bullen, A. J.; Matamis, G.; O’Hara, K. E.; Cahill, D. G., Thermal conductivity and sound velocities of hydrogen-silsesquioxane low-k dielectrics.

Phys. Rev. B 2002, 65 (9), 094205. 28. Curtin, B. M.; Fang, E. W.; Bowers, J. E., Highly ordered vertical silicon nanowire array composite thin films for thermoelectric devices. J. Elect. Mater. 2012, 41 (5), 887-894. 29. Ghose, S.; Watson, K.; Delozier, D.; Working, D.; Connell, J. W.; Smith, J.; Sun, Y.; Lin, Y. In Thermal Conductivity of Polyimide/Carbon Nanofiller Blends, Key Engineering Materials, Trans Tech Publ: 2007; pp 749-752. 30. Ziman, J. M., Electrons and phonons: the theory of transport phenomena in solids. Oxford university press: 1960. 31. Wang, Z.; Mingo, N., Diameter dependence of SiGe nanowire thermal conductivity.

Appl. Phys. Lett. 2010, 97 (10), 101903.


27

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 28 of 36

32. Casimir, H., Note on the conduction of heat in crystals. Physica 1938, 5 (6), 495500. 33. Lee, J.; Lim, J.; Yang, P., Ballistic phonon transport in holey silicon. Nano Lett. 2015, 15 (5), 3273-3279. 34. Xie, G.; Guo, Y.; Wei, X.; Zhang, K.; Sun, L.; Zhong, J.; Zhang, G.; Zhang, Y.-W., Phonon mean free path spectrum and thermal conductivity for Si1− xGex nanowires. Appl. Phys. Lett. 2014, 104 (23), 233901. 35. Satyala, N.; Vashaee, D., The effect of crystallite size on thermoelectric properties of bulk nanostructured magnesium silicide (Mg2Si) compounds. Appl. Phys. Lett. 2012, 100 (7), 073107. 36. Asheghi, M.; Kurabayashi, K.; Kasnavi, R.; Goodson, K., Thermal conduction in doped single-crystal silicon films. J. Appl. Phys. 2002, 91 (8), 5079-5088. 37. Liu, W.; Asheghi, M., Thermal conduction in ultrathin pure and doped single-crystal silicon layers at high temperatures. J. Appl. Phys. 2005, 98 (12), 123523. 38. Li, Y.; Buddharaju, K.; Singh, N.; Lee, S., Top-down silicon nanowire-based thermoelectric generator: design and characterization. J. Elect. Mater. 2012, 41 (6), 989-992. 39. Li, Y.; Buddharaju, K.; Singh, N.; Lo, G.; Lee, S., Chip-level thermoelectric power generators based on high-density silicon nanowire array prepared with top-down CMOS technology. IEEE Electron Device Lett. 2011, 32 (5), 674-676. 40. Li, Y.; Buddharaju, K.; Tinh, B. C.; Singh, N.; Lee, S. J., Improved vertical silicon nanowire based thermoelectric power generator with polyimide filling. IEEE Electron

Device Lett. 2012, 33 (5), 715-717. 41. Dávila, D.; Tarancon, A.; Calaza, C.; Salleras, M.; Fernández-Regúlez, M.; San Paulo, A.; Fonseca, L., Monolithically integrated thermoelectric energy harvester based on silicon nanowire arrays for powering micro/nanodevices. Nano Energy 2012, 1 (6), 812-819. 42. Cahill, D. G., Thermal conductivity measurement from 30 to 750 K: the 3ω method.

Rev. Sci. Inst. 1990, 61 (2), 802-808. 43. Mingo, N., Calculation of Si nanowire thermal conductivity using complete phonon dispersion relations. Phys. Rev. B 2003, 68 (11), 113308.


28

Page 29 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

44. Mingo, N.; Hauser, D.; Kobayashi, N.; Plissonnier, M.; Shakouri, A., “Nanoparticlein-Alloy” approach to efficient thermoelectrics: silicides in SiGe. Nano Lett. 2009, 9 (2), 711-715. 45. Callaway, J., Model for lattice thermal conductivity at low temperatures. Phys. Rev. 1959, 113 (4), 1046. 46. Holland, M., Analysis of lattice thermal conductivity. Phys. Rev. 1963, 132 (6), 2461.


29

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 30 of 36

Figure 1. Structural characterization of the vertical Si-NWs with rough surface. a, Crosssectional view scanning electron microscope (SEM) image of the vertical Si-NW array with diameter of 200 nm and height of 2 m. Inset shows top-view SEM image. b-d, High-resolution transmission electron microscope (HR-TEM) images of the vertical Si-NWs (Surface roughness (η) = 2.28 nm, 4.29 nm and 6.88 nm).


30

Page 31 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

Figure. 2. Thermal conductivity of vertical Si-NWs with different diameters (DNW) and surface roughness (η). a, Thermal conductivity of various vertical Si-NWs (Filled symbol: measured data, empty symbol: previously reported data in the literature, solid line: calculated value using p*). b, Thermal conductivity of vertical Si-NWs with DNW of 200 nm (red) and 350 nm (black) as function of normalized specular parameter p* related with η (Filled symbol: measured data and solid line: calculated value using p*). c, Phonon mean free path and cumulative thermal conductivity versus reciprocal of phonon wavelength for vertical Si-NWs with DNW of 200 nm and

η = 2.28, 4.29 and 6.88 nm. d, Phonon mean free path and cumulative thermal conductivity versus reciprocal of phonon wavelength for the vertical Si-NWs with DNW of 200 nm (red) and 350 nm (blue).


31

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 32 of 36

Figure 3. Temperature dependence of heat transport for vertical Si-NWs. a, Thermal conductivity of vertical Si-NWs with different diameters and surface roughness in the temperature range of 300-500 K. b, Phonon mean free path versus reciprocal of phonon wavelength for bulk Si and vertical Si-NWs (DNW= 200 and 350 nm) with η = 6.88 nm at temperature of 300 (blue), 400 (black), 500 K (red).


32

Page 33 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters


33

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 34 of 36

Figure 4. Dopant dependence of the thermal conductivity of vertical Si-NWs. a, Comparison of thermal conductivity according to diameter and dopant in vertical Si-NWs with η = 2.28 and 6.88 nm. b, Phonon mean free path and cumulative thermal conductivity versus reciprocal of phonon wavelength for intrinsic (black), phosphorous doped (red), and boron doped (blue) vertical rough Si-NWs with diameter of 350 nm. c, Phonon mean free path and cumulative thermal conductivity


34

Page 35 of 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

versus reciprocal of phonon wavelength for intrinsic (black), phosphorous doped (red), and boron doped (blue) vertical rough Si-NWs with diameter of 200 nm.


35

Nano Letters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 36 of 36

Figure 5. Power generation performance of vertical rough Si-NW thermoelectric module. a, Photograph of a fabricated thermoelectric device chip and module with a size of 1 cm X 1 cm. b, Open circuit voltage versus temperature difference for various Si-NW thermoelectric modules. c, Output voltage and power generation of the rough Si-NW thermoelectric module for various temperature differences.

Table of Content Image


36

Vertical Silicon Nanowire Thermoelectric Modules with Enhanced

Recommend Documents