Vertically Integrated Multiple Nanowire Field Effect Transistor - Nano

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Vertically Integrated Multiple Nanowire Field Effect Transistor Byung-Hyun Lee, Min-Ho Kang, Dae-Chul Ahn, Jun-Young Park, Taewook Bang, Seung-Bae Jeon, Jae Hur, Dongil Lee, and Yang-Kyu Choi Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.5b03460 • Publication Date (Web): 06 Nov 2015 Downloaded from http://pubs.acs.org on November 8, 2015

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Vertically Integrated Multiple Nanowire Field Effect Transistor Byung-Hyun Lee, 1,2 Min-Ho Kang,3 Dae-Chul Ahn, 1 Jun-young Park, 1 Taewook Bang, 1 SeungBae Jeon,1 Jae Hur, 1Dongil Lee, 1 and Yang-Kyu Choi1* 1

School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea

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Department of Memory Business, Samsung Electronics, San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do 445-701, Republic of Korea

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Department of Nano-process, National Nanofab Center (NNFC), 291 Daehak-ro, Yuseong-gu, Daejeon 305-701, Republic of Korea

Byung-Hyun Lee: [email protected] Min-Ho Kang: [email protected] Dae-Chul Ahn: [email protected] Jun-Young Park: [email protected] Taewook Bang: [email protected]

ACS Paragon Plus Environment

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Seung-Bae Jeon: [email protected] Jae Hur: [email protected] Dongil Lee: [email protected] Yang-Kyu Choi: [email protected] * Address correspondence to [email protected].


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Abstract A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by five-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

Keywords: Silicon nanowire (SiNW), Gate-all-around (GAA), Vertical integration, Field-effect transistor (FET), Three-dimensional nonvolatile memory, One-route all-dry etch.


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During the past several decades, microelectronics has led to the remarkable growth of information technology (IT), and the transistor has played a crucial role in this achievement. The transistor is the most fundamental component among the great variety of electronic components used to configure a functional block. With the development of silicon-based semiconductor technology, the metal-oxide-semiconductor field-effect transistor (MOSFET) has been studied carefully for its geometrical miniaturization, yielding continual improvements in the fabrication cost, productivity levels, and performance.1 However, the continuous scaling down of the transistor gave rise to fatal short-channel effects (SCEs)2-3 in addition to process limitations, which has increased the demand for a novel approach to meet new high-performance and scalability goals. In order to overcome the severe SCEs originating from the continuing device miniaturization efforts, considerable endeavors has been dedicated to the use of new materials,4-7 innovative designs,8,9 and novel operations.10-12 Despite the fact that several new materials hold great promise, however, silicon still remains the most attractive material when considering its cost and the maturity of its fabrication process.13 In particular, various attempts based on the silicon process, which is a core technology for fabricating semiconductor devices, have permitted novel designs of transistors to suppress SCEs, resulting in the creation of three-dimensional (3-D) structures beyond the conventional two-dimensional (2-D) structures.14 As a result, multiple-gate structures with high gate controllability, such as a tri-gate,15 omega-gate,16 and gate-all-around (GAA)17 structures, were introduced as alternatives. Among them, due to its reinforced electrostatic controllability and transport properties, the GAA structure is considered by many to be the most promising candidate to extend the roadmap of electronic devices with regard to the suppression of SCEs.13, 17 In this respect, the GAA-based silicon nanowire (SiNW) structure


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allowed for the extreme scaling down of the transistor to less than 3 nm, 18 thereby showing high potential for versatile applications in various fields.19-22 Although the GAA-based SiNW is an optimal structure with which to suppress SCEs, this structure is associated with a critical problem related to the extreme scaling down of NW. Due to the strong dependency on the size of the NW with respect to the on-state current (ION), employing this structure requires a proper compromise between the controllability of SCEs and the drivability of ION.23 Continuous research to increase ION under given dimensions have led to various attempts, such as strained silicon and new channel materials with high mobility.13 However, severe process variability, the increasing fabrication cost, and poor compatibility with the silicon process are all issues which have yet to be resolved. Here, the increase of the ION rate should be prudently taken into account. It is typically reported that the drivability of ION using strained silicon technology increases by 200 %.24 However, the improvement effect remarkably decreases by 25 % under sub-100 nm regime, 25-27 and further the effect can be unexpectedly degraded by extremely scaled NW below 10 nm. It should be noted that the recorded increase of the rate, i.e., 25 %, is also not acceptable for the feasibility of high-performance-oriented SiNW transistors. Considering the process-induced variability and fabrication costs, the most indisputable solution for the improvement of ION is to augment the number of NWs such as in a multiple-channel-based FET.28 However, laterally bundling multiple NWs (multi-NWs) directly conflicts with the density of the integration due to the enlarged size of the transistor. In addition, a research on the vertical nanowire FET comprised of a cylindrical shell-like gate wrapping a silicon pillar was reported.29It has a drain (D) electrode at top and a source (S) electrode at bottom, which are perpendicular to wafer surface. But the vertical nanowire FET has a few weaknesses. First, in the vertical nanowire FET, a gate length is corresponding to a height


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difference between S/D thus there is only one-gate length (fixed gate length) in a wafer because such height is determined by the etching time of a silicon pillar. Hence a circuit design to use various gate lengths is limited. Second, in terms of packing density, the horizontal nanowire FET is preferred because its foot print in layout is not increased as long as the multiple nanowires are vertically stacked. Third, the inherent asymmetric S/D resistance arisen from the vertical configuration of the pillar is problematic as reported elsewhere. 30,31 Thus, the development of an optimal structure that satisfies high ION and good scalability simultaneously is required. The best strategy is to combine the GAA structure to suppress SCEs for ultimate scalability and a vertically integrated NW structure to maximize the ION current for high performance. In this study, we demonstrate a vertically integrated multi-NW FET (VM-FET) on a bulk-Si substrate using one-route all-dry etching process (ORADEP) for the first time. The vertical stacking of NW has been suggested as an alternative to meet the new requirements of high performance and good scalability. However, previous results revealed a limitation to the stable formation of a vertically integrated multi-NW structure due to the complexity of the process and process-induced critical failures. Fang et al.32 fabricated a vertically integrated multi-NW by stacking of dual materials. However, their method requires careful treatment of the interface due to the use of a heteromaterial. Unlike the oxidation and wet etching process reported by Fang et al., the selective dry etching announced by Dupré et al.33 and Bernard et al.34 is easy and simple technique for the stable formation of vertically integrated 3-D channel. But, their works cannot avoid the process complexity originated from the epitaxial growth of Si and Ge. Another approach to realize a vertically integrated multi-NW structure was proposed in the work of Sacchetto et al.35 and Ng et al.36 Their scheme, which is known as the Bosch process, allowed the fabrication of a frame for the multi-NW structure via deep reactive-ion etching


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(DRIE). However, sequential iterative sacrificial oxidation and wet etching led to serious concerns over stiction failure, as the structure is associated with the unstable formation of NW as well as greater process complexity. Therefore, the stable formation of vertically integrated multiNW in the fabrication process with high controllability and high reproducibility remains a challenge. Under such conditions, this study demonstrates a simple ORADEP which can be used to create stable vertically integrated multi-NW structures without stiction failure, which permits for the first time the stable formation of multi-NWs stacked up to five levels. Because the process offers high uniformity and high reproducibility, it can be utilized for the creation of highly integrated arrays with even more than five levels. Moreover, it is possible to utilize the process regardless of whether a bulk-Si or a silicon-on -insulator (SOI) substrate is used. An image of a VM-FET with the most number of NWs was captured with the aid of high-resolution transmission electron microscopy (TEM), which proves the superiority of this process compared to previous results.32,35,36 The device exhibited outstanding performance without a significant degradation of important parameters compared to a single NW-based FET. Furthermore, the VM-FET with oxide/nitride/oxide (ONO) gate dielectric which served as a charge-trapping layer was successfully applied to nonvolatile memory (NVM), resulting in reliable memory functioning. Note that this result is suitable for the full 3-D integration of high-capacity Flash memory based on its low cost and high throughput using a fully complementary MOS (CMOS) compatible process. Thus, this study demonstrates the feasibility of the most advanced type of transistor, which offers high performance, good scalability, and excellent controllability of SCEs for future electronics. The formation of the vertically integrated multi-NW is the most crucial procedure for fabricating such a VM-FET with five channels. Therefore, the ORADEP was introduced as a


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key process in this study, as illustrated in Figure 1a. The ORADEP consists of polymer passivation and a sequential isotropic dry etching step. First, C4F8-based polymer is adsorbed on the region patterned by an oxide hard mask, where the hard mask serves as a protection layer during the ORADEP to form vertically integrated multi-NW. Next, plasma etching using SF6 gas is done to form the NWs. Because the sidewall of the patterned silicon is protected from the C4F8-based polymer during the SF6-based plasma etching process, it is possible to form a NW profile by means of isotropic dry etching. The iteration of such a process, i.e., polymer passivation and plasma etching, allows the reproducible formation of uniform NW. Unlike previous procedures, there is no sequential carving oxidation or wet etching to fabricate vertically integrated multi-NW structures when using this process. Accordingly, ORADEP circumvents process complexity and stiction failure. However, non-optimized condition of the ORADEP can cause either a scallop pattern, in which each NW is not completely separated from others, or even broken NWs (See the Supporting Information). Therefore, it should be noted that the optimization of the main parameters, such as the flux of the gas, i.e., C4F8 or SF6, the polymer passivation and plasm etching times, the chuck temperature, and the plasma power, is required. The detailed process conditions are provided in the Supporting Information. An image of a vertically integrated multi-NW structure formed by the ORADEP is presented in Figures 1b and 1c. The uniform and stiction-free formation of NWs as realized using the optimum conditions is identified via scanning electron microscopy (SEM) and TEM. Figure 2 shows the flow of the main fabrication process. A bulk-Si wafer was used as a substrate. The channel region is defined by a high-resolution photolithography process, and the optimized ORADEP is then employed to form the vertically integrated multiNWs. For the isolation of the transistors, an inter-layer dielectric (ILD) material is deposited


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with the aid of a low pressure chemical vapor deposition (LPCVD) technique, followed by planarization using a chemical mechanical polishing (CMP) technique. The release of the SiNW for the GAA structure is done via the partial etching of the ILD. Thermal oxidation and a LPCVD process are employed, respectively, to form the gate dielectrics for the transistor and the memory function. The poly-crystalline silicon (poly-Si) for the gate electrode is deposited by LPCVD to surround the SiNW, after which the poly-Si is plarnarized by means of the CMP process. In order to protect the actual channel region during the ion implantation process to form the S/D electrode, the proper hard mask layers composed of oxide and nitride were deposited on the planarized poly-Si. And then, the gate was patterned by a typical photolithography and dry etching process. Finally, the S/D region to serve as an electrode is formed by self-aligned ion implantation, followed by a rapid thermal annealing (RTA) process for dopant activation and the curing of implantation-induced physical damage. Self-aligned S/D implantation was carried out while the exposed gate blocked the dopants as the implant stopper. Thus excepting the region covered by the exposed gate, all other areas were heavily doped. The I-V characteristics shown in Figure 4 demonstrate the suitability and acceptable variability arisen from the proposed processes. Supporting Information includes the details of the overall process. A schematic of a VM-FET fabricated using this process is illustrated in Figure 2b. Figure 3a shows cross-sectional TEM images of the fabricated device cut along the a-a' direction shown in Figure 2b. The clear separation of NWs surrounded by poly-Si shows the complete realization of the GAA structure with the vertically integrated multi-NWs. Note that the presence of five vertically integrated SiNWs with a uniform profile verifies the reliable process reproducibility of the ORADEP. Figure 3b shows an enlarged image of one of the


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SiNWs shown in Figure 3a. Thermally grown silicon dioxide (SiO2) surrounding the SiNW with a type of rhombus serves as a gate dielectric layer for a MOSFET, which is clearly defined by energy-dispersive X-ray spectroscopy (EDS) mapping as shown in Figure 3c. The highresolution image of the SiNW in Figure 3d shows the silicon lattice. Its high-crystallinity is also supported by the fast Fourier transform (FFT) image in Figure 3e, demonstrating the high stability of the ORADEP. In addition to the VM-FET with the thermal oxide for the gate dielectric, silicon/oxide/nitride/oxide/silicon (SONOS) structure-based nonvolatile memory (NVM) with vertically integrated multi-NWs was fabricated. Excluding the process to form the gate dielectric, the fabrication process of the memory is equivalent to that of a VM-FET created with thermal oxide. Figure 3f shows a cross-sectional TEM image of vertically integrated SONOS NW-based NVM. The thickness of tunnel oxide with a 3 nm, charge trapping nitride with a 6 nm, and barrier oxide with 8 nm are clearly defined in Figure 3g, as supported by the EDS mapping analysis results shown in Figure 3h. The electrical characteristics of this type of VM-FET are shown in Figure 4. The drain current – drain voltage (ID-VD) characteristic of the VM-FET with five channels is compared to that of the single NW-based transistor in Figure 4a. The VM-FET with five channels exhibits a significant enhancement of ION compared to the single NW-based FET. Figure 4b shows a comparison of ION at the same operation voltage considering the difference in the threshold voltage (VT), where a significant increase in ION, by nearly fivefold, is identified in the VM-FET with five channels. The drain current – gate voltage (ID-VG) characteristic shown in Figure 4c exhibits a high ION which exceeds 100µA with a steep switching function. No severe performance degradation or abnormal characteristics were noted during the switching operation. The VM-FET with five channels results in clearly improved drivability of ION without the


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abnormal degradation of any of the parameters, which verifies the feasibility of this device for the vertical stacking of NW and ultimately to mitigate the performance degradation caused by the extreme scaling down of NW. In addition to the VM-FET with the thermal oxide gate dielectric, the memory effect of a five level integrated GAA-based SONOS NW FET is presented in Figure 5. The NVM characteristics are demonstrated in Figures 5a to 5d. As shown in Figure 5a, a large programming window above 5 V, referring to the difference in the threshold voltage before and after programming, is obtained from this memory device without degradation of the subthreshold slope (SS), demonstrating the viability of multi-level cell (MLC) operation. That is, each programming voltage gives rise to a reproducible change of the threshold voltage, leading to various memory states with good controllability. Figure 5b shows the change in the threshold voltage, i.e., the memory window, as a function of the stress time, resulting in stable program/erase transient characteristics. A robust data retention time and reliable switching endurance are also achieved (Figures 5c and 5d), providing further evidence of the superb controllability of process-induced variability even for the multi-NW FET. These results indeed can have an effect on 3-D integration for high-capacity memory aimed at a low-cost, simple, and fully CMOS-compatible fabrication process. In summary, we demonstrate for the first time a GAA structure-based vertically integrated multi-NW FET which can handle up to five channels. The ORADEP obtained from the optimization of the deep RIE process permitted the formation of uniform multi-NWs, thus reducing the complexity of the process and mitigating stiction failure. The fabrication of such a device is based on a fully CMOS-compatible process, thereby guaranteeing high integrity. Images of the fabricated device, i.e., the vertically integrated five level SiNW-based FET, were acquired with high-resolution TEM. The device exhibited remarkably improved ION drivability


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without a significant degradation of the main parameters, compared to a GAA-based FET with a single SiNW design. These results thus support the good controllability of process-induced variability as well as, the feasibility of this device for versatile applications which may utilize high-performance-based SiNW structures. The demonstration of such a device is meaningful in view of the suppression of the SCE, the enhancement of the performance, and the effective scalability. Furthermore, an application to NVM using the device was successfully introduced with the achievement of stable memory functions such as a large memory window, a robust retention time, and reliable switching endurance. The findings here are expected to be effective with regard to the development of highly integrated 3-D NVM created by means of a fully CMOS compatible process. Thus, this research suggests an optimum configuration for end-ofthe-roadmap devices aimed at versatile future electronics.

Acknowledgments This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2011-0031848). This research was partially supported by the Pioneer Research Center Program through the National Research Foundation of Korea funded by the Ministry of Science, ICT & Future Planning (Grant 20120009594). Supporting Information -

Fabrication process

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Experimental equipment

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Nanowire FETs with performance booster

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GIDL in the VM-FET


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VM-FET with laterally parallel stacks of the nanowire


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Figure Captions Figure 1. Formation of the vertically integrated multi-NW using the ORADEP. (a) Schematic of the ORADEP. The ORADEP realized after the optimization of C4F8-based polymer passivation and SF6-based isotropic dry etching permits the uniform and reproducible formation of vertically integrated multi-NWs, resulting in a simpler and stiction-free process. (b) SEM image of the vertically integrated multi-NW structure formed using the ORADEP. The stiction-free and uniform multi-NW structure supports high reproducibility and low variability of the process. (c) Cross-sectional TEM image along the a-a' direction in Figure 1b. The layers surrounding the SiNW serve as a passivation layer to prevent the physical damage of the device during the focused ion beam (FIB) process for the TEM analysis.

Figure 2. Schematic of the main process and a fabricated device. (a) Schematic of the main fabrication process. The entire process is fully compatible with the silicon-based CMOS process, thereby guaranteeing high completeness of the whole fabrication process. (b) Schematic of the vertically integrated five NW-based FET on a bulk-silicon substrate. Figure 2b includes a crosssectional image along the a-a' (parallel to the gate length) direction and the b-b' (parallel to the NW length) direction of the fabricated device.

Figure 3. TEM image of the fabricated device and results of an analysis of the SiNW. (a) Crosssectional TEM image along the a-a' direction of the fabricated device with thermal oxide for the gate dielectric. The poly-Si surrounding five NWs clearly demonstrates the GAA-based FET with the vertically integrated multi-NW structure. (b) Enlarged image of the SiNW in Figure 3a.


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Nano Letters

The thickness of the thermally grown silicon dioxide (SiO2), which serves as the gate dielectric, is 5 nm. (c) EDS mapping image of the SiNW in Figure 3b. Si and SiO2 are clearly distinguished in Figure 3c via an EDS analysis. (d) High-resolution TEM image of the SiNW. (e) FFT image of the SiNW in Figure 3d. The image of the clear crystalline structure supports the singlecrystallization of the SiNW. (f) Cross-sectional TEM image of the O/N/O gate dielectric-based FET with five vertically integrated five NWs. Five vertically integrated SiNWs with a uniform profile were fabricated with reliable process reproducibility. (g) Enlarged image of the NW with the O/N/O gate dielectric in Figure 3a. The image clearly shows the SONOS configuration for the NVM function, where the thicknesses of the O/N/O are 3 nm, 6 nm, and 8 nm. (h) EDS mapping image of the SiNW with the O/N/O gate dielectric in Figure 3g. Clear classification of each layer is shown in Figure 3h.

Figure 4. I-V characteristics (a) ID-VD characteristic of each FET with single NW and five vertically integrated NWs. LG, WNW, and HNW are a gate length, a nanowire width, and its height, respectively. (b) Comparison of ID at the same operation voltage considering a different threshold voltages of each device. The VM-FET shows that the current drivability is increased by nearly fivefold. (c) ID-VG characteristics of a FET with a single NW and five vertically integrated NWs. Compared to the single NW-based FET, the VM-FET with five channels shows improved performance without significant degradation of any of the other parameters, in this case of the SS and the off-state leakage current. Even for five level stacked multi-NW structure, this result therefore demonstrates good controllability with regard to process variability.


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Figure 5. Nonvolatile memory effect of a SONOS NW-based FET. (a) Memory window for the programing and erase operation. A high memory window of 5 V was obtained from the device, which is suitable for MLC operations. (b) Program and erase transient characteristics. The y-axis on the left shows the VT shift, i.e., the memory window, as a function of the pulse time during the programing operation, while the y-axis on the right shows this characteristic during the erase operation. That is, VPGM and VERS refer to voltage levels for programming and erasing, respectively. (d) Data retention characteristics. The device exhibits an acceptable memory window even above 108 seconds, indicating its suitability for use in NVM applications. (e) The variation of the memory window as a function of iterative program and erase cycles. Reliable switching endurance without SS degradation was achieved in the device.


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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Nano Letters

Figure 1. Formation of the vertically integrated multi-NW using the ORADEP. (a) Schematic of the ORADEP. The ORADEP realized after the optimization of C4F8-based polymer passivation and SF6-based isotropic dry etching permits the uniform and reproducible formation of vertically integrated multi-NWs, resulting in a simpler and stiction-free process. (b) SEM image of the vertically integrated multi-NW structure formed using the ORADEP. The stiction-free and uniform multi-NW structure supports high reproducibility and low variability of the process. (c) Cross-sectional TEM image along the a-a' direction in Figure 1b. The layers surrounding the SiNW serve as a passivation layer to prevent the physical damage of the device during the focused ion beam (FIB) process for the TEM analysis. 155x142mm (300 x 300 DPI)


Nano Letters

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Figure 2. Schematic of the main process and a fabricated device. (a) Schematic of the main fabrication process. The entire process is fully compatible with the silicon-based CMOS process, thereby guaranteeing high completeness of the whole fabrication process. (b) Schematic of the vertically integrated five NW-based FET on a bulk-silicon substrate. Figure 2b includes a cross-sectional image along the a-a' (parallel to the gate length) direction and the b-b' (parallel to the NW length) direction of the fabricated device. 139x109mm (300 x 300 DPI)


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Nano Letters

Figure 3. TEM image of the fabricated device and results of an analysis of the SiNW. (a) Cross-sectional TEM image along the a-a' direction of the fabricated device with thermal oxide for the gate dielectric. The poly-Si surrounding five NWs clearly demonstrates the GAA-based FET with the vertically integrated multi-NW structure. (b) Enlarged image of the SiNW in Figure 3a. The thickness of the thermally grown silicon dioxide (SiO2), which serves as the gate dielectric, is 5 nm. (c) EDS mapping image of the SiNW in Figure 3b. Si and SiO2 are clearly distinguished in Figure 3c via an EDS analysis. (d) High-resolution TEM image of the SiNW. (e) FFT image of the SiNW in Figure 3d. The image of the clear crystalline structure supports the single-crystallization of the SiNW. (f) Cross-sectional TEM image of the O/N/O gate dielectric-based FET with five vertically integrated five NWs. Five vertically integrated SiNWs with a uniform profile were fabricated with reliable process reproducibility. (g) Enlarged image of the NW with the O/N/O gate dielectric in Figure 3a. The image clearly shows the SONOS configuration for the NVM function, where the thicknesses of the O/N/O are 3 nm, 6 nm, and 8 nm. (h) EDS mapping image of the SiNW with the O/N/O gate dielectric in Figure 3g. Clear classification of each layer is shown in Figure 3h. 115x78mm (300 x 300 DPI)


Nano Letters

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Figure 4. I-V characteristics (a) ID-VD characteristic of each FET with single NW and five vertically integrated NWs. LG, WNW, and HNW are a gate length, a nanowire width, and its height, respectively. (b) Comparison of ID at the same operation voltage considering a different threshold voltages of each device. The VM-FET shows that the current drivability is increased by nearly fivefold. (c) ID-VG characteristics of a FET with a single NW and five vertically integrated NWs. Compared to the single NW-based FET, the VM-FET with five channels shows improved performance without significant degradation of any of the other parameters, in this case of the SS and the off-state leakage current. Even for five level stacked multi-NW structure, this result therefore demonstrates good controllability with regard to process variability. 148x124mm (300 x 300 DPI)


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Nano Letters

Figure 5. Nonvolatile memory effect of a SONOS NW-based FET. (a) Memory window for the programing and erase operation. A high memory window of 5 V was obtained from the device, which is suitable for MLC operations. (b) Program and erase transient characteristics. The y-axis on the left shows the VT shift, i.e., the memory window, as a function of the pulse time during the programing operation, while the y-axis on the right shows this characteristic during the erase operation. That is, VPGM and VERS refer to voltage levels for programming and erasing, respectively. (d) Data retention characteristics. The device exhibits an acceptable memory window even above 108 seconds, indicating its suitability for use in NVM applications. (e) The variation of the memory window as a function of iterative program and erase cycles. Reliable switching endurance without SS degradation was achieved in the device. 135x107mm (300 x 300 DPI)


Nano Letters

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Table of Contents 31x12mm (300 x 300 DPI)


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Vertically Integrated Multiple Nanowire Field Effect Transistor - Nano

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