Chemical Imprinting of Crystalline Silicon with Catalytic Metal Stamp in

Dec 10, 2017 - These techniques imprint predefined structures on a stamp to the polymer resist and use the polymer resist as a mask to dry etch the na...
0 downloads 8 Views 4MB Size
Subscriber access provided by READING UNIV

Article

Chemical Imprinting of Crystalline Silicon with Catalytic Metal Stamp in Etch Bath Bugeun Ki, Yunwon Song, Keorock Choi, Jung Hwan Yum, and Jungwoo Oh ACS Nano, Just Accepted Manuscript • DOI: 10.1021/acsnano.7b07480 • Publication Date (Web): 10 Dec 2017 Downloaded from http://pubs.acs.org on December 12, 2017

Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a free service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are accessible to all readers and citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.

ACS Nano is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.

Page 1 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Chemical Imprinting of Crystalline Silicon with Catalytic Metal Stamp in Etch Bath Bugeun Ki1,2, Yunwon Song1,2, Keorock Choi1,2, Jung Hwan Yum3,4 and Jungwoo Oh1,2* 1

School of Integrated Technology, Yonsei University, Incheon 21983, Republic of Korea 2

3

Yonsei Institute of Convergence Technology, Incheon 21983, Republic of Korea

Center for Multidimensional Carbon Materials (CMCM), Institute for Basic Science (IBS), Ulsan 44919, Republic of Korea

4

Department of Chemistry, Ulsan National Institute of Science and Technology (UNIST), Ulsan 44919, Republic of Korea

KEYWORDS: metal-assisted chemical etching, nano/microstructures, lithography, nanoimprint, catalyst, stamp

ABSTRACT: Conventional lithography using photons and electrons continues to evolve to scale down threedimensional (3D) nanoscale patterns, but the complexity of technology and equipment is increasing due to diffraction and scattering problems. Physical contact lithography methods, such as nanoimprint and soft lithography, have been developed as an alternative technique. These techniques imprint predefined structures on a stamp to the polymer resist and use the polymer resist as a mask to dry etch the nanostructure on the substrate. In this study, we introduce a method of chemically imprinting crystalline silicon (Si) with a catalytic stamp to enable the direct etching of the Si without using a polymer mask. A metal catalyst is deposited on the predefined structure of the stamp. The stamp physically contacts the Si in the etching bath, and 1 ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 2 of 20

metal-assisted chemical etching (MaCE) occurs on the semiconductor surface. Since the metal catalyst is mounted on a stamp, it can be used repeatedly. This is a technology that combines conventional lithography and etching without using a polymer resist. This technology not only produced nano/microscale arrays of circular and square holes and trench structures but also successfully produced complex eagle-shaped structures that contained such structures.

Semiconductor devices have been significantly miniaturized to process large amounts of information at high bandwidths. As the operation voltage has been lowered to reduce the power consumption, pitch scales have been decreasing accordingly to maintain the appropriate electric field. Parasitic electrostatic forces result in several challenges in highly scaled-down devices.1 Introducing a three-dimensional (3D) architecture is one way to address these issues and improve electrostatic control.2-5 In addition, a smaller footprint is achieved by introducing 3D structures, resulting in an increase in the fabrication yield and a reduction in the manufacturing cost. As such, the 3D silicon (Si) structure has been gaining increasing importance in the field of semiconductor devices. Conventional photolithography faces feature size limits due to light diffraction and scattering effects. To fabricate highly scaled semiconductors, it is necessary to continuously improve the lithography technologies. A photolithography process involving extreme ultraviolet (EUV) wavelengths has emerged as a next-generation technology, and researchers have been actively developing techniques to produce a suitable source power and photomask.6-8 Maskless writing methods such as electron beam (E-beam) lithography are capable of high-resolution patterning911

. However, meeting industrial requirements for the fabrication of 3D Si structures using these

processes has been challenging owing to the cost of the complex processes, including multiple photolithography and etching steps, which require expensive equipment. Photolithography requires several components, such as the optical mask and light-sensitive photoresist, and several steps, including chemical treatment and etching. Alternative lithography techniques have been proposed to reduce manufacturing costs while maintaining high resolution. Physical contact-based patterning is a simple process that can generate nanoscale patterns.12-15 Nanoimprint lithography (NIL) creates nanoscale patterns over a wide area with low cost, high throughput, and high resolution.16-18 NIL directly imprints 2 ACS Paragon Plus Environment

Page 3 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

nanostructures from a stamp on a polymer resist by a combination of heat and pressure. This technique has triggered a great deal of interest from the scientific and technical communities. NIL is a mechanical technique that relies on the one-to-one master template that is replicated in the imprinting process. Another technique, soft lithography, provides gentle contact between a stamp and substrate.19-22 An elastomeric stamp is fabricated by casting a liquid polymer precursor onto a master. The mechanical properties of the stamp are critical to its ability to transfer a pattern with high fidelity. The stamp is inked with a liquid solution containing functional molecules, and the ink is transferred from the stamp to the substrate. With these techniques, a predefined pattern is imprinted on the polymer resist. Dry etching fabricates the nanoscale structure using the polymer resist as a mask. Reactive-ion etching (RIE) is generally used for dry etching, because it has good process control over fine patterns with high aspect ratios. However, accelerating plasma ions can cause defects in semiconductor surfaces. Vacuum systems, including gas cabinets and scrubbers for toxic gas handling, increase overall process complexity. As an alternative to this technique, metal-assisted chemical etching (MaCE) has often been considered along with lithography.23-26 As a chemical etching technique, MaCE is advantageous, as it provides anisotropic etching profiles without generating surface damage.27-30 Moreover, it obviates the need for high-investment facilities such as vacuum equipment or gas installations, as the process can be conducted with patterned metal catalysts in etch baths, thereby reducing the processing costs.31-33 Attempts to combine physical contact-based patterning with cost-effective wet etching have led to the development of superionic solid-state stamping (S4)-MaCE,13-14, 34 a simple and repeatable approach using a Ag2S stamp followed by MaCE to pattern the Ag film deposited on a Si substrate. However, S4-MaCE consists of two separate processes—patterning and etching—and requires an extra step to remove the remaining noble metal catalyst used for the catalysts. Thus, the processing costs increase with the costs of the metal catalysts to be removed. If the patterning and etching processes mentioned above were integrated into a single-step process that provides reproducibility, simplicity, and anisotropy without costly equipment, it would be the ideal 3D semiconductor manufacturing method. Thus, in this work, we describe a stamp-based, repeatable, single-step MaCE process called “chemical imprinting” for 3D semiconductor fabrication for a variety of applications. Chemical imprinting consists of only one step, as shown in Figure 1, for lithography and etching. Topological patterns are formed on a 3 ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 4 of 20

material to be used as a stamp by using conventional photolithography and dry etching. A metal catalyst (e.g., Au, Pt, Ag, Cu, Pd, Ni) is deposited on these patterns in the stamp via physical vapor deposition. The stamp is physically pressed on the crystalline Si substrate (100) in the etch bath. The mirror-symmetric patterns in the stamp are chemically imprinted on the Si. The stamp is then released from the substrate and recycled for subsequent chemical imprinting. The technique suggested in this study does not require either photomasks for lithography or polymer resists for subsequent etching. It is a rather method that involves simultaneous lithography and etching carried out via physical contact and a chemical reaction between the stamp and the semiconductor. While conventional MaCE is a one-time process that requires the removal of the metal catalyst after etching, chemical imprinting with stamp MaCE reuses the metal catalyst, because the metal catalyst is mounted on a stamp.

Figure 1. Schematic illustration of chemical imprinting of crystalline Si, which conducts lithography and etching simultaneously via catalytic metal stamp for nano/microstructure fabrication.

Results and Discussion Figure 2 illustrates the stamp-etching mechanisms at the catalyst–Si interface. The etching occurs when the metal catalyst is pressed on the Si substrate in the etch bath composed of an acid (HF), an oxidant (H2O2), and a buffer solution (H2O). The etching solution was composed of hydrofluoric (HF) acid, hydrogen peroxide (H2O2), and deionized (DI) water with the volumetric ratio of 10 : 1 : 20, and chemical imprinting was conducted at room temperature. Holes (h+) are generated in the process of the reduction of H2O2 to H2O by the metal catalyst (Au) on the stamp. 4 ACS Paragon Plus Environment

Page 5 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

The generated holes (h+) are transported through the Au and then injected into the Si. Si is oxidized by the injected holes (h+) and dissolved in the form of the product (SiF62-) by the reactant (HF). Stamp etching occurs in the contact area between the catalyst and Si and causes anisotropic etching in the vertical direction. However, mass transport is limited, as chemical imprinting progresses in the vertical direction, so the aspect ratio is not as high as that obtained from conventional MaCE. As in the case of conventional MaCE, if the chemical reaction is a limiting process as compared to the mass transfer, excessive h+ injection into the Si in the lateral direction can result in isotropic etching characteristics. After being released from the Si substrate, the stamp can be recycled to replicate identical patterns on another Si substrate. Another advantage is that the catalysts, which are usually noble metals, can be used multiple times, thus reducing the processing costs. We chose the Si substrate as a stamping material for nano/micropatterns with aspect ratios greater than 1 in this study and fabricated them with conventional lithography and dry etching. For repeated use of the stamp, a passivation layer was required to prevent the injection of holes (h+) and the etching solution into the stamp rather than the Si substrate. A 100 nm-thick fluorocarbon was used as a protective layer, and it was not damaged when it was immersed in the etch bath for hours. On the other hand, when other polymers and metals were used as passivation layers, they were stripped from the stamp within a few minutes. A fluorocarbon inserted between the stamp material and the metal catalyst served as an effective electric/chemical barrier against the injection of holes and HF into the stamp material.

5 ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 6 of 20

Figure 2. Schematic illustration of chemical imprinting mechanism. The etching occurs as follows: 1) H2O2 is reduced to H2O by the metal catalyst in the etch bath. The holes diffuse through the metal and are injected into the Si. 2) HF dissolves the oxidized Si substrates. After the chemical reaction, the ionized products diffuse out through the gap between the stamp and the Si. A fluorocarbon inserted between the stamp material and the metal catalyst serves as an effective electric/chemical barrier. Figure 3 demonstrates the stamps (A-1, B-1, C-1, and D-1) and 3D structures (A-2, B-2, C-2, and D-2) mirror-symmetrically imprinted on the Si substrates for 30 min. The patterns used in chemical imprinting include (A) a circular pillar array with a 600-nm diameter and 2-µm space, (B) a square pillar array with a 1-µm length and 1-µm space, and (C) a rectangular array with a 1-µm width and 1-µm space. In these open structures, reactants (HF) and products (SiF62-) can access all regions of the patterns. A pattern featuring a curved loop structure that did not allow the free movement of the solution and byproducts was also demonstrated (D). All the metal stamps successfully etched the identical patterns on the Si substrates. Holes, trenches, dots, and curved lines were clearly imprinted. Figures A-3, B-3, and C-3 show the cross-section after chemical imprinting and etched depths are 1760 nm, 400 nm, and 260 nm, respectively. A pattern having a width wider than that of the stamp was formed on the Si by this technique. 6 ACS Paragon Plus Environment

Page 7 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Catalyst metal on sidewalls may inject excessive holes into lateral Si as the stamp descends into the substrate. In particular, Figure A-3 shows that the Si substrate was imprinted with the circular pillars to form circular holes having an aspect ratio of about 3:1. They are distinctly different from previous results that simply left traces of the pattern on the substrate. Figure D-2 shows the complex results of an eagle head imprinted with continuous curves and dots. This particular pattern consists of a closed structure where the contact between the stamp and the substrate can limit the mass transport of the etching solution and byproducts. However, the etching was successful, presumably because mass transport occurred through the gap between the stamp and the substrate. This shows that not only an array structure of a single pattern but also various patterns of irregular shapes can be imprinted on a Si substrate.

7 ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 8 of 20

Figure 3. Stamps and nano/microstructures mirror-symmetrically imprinted on Si after etching for 30 min. The stamp patterns include (A-1) a circular pillar array, (B-1) a square pillar array, (C-1) a rectangular array, and (D-1) a mixed pattern consisting of curved lines and dots. 3D structures were imprinted on Si substrates as (A-2) a circular hole array, (B-2) a square hole array, (C-2) a rectangular trench array, and (D-2) an eagle head mixed pattern consisting of a closed-curve trench. The depths of the etched patterns are approximately (A-3) 1760 nm, (B-3) 400 nm (53° tilted from top view), (C-3) 260 nm and (D-2) 120 nm. The eagle emblem of Yonsei University is printed with permission from Yonsei University. Figure 4 shows a Transmission electron microscopy (TEM) image of the trench after the chemical imprinting of Si. All three parts inside the trench show sharp atomic arrays. The lattice spacing of the (001) and (110) planes remained 0.54 nm and 0.38 nm, respectively. This is consistent with the d-spacing plane of single-crystalline Si. After the imprinting, the high-quality single crystals remained undamaged without distortion or defects. The fast Fourier transform (FFT) patterns in the insets also confirm the feasibility of using single-crystalline Si. Conventional MaCE of Si tends to leave porous Si on the surface due to hole accumulation and uneven etching, which was not the case in our study. Porous Si was previously reported to be an essential transport path of reactants and products for chemical etching35. Stamp etching was demonstrated with porous Si, and single-crystalline Si was difficult to etch36-40. However, our results clearly confirmed that this chemical imprinting was possible with single-crystalline Si. It was also evident that the porous region was not a prerequisite and that high-quality singlecrystalline Si remained without porosity.

8 ACS Paragon Plus Environment

Page 9 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Figure 4. Cross-sectional TEM images of imprinted trench in crystalline Si (100). The surface at three points showed single-crystalline Si, and the measured lattice spacings of the (001) and (110) planes were 0.54 nm and 0.38 nm, which correspond to each d-spacing plane. Insets are FFT images on the Si surface. Figure 5 shows the scanning electron microscope (SEM) images of (A) the Si surface morphologies according to the etching time and (B) the corresponding schematic mechanisms. A 5 × 5-µm2 stamp was used. At the beginning of the imprinting, the stamp and the Si substrate were in contact with each other over the whole area. Etching occurred from the edge of the contact between the metal stamp and the Si substrate. The edge of the substrate showed a somewhat irregularly etched surface, and the center remained unetched. As time increased, etching proceeded to the center of the Si. Finally, the entire Si surface in contact with the metal 9 ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 10 of 20

catalyst was completely etched to a depth of 160 nm and remained flat with an RMS roughness of 18.421 nm. In conventional MaCE, it is generally known that the etching begins at the edge of the contact area between the metal catalyst and the Si substrate exposed to the etching solution. Since the mass transport rate of reactants and products for etching is higher at the edges, MaCE occurs more rapidly at the edges than at the center. Thus, the non-uniformity of the etching causes the metal catalyst and the etched Si surface to tend to undergo microscale bending41. This has been a potential problem in manufacturing various types of semiconductor structures. However, even when a microscale metal catalyst was used, stamp etching could provide a flat surface in the etched region of the Si substrate without bending. This is because etching stops or becomes extremely slow at the already-etched Si surface separated from the metal catalyst of the stamp, and it continues at the center where the Si surface is still in contact with the metal catalyst. When the center area is completely etched, the contact between the stamp and the Si substrate is restored as before, and the etching process is repeated. Therefore, this method solves the bending problem of the microscale metal catalyst and Si etching regions, thereby resulting in a flat etched surface.

Figure 5. (A) SEMs of Si surface and (B) corresponding imprinting. At the early stage, the etching begins from the edge area of the square pattern. Then, the etched Si surface at the edge area and the metal catalyst on the stamp pattern are separated, and reactants and products are transported through the spaces. While the etching stops or slows down in the edge areas where holes are not injected, the injected holes and the diffused reactants cause etching in the central 10 ACS Paragon Plus Environment

Page 11 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

area. After sufficient etching of the center area, the flat etched Si surface comes in contact with the metal catalyst, and the etching is repeated. Mass transport of reactants and products is generally known to occur only through porous layers formed during conventional MaCE, because there is no space between the metal catalyst and the substrate35. However, in this stamp etching, the separation of the already-etched Si surface and the metal catalyst provides a space between the substrate and the metal catalyst. Through the space connecting the center area and the edge area of the pattern, reactants and products can be freely transported in and out. Hence, the mass transport of reactants and products does not necessarily require the formation of porous layers. Due to the fixed nature of the metal catalyst on the stamp, this chemical imprinting has several advantages in addition to the flat surface after etching described above. Multilevel patterns in the stamp can be imprinted on the Si as in grayscale lithography. Figure 6 shows SEM images of (A) nano/micropatterns with different bridge heights connecting the pillars and (B) 3D structures imprinted on the Si after etching for 30 min. Figure 6(C) is an atomic force microscope (AFM) image of the etched multilevel Si structure showing the height difference between the pillars and the bridges. Holes with a depth of 0.6 µm are hexagonally imprinted, and trenches with a height of 0.3 µm connect these holes. These results demonstrate that not only 2D patterns but also 3D patterns can be efficiently replicated using this approach.

Figure 6. Fabrication of multilevel structures. (A) 30°-tilted SEM image of a polymer-based multilevel stamp consisting of hexagonally arranged pillars and relatively low-height bridges connecting the pillars. (B) Hexagonally arranged circular holes (0.6 µm) and relatively low-depth trenches (0.2 µm) connecting the holes after the chemical imprinting for 30 min. (C) AFM image and profile showing 0.3-um depth difference between holes and trenches. 11 ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 12 of 20

Figure 7 shows a stamp of a complex shape and a Si substrate imprinted with this shape. The predefined pattern on the stamp consists of several micro/nano-unit patterns. Optical microscope photography shows the precise school emblem, the YONSEI eagle, on a 1x1-cm2 stamp, which was manufactured by direct writing lithography and subsequent processes. This complex structure containing multiple unit patterns is well imprinted on a Si substrate after etching for 30 min. The emerging coloration in the imprinted Si is a form of structural coloration by diffraction grating of the periodic structure, suggesting that it can be applied to various optical applications.

Figure 7. Optical microscope photography of (A) stamp of complex eagle shape and (B) 1x1cm2 Si substrate imprinted with this shape. Predefined patterns in (A) manufactured by direct writing lithography and subsequent processes. Mirror-symmetrical patterns in (B) chemically imprinted on Si substrates for 30 min. The eagle emblem of Yonsei University is printed with permission from Yonsei University.

Figure 8 shows SEM images of (A) the stamp and (B) the Si substrates. In Figure 8 (A), the eagle shape was well defined in the stamp and composed of numerous letters in the word YONSEI. Each letter in the word YONSEI consists of an array of individual patterns that were used in preliminary experiments. In higher resolution SEMs, we can see each letter clearly defined. Y and S are composed of circular pillar arrays, O is composed of curved lines, E is composed of straight lines, and N and I are composed of stripe arrays. Figure 8 (B) shows the eagle shapes mirror-symmetrically imprinted on the Si substrates after etching for 30 min. Of course, they were not as clear as the predefined patterns on the stamp, but the overall patterns chemically imprinted on the Si were well maintained. In part, the circular pillar arrays, curved lines, and straight lines that constituted the word YONSEI on the stamp 12 ACS Paragon Plus Environment

Page 13 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

were well transferred to the Si substrate with a periodic structure of circular dots, curved lines, and straight trenches. The results show that this technique can be used repeatedly in large areas. In addition, the imprinting of virtually any shape is possible, suggesting that it can be used in a variety of electronics and photonics applications.

13 ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Figure 8. SEM images of (A) stamps of complex eagle shape consisting of numerous letters in the word YONSEI with circular pillars, rectangular stripes, and closed-curve mixed patterns and (B) Si substrates’ mirror-symmetric patterns imprinted with hole arrays, trench arrays, and curved lines. The eagle emblem of Yonsei University is printed with permission from Yonsei University. Conclusion We demonstrated a chemical imprinting method to fabricate various types of Si nano/microstructures. Various 3D Si structures consisting of circular/square holes and rectangular/curved-loop trenches were imprinted on the Si substrates using a metal catalystcoated stamp in a chemical etch bath. When the stamp was continuously pressed in the direction of the substrate, the metal catalyst attached to the stamp maintained contact with the substrate. The aspect ratio of the pattern etched on the Si was not as large as the aspect ratio of the stamp 14 ACS Paragon Plus Environment

Page 14 of 20

Page 15 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

pattern, but it was found to be about 3 : 1 on the circular hole array. However, when this technique was used to imprint complex patterns, the Si was not etched with a high aspect ratio, as in conventional metal-assisted chemical etching. Mass transport was limited in complex structures as chemical imprinting proceeded into the substrates. If etching did not occur at any point of the stamp, etching stopped completely, and a high aspect ratio could not be obtained. Low aspect ratios were obtained in stamps of complex patterns. Unlike conventional MaCE of the Si, which caused the metal catalyst to bend on the micrometer scale and the etched Si surface to form a porous region, this chemical imprinting maintained a flat and crystalline Si lattice. Multilevel Si structures were fabricated in a single step by using a grayscale stamp. Large, complex eagle-shaped stamps were repeatedly imprinted on the Si substrates. The results suggest that this chemical imprinting method will facilitate academic and industrial research on nanostructures and their applications.

Experimental Section Stamp Preparation. We used boron-doped p-Si (100) substrates with a resistivity in the range of 5 to 30 Ω·cm for fabricating the stamp. Direct writing and contact aligner photolithography were used to define various photoresist patterns on the Si substrates. The patterned Si substrates were deep dry etched with halocarbon-based plasmas and carbon halogen radicals in the inductively coupled plasma reactive-ion etcher (ICP-RIE). For anisotropic profiles, a pulsed etching process (Bosch process) was applied to the etching with sulfur hexafluoride gas (SF6) and octafluorocyclobutane gas (C4F8) plasma at 600 W. A fluorocarbon was polymerized on the vertical faces of the Si structures. The so-called scalloping effect was observed on the pillar patterns. Polymer resist and fluorocarbon were removed using a plasma asher at 200 W for 5 min, followed by sonication in acetone, IPA, and DI water for 5 min each. The 100 nm-thick fluorocarbon passivation was then performed to the stamp for passivation using octafluorocyclobutane gas (C4F8) plasma at 600 W for 30 s. To improve the adhesion for the metal catalysts, 50 nm Cr was sputtered on a fluorocarbon passivation layer42, and 100 nm Au catalyst was in situ sputtered on a Cr layer. The Au layer thickness exceeded 20–40 nm to prevent metal tearing during contact with the substrate. Multilevel Stamp Preparation. The multilevel pattern was fabricated on the p-Si using the contact aligner. The distance between the stamp and the photomask was adjusted to induce 15 ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 16 of 20

interference of patterns, and the bridge patterns connecting the hexagonally arranged circular pillars were formed. The deposition of the barrier, adhesion, and metal catalyst layers was performed as described in the Stamp Preparation section. Chemical Imprinting. Before chemical imprinting, the Si substrates were pre-cleaned via sonication using acetone, IPA, and DI water for 5 min each. Native oxide was removed in buffered oxide etchant (BOE) and DI water for 1 min. We used a jig to bring the stamp into contact with the Si in the etch bath. The stamp was pressed on the Si in the etch bath, which was composed of HF (48% wt), H2O2 (30% wt.), and DI water with the volumetric ratio of 10:1:20, respectively. MaCE occurred at the interface between the stamp and the semiconductor surface. MaCE solutions included an oxidizing agent (e.g., H2O2, HNO3, KMnO4) and an acid (e.g., HF, H2SO4). Holes (h+) were produced by the catalytic reaction of an oxidizing agent and a metal catalyst. These holes were injected into the Si substrate through metal–substrate contact to oxidize and dissolve the substrate. The jig was manually operated to align the stamp with the Si substrate in the etch bath. The mechanical load of the jig was measured as 50 N using a torque meter. After a certain amount of time, the jig was loosened to release the Si substrate and the stamp. The Si substrate was rinsed immediately in DI water for 5 min and dried with N2.

ASSOCIATED CONTENT Supporting Information An image of prototype tool used for the chemical imprinting; CAD image of eagle-shaped pattern; Different passivation layer test; SEM images of the circular pillars that consist of the stamp patterns; The AFM image of chemically imprinted 5x5 µm2 square pattern on Si; In-plane mass transport induced unflatten large area pattern; Tracing the exact position of particular etched pattern after multiple usage of stamp;

AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] 16 ACS Paragon Plus Environment

Page 17 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

Author Contributions B. Ki and J. Oh developed the original ideas. B. Ki, J. H. Yum, and J. Oh contributed to the paper writing. B. Ki carried out most of the experimental work. Y. Song and K. Choi assisted with some experiments and data analysis.

ACKNOWLEDGMENT This research was supported by the MSIT(Ministry of Science and ICT), Korea, under the ICT Consilience Creative program(IITP-2017-2017-0-01015) supervised by the IITP(Institute for Information & communications Technology Promotion). This research was also supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science, and Technology (2016R1D1A1A09918647).

REFERENCES

1. Taur, Y. CMOS Design Near the Limit of Scaling. IBM J. Res. Dev. 2002, 46, 213-222. 2. Bin, Y.; Leland, C.; Ahmed, S.; Haihong, W.; Bell, S.; Chih-Yuh, Y.; Tabery, C.; Chau, H.; Qi, X.; Tsu-Jae, K.; et al. In FinFET Scaling to 10 nm Gate Length; Digest. International Electron Devices Meeting, 2002; pp 251-254. 3. Colinge, J. P. Multiple-Gate SOI MOSFETs. Solid-State Electron. 2004, 48, 897-905. 4. Lin, C.-H.; Chang, J.; Guillorn, M.; Bryant, A.; Oldiges, P.; Haensch, W. In Non-Planar Device Architecture for 15nm Node: FinFET or Trigate?; SOI Conference (SOI); 2010 IEEE International, IEEE: 2010; pp 1-2. 5. Song, Y.; Mohseni, P. K.; Kim, S. H.; Shin, J. C.; Ishihara, T.; Adesida, I.; Li, X. L. Ultra-High Aspect Ratio InP Junctionless FinFETs by a Novel Wet Etching Method. IEEE Electron Device Lett. 2016, 37, 970-973. 6. Bjorkholm, J. E. EUV Lithography—the Successor to Optical Lithography. Intel Technology Journal 1998, 3, 98. 7. Wagner, C.; Harned, N. EUV Lithography: Lithography Gets Extreme. Nat. Photonics 2010, 4, 24-26. 8. Hadrich, S.; Klenke, A.; Rothhardt, J.; Krebs, M.; Hoffmann, A.; Pronin, O.; Pervak, V.; Limpert, J.; Tunermann, A. High Photon Flux Table-Top Coherent Extreme-Ultraviolet Source. Nat. Photonics 2014, 8, 779-783. 9. Tseng, A. A.; Chen, K.; Chen, C. D.; Ma, K. J. Electron Beam Lithography in Nanoscale Fabrication: Recent Development. IEEE Trans. Electron. Packag. 2003, 26, 141-149. 17 ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 18 of 20

10. Manfrinato, V. R.; Zhang, L.; Su, D.; Duan, H.; Hobbs, R. G.; Stach, E. A.; Berggren, K. K. Resolution Limits of Electron-Beam Lithography Toward the Atomic Scale. Nano Lett. 2013, 13, 1555-1558. 11. Chen, Y. Nanofabrication by Electron Beam Lithography and Its Applications: A Review. Microelectron. Eng. 2015, 135, 57-72. 12. Chou, S. Y.; Krauss, P. R.; Renstrom, P. J. Nanoimprint Lithography. J. Vac. Sci. Technol. B 1996, 14, 4129-4133. 13. Hsu, K. H.; Schultz, P. L.; Ferreira, P. M.; Fang, N. X. Electrochemical Nanoimprinting with Solid-State Superionic Stamps. Nano Lett. 2007, 7, 446-451. 14. Kumar, A.; Hsu, K. H.; Jacobs, K. E.; Ferreira, P. M.; Fang, N. X. Direct Metal NanoImprinting Using an Embossed Solid Electrolyte Stamp. Nanotechnology 2011, 22, 155302. 15. Garcia, R.; Knoll, A. W.; Riedo, E. Advanced Scanning Probe Lithography. Nat Nanotechnol. 2014, 9, 577-587. 16. Guo, L. J. Nanoimprint Lithography: Methods and Material Requirements. Adv. Mater. 2007, 19, 495-513. 17. Kooy, N.; Mohamed, K.; Pin, L. T.; Guan, O. S. A Review of Roll-to-Roll Nanoimprint Lithography. Nanoscale Res. Lett. 2014, 9, 320. 18. Shim, W.; Braunschweig, A. B.; Liao, X.; Chai, J.; Lim, J. K.; Zheng, G.; Mirkin, C. A. Hard-Tip, Soft-Spring Lithography. Nature 2011, 469, 516-520. 19. Xia, Y. N.; Whitesides, G. M. Soft Lithography. Annu. Rev. Mater. Sci. 1998, 28, 153184. 20. Odom, T. W.; Love, J. C.; Wolfe, D. B.; Paul, K. E.; Whitesides, G. M. Improved Pattern Transfer in Soft Lithography Using Composite Stamps. Langmuir 2002, 18, 5314-5320. 21. Rogers, J. A.; Nuzzo, R. G. Recent Progress in Soft Lithography. Mater. Today 2005, 8, 50-56. 22. Qin, D.; Xia, Y. N.; Whitesides, G. M. Soft Lithography for Micro- and Nanoscale Patterning. Nat. Protoc. 2010, 5, 491-502. 23. Li, X.; Bohn, P. Metal-Assisted Chemical Etching in HF/H2O2 Produces Porous Silicon. Appl. Phys. Lett. 2000, 77, 2572-2574. 24. Huang, Z. P.; Geyer, N.; Werner, P.; de Boor, J.; Gosele, U. Metal-Assisted Chemical Etching of Silicon: A Review. Adv. Mater. 2011, 23, 285-308. 25. Azeredo, B. P.; Sadhu, J.; Ma, J.; Jacobs, K.; Kim, J.; Lee, K.; Eraker, J. H.; Li, X.; Sinha, S.; Fang, N.; et al. Silicon Nanowires with Controlled Sidewall Profile and Roughness Fabricated by Thin-Film Dewetting and Metal-Assisted Chemical Etching. Nanotechnology 2013, 24, 225305. 26. Balasundaram, K.; Mohseni, P. K.; Shuai, Y. C.; Zhao, D. Y.; Zhou, W. D.; Li, X. L. Photonic Crystal Membrane Reflectors by Magnetic Field-Guided Metal-Assisted Chemical Etching. Appl. Phys. Lett. 2013, 103, 214103. 27. DeJarld, M.; Shin, J. C.; Chern, W.; Chanda, D.; Balasundaram, K.; Rogers, J. A.; Li, X. Formation of High Aspect Ratio GaAs Nanostructures with Metal-Assisted Chemical Etching. Nano Lett. 2011, 11, 5259-5263. 28. Kim, J.; Han, H.; Kim, Y. H.; Choi, S.-H.; Kim, J.-C.; Lee, W. Au/Ag Bilayered Metal Mesh as a Si Etching Catalyst for Controlled Fabrication of Si Nanowires. ACS Nano 2011, 5, 3222-3229. 29. Song, Y.; Oh, J. Thermally Driven Metal-Assisted Chemical Etching of GaAs with InPosition and Out-of-Position Catalyst. J. Mater. Chem. A 2014, 2, 20481-20485. 18 ACS Paragon Plus Environment

Page 19 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

ACS Nano

30. Kim, J.; Oh, J. Formation of GaP Nanocones and Micro-Mesas by Metal-Assisted Chemical Etching. Phys. Chem. Chem. Phys. 2016, 18, 3402-3408. 31. Song, Y.; Ki, B.; Choi, K.; Oh, I.; Oh, J. In-Plane and Out-of-Plane Mass Transport during Metal-Assisted Chemical Etching of GaAs. J. Mater. Chem. A 2014, 2, 11017-11021. 32. Kim, S. H.; Mohseni, P. K.; Song, Y.; Ishihara, T.; Li, X. L. Inverse Metal-Assisted Chemical Etching Produces Smooth High Aspect Ratio InP Nanostructures. Nano Lett. 2015, 15, 641-648. 33. Kim, J. D.; Mohseni, P. K.; Balasundaram, K.; Ranganathan, S.; Pachamuthu, J.; Coleman, J. J.; Li, X. Scaling the Aspect Ratio of Nanoscale Closely Packed Silicon Vias by MacEtch: Kinetics of Carrier Generation and Mass Transport. Adv. Funct. Mater. 2017, 27, 1605614. 34. Chern, W.; Hsu, K.; Chun, I. S.; de Azeredo, B. P.; Ahmed, N.; Kim, K. H.; Zuo, J. M.; Fang, N.; Ferreira, P.; Li, X. L. Nonlithographic Patterning and Metal-Assisted Chemical Etching for Manufacturing of Tunable Light-Emitting Silicon Nanowire Arrays. Nano Lett. 2010, 10, 1582-1588. 35. Geyer, N.; Fuhrmann, B.; Huang, Z. P.; de Boor, J.; Leipner, H. S.; Werner, P. Model for the Mass Transport during Metal-Assisted Chemical Etching with Contiguous Metal Films As Catalysts. J. Phys. Chem. C 2012, 116, 13446-13451. 36. Azeredo, B. P.; Lin, Y.-W.; Avagyan, A.; Sivaguru, M.; Hsu, K.; Ferreira, P. Direct Imprinting of Porous Silicon via Metal-Assisted Chemical Etching. Adv. Funct. Mater. 2016, 26, 2929-2939. 37. Zhang, J.; Zhang, L.; Han, L. H.; Tian, Z. W.; Tian, Z. Q.; Zhan, D. P. Electrochemical Nanoimprint Lithography: when Nanoimprint Lithography Meets Metal Assisted Chemical Etching. Nanoscale 2017, 9, 7476-7482. 38. Zhang, J.; Zhang, L.; Wang, W.; Han, L. H.; Jia, J. C.; Tian, Z. W.; Tian, Z. Q.; Zhan, D. P. Contact Electrification Induced Interfacial Reactions and Direct Electrochemical Nanoimprint Lithography in N-Type Gallium Arsenate Wafer. Chem. Sci. 2017, 8, 2407-2412. 39. Zhang, L.; Zhang, J.; Yuan, D.; Han, L. H.; Zhou, J. Z.; Tian, Z. W.; Tian, Z. Q.; Zhan, D. P. Electrochemical Nanoimprint Lithography Directly on N-Type Crystalline Silicon (111) Wafer. Electrochem. Commun. 2017, 75, 1-4. 40. Torralba, E.; Halbwax, M.; El Assimi, T.; Fouchier, M.; Magnin, V.; Harari, J.; Vilcot, J. P.; Le Gall, S.; Lachaume, R.; Cachet-Vivier, C.; et al. 3D Patterning of Silicon by Contact Etching with Anodically Biased Nanoporous Gold Electrodes. Electrochem. Commun. 2017, 76, 79-82. 41. Choi, K.; Song, Y.; Oh, I.; Oh, J. Catalyst Feature Independent Metal-Assisted Chemical Etching of Silicon. RSC Adv. 2015, 5, 76128-76132. 42. Chang, C. A.; Kim, Y. K.; Schrott, A. G. Adhesion Studies of Metals on Fluorocarbon Polymer-Films. J. Vac. Sci. Technol. A 1990, 8, 3304-3309.

19 ACS Paragon Plus Environment

ACS Nano 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 20 of 20

ToC

20 ACS Paragon Plus Environment