Development of Fully Printed Electrolyte Gated Oxide Transistors

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Development of Fully Printed Electrolyte Gated Oxide Transistors using Graphene Passive Structures Surya Abhishek Singaraju, Tessy T. Baby, Felix Neuper, Robert Kruk, Jasmin Aghassi Hagmann, Horst Hahn, and Ben Breitung ACS Appl. Electron. Mater., Just Accepted Manuscript • DOI: 10.1021/acsaelm.9b00313 • Publication Date (Web): 15 Jul 2019 Downloaded from pubs.acs.org on July 19, 2019

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ACS Applied Electronic Materials

Development of Fully Printed Electrolyte Gated Oxide Transistors using Graphene Passive Structures

Surya Abhishek Singaraju*,a, Tessy Theres Babya, Felix Neupera, Robert Kruka, Jasmin Aghassi Hagmanna,b, Horst Hahna,c, Ben Breitung*,a,d

a Institute of Nanotechnology, Karlsruhe Institute of Technology, Hermann-von-

Helmholtz-Platz 1, 76344 Eggenstein-Leopoldshafen, Germany

b Department of Electrical Engineering and Information Technology, Offenburg

University of Applied Science, Offenburg 77652, Germany

c KIT-TUD Joint Research Laboratory Nanomaterials Institute of Materials Science,

Technische Universität Darmstadt (TUD), Darmstadt 64287, Germany

ACS Paragon Plus Environment

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ACS Applied Electronic Materials 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

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d Karlsruhe Nano Micro Facility, Karlsruhe Institute of Technology, Hermann-von-

Helmholtz-Platz 1, 76344 Eggenstein-Leopoldshafen, Germany

corresponding author(s): [email protected], [email protected]

Abstract

During the past decade to the present time, the topic of printed electronics has gained a lot of attention for their potential use in a number of practical applications, including biosensors, photovoltaic devices, RFIDs, flexible displays, large-area circuits etc. To fully realize printed electronic components and devices, effective techniques for the printing of passive structures and electrically and chemically compatible materials in the printed devices need to be developed first. The opportunity of using electrically conducting graphene inks will enable the integration of passive structures into active devices, as for


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example, printed electrolyte-gated transistors (EGTs). Accordingly, in this study, we present the parametric results obtained on fully-printed electrolyte-gated transistors having graphene as the passive electrodes, and an inorganic oxide semiconductor as the active channel, and a composite solid polymer electrolyte (CSPE) as the gate insulating material. This configuration offers high chemical and electrical stability while at the same time allowing EGT operation at low potentials, implying the distinct advantage of operation at low input voltages. The printed in-plane EGTs we developed exhibit excellent performance with device mobility up to 16 cm2V-1s-1, an ION/IOFF ratio of 105, with a subthreshold slope of 120 mVdec-1.

KEYWORDS: Fully printed, graphene electrodes, oxide semiconductor, electrolyte-gated,

contact resistance, electrolyte-gated transistor (EGT) mobility


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Introduction

With the advent of the “Internet of Things” (IoT), it is expected that soon the demand for about a billion flexible and wearable sensors per day is expected1. To be well prepared for meeting this need, there is an ongoing intense search to find cost-effective methods, materials, and simple, scalable printing procedures for fabricating electronics. Direct, additive processes such as

screen printing, gravure printing, ink-jet printing or

microplotting are suitable manufacturing techniques for printed devices and they already are being utilized for various applications, e.g., bio-sensing2,3, medical applications4, circuit applications5, LEDs6,7, and photovoltaics8. One of the major advantages of printed electronics is the possibility of low temperature fabrication of device components. Conventional processes, requiring high temperature and/or high vacuum techniques in order to produce these components, cannot be used to make electronics on flexible substrates such as polymers. Therefore, to develop and fabricate printed electronic


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circuits, materials and techniques that are suitable for low vacuum and low temperature processing must be found. Since transistors are the backbone of most electric circuits, printed transistor types, instead of hybrid versions (composed of a combination of brittle pre-patterned structures and printed parts), need to be designed, developed, and fabricated. At present time, the number of reports regarding appropriate printable passive structures is still rather limited, especially for electrolyte gated transistors (EGTs)9,10. Printing passive structures includes the printing of the source, drain, and the gate electrodes of a transistor. With regard to conductivity, metal electrodes would be the preferred choice. However, they are usually deposited by thermal evaporation11 or photolithography12 processes but not printed. Even if printed, a high contact resistance at the metal-semiconductor interface leads to a lower electrical compatibility between the metal and the semiconductor13. Nevertheless, recently, studies about a certain compatibility between silver and oxide semiconductor have been published14,15. However, in addition to the above mentioned disadvantage, silver is not compatible with the electrolyte, due to the ensuing undesirable chemical reactions during operation that facilitate metal migration. Therefore, instead of metals, conductive oxides such as indium


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tin oxide (ITO) are used as electrode material for n-type oxide semiconductors because they are chemically and electrically stable. However, one of their drawbacks is the fact that they are usually lithographically processed16 as well. Notwithstanding these disadvantages, it has been reported that solution processed ITO inks have been used to fabricate EGTs17. However, this fabrication technique requires sintering at high temperatures (up to 500°C) in order to obtain low sheet resistances. Consequently, the technique precludes the usage of flexible substrates. In this regard, a possible printable electrode material is graphene, which has been shown to exhibit high conductivity and chemical stability18 and it can be also processed at low temperatures19. Previously, graphene was generally deposited via CVD methods

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and widely known

for its role as a semiconductor material in printed electronics21. Recently, printed passive electrodes based on graphene inks22 have been shown as promising components for printed electronics. It must be pointed out however, that to date, printed graphene-based transistors used dielectric gating13, non-direct fabrication processing23 or organic materials24 which exhibit low mobilities.


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In this paper, we instead report on the novel development and implementation of a printed graphene-based passive structure for an n-type inorganic EGT, paving the way to the fabrication of a fully printed transistor. This EGT operates at low input voltages and it exhibits excellent transistor performance. Furthermore, we report on the optimization of the EGT geometry and on its impact on the EGT performance, when changing from an in-plane to a top-gate device.

Results and Discussion

Towards fabrication of electric circuits on flexible substrates, the first step is to develop a procedure for a fully printed transistor, including all its active and passive components. Therefore, the emphasis is placed here on the development and optimization of device parameters for a fully printed EGT, using graphene ink for passive structures, rather than fabricating the printed devices on flexible substrates. Graphene ink is chosen as material for the passive structures for its superior chemical stability as compared with metal inks, such as Ag-based nano-particulate inks, which might react with strongly oxidizing


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chemicals like LiClO4 incorporated in the CSPE (Fig. S1). The chemical stabilities of the printed graphene ink and the printed silver ink against electrolyte are investigated using cyclic voltammetry (Fig. S2). To investigate the electrical behavior of the printed graphene electrodes (details about printing technique and procedure can be found in the experimental section of the paper), van-der-Pauw measurements were carried out on electrodes prepared at different temperatures and the impact of the curing temperature was also investigated. It was found (refer to Fig. S3a in the supporting information) that the resistance of the printed graphene electrodes decreases with increasing annealing temperature up to 250 °C, above which only a minor decrease in the resistance was observed. It has been reported22 that ethyl cellulose, used as a binder in the graphene ink, thermally decomposes into aromatic species, resulting in a π-π stacking with graphene that contributes to a better charge transport. These decomposition products also participate in forming a dense continuous graphene film (refer to Fig. S3b in the supporting information). However, when heated above 400°C, ethyl cellulose and its decomposition products decompose further, thereby reducing the conductivity of the film.


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The obtained conductivity values (2 x 104 S/m) are as expected, these values are below the conductivities of metallic thin films (107 S/m)25 or sputtered ITO (5 x 105 S/m)26, but, these lower values do not limit the current flow when the EGT channel is open27. In order to test the printed graphene electrodes incorporated in a fully printed in-plane EGT (a side-view in the schematic of the printed in-plane EGT is shown in the supporting information. Fig. S4) and to investigate their impact on the EGT performance, an adapted printing procedure was developed. The necessary steps to construct an all-printed EGT with graphene electrodes are illustrated in Fig. 1a. First, the precursor ink for In2O3 was ink-jet printed on a glass substrate and then annealed at 400°C. Afterwards, the graphene electrodes were partially printed on top of the semiconductor, using a micro plotting technique as shown in Fig. 1a and then annealed to 250 °C. This was followed by vacuum processing to form the backbone structure of the in-plane transistor. Finally, the polymer electrolyte was ink-jet printed across the semiconductor and gate electrode and dried at room temperature. To print the semiconducting channel and the electrolyte, a previously reported technique16 was used. Additional details on the synthesis procedure for these inks can be found in the experimental section of the paper.


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Due to the subsequent temperature treatment at 400°C, it was necessary to first print the semiconductor, prior to the to the printing of the passive electrodes, otherwise, the graphene ink would decompose if exposed at 400°C temperature. A cross sectional scanning electron micrograph (SEM) image, taken after the printing of the graphene electrodes (Fig. 1b), shows the smooth interface between the substrate and the channel as well as between the channel and the graphene electrode.

Figure 1 a) Schematic of the fabrication of an all printed EGT. (i) Semiconductor precursor ink-jet printed on the glass substrate; (ii) graphene passive electrodes deposited by microplotting; and, (iii) CSPE ink-jet printed across semiconductor and gate electrode. Fig. 1b) Cross sectional SEM micrograph, taken after the printing of graphene (as shown in the schematic), reveals a three distinct printed layer.


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The transistor characteristics of the as-prepared fully-printed in-plane EGT, are summarized in Fig. 2. The transfer curve in Figure 2a shows a clear switching behavior of the device at a threshold voltage (VTh) of 0.23 V, rendering it as a normally-off device. The drain current (IDS) starts to increase linearly with the gate voltage (VGS) from an offvalue (IOFF) of 10-9 A to an on-value (ION) of about 10-4 A, which results in an ION/IOFF ratio of ~105. The subthreshold slope is calculated to be 120 mVdec-1 (theoretically limit around 60 mVdec-1). It should be noted that in the present device, the channel is 150 µm in length (𝐿) and 60 µm in width (𝑊). The negligible gate leakage current (~10-10 A) makes the device very stable even at low input voltages. The output I-V curve in Fig. 2b shows a linear increase in the drain current at low drain voltages and it saturates at higher drain voltages, in currents in the range of 10-5 to 10-4 A, for different gate-source potentials.


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Figure 2. Electrical characterization of the as-prepared fully-printed EGT. a) Transfer characteristics. The inset shows an optical microscope image of the device; electrolyte (dark), graphene electrodes (light grey) and the semiconductor (#) connecting source and drain. b) Output IDS vs VDS curves at different VGS.

To further characterize the printed devices, the mobility of the transistors was calculated and the contact resistance between the printed graphene and In2O3 was determined.

Mobility calculation The electronic mobility (µlin) of the transistor with channel width W and length L is computed from the slope of the linear region of the transfer curve

( ) in Fig. 2b at a ∂𝐼𝐷𝑆

∂𝑉𝐺𝑆


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constant source/drain voltage (VDS) using Eq. 1, under the precondition that

𝑉𝐷𝑆 ≪ 𝑉𝐺𝑆 ―

𝑉𝑇ℎ.

𝐿

𝜇𝑙𝑖𝑛 = 𝑊𝐶𝑠𝑝𝑉𝐷𝑆

( ) ∂𝐼𝐷𝑆

∂𝑉𝐺𝑆

(1)

To compute µlin, the double layer specific capacitance at the channel-electrolyte interface (CSP) has to be previously determined. This can be done by cyclic voltammetry (CV) measurements. Therefore, the current density (JGS), at different sweeping rates ( ∂𝑉𝐺𝑆

∂𝑉𝐺𝑆

∂𝑡

∂𝑡

( )) has been evaluated and the slope of the curves measured (𝐽𝐺𝑆 = 𝐶𝑆𝑃( )). These measurements are performed on identical in-plane device structures, with shortened source and drain electrodes (Fig.3a) using different sweeping rates of the gate-source potential between -0.5 V and 1 V. As a positive gate bias (VGS) is applied, the channel forms at the threshold voltage and a further increase of VGS leads to an accumulation of electrons in the channel. As a result, the current density (calculated using the area of the In2O3 electrode covered by the electrolyte) in the CVs is increasing with VGS. This


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behavior can be observed in the CV curves by using different scan rates (Fig. 3b). The current density, JGS, is linearly proportional to the scan rate (Fig. 3c), which indicates a capacitive behavior. The slope of these measured straight lines yields CSP at different applied potentials. Fig. 3d shows CSP as a function of VGS. The capacitance increases almost linearly from 10 μFcm-2 at 0.1 V to 35 μFcm-2 at 0.5 V and it appears to saturate after 0.7 V at 42 μFcm-2. The capacitance of 40 μFcm-2 at a gate voltage of 0.6 V is used for the mobility extraction. This trend is similar to the capacitance that has been observed in an ideal metal insulator semiconductor (MIS) capacitor structure 28.


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Figure 3. Capacitance measurement performed using cyclic voltammetry. a) Schematic of the planar plate capacitor geometry used to measure the double layer capacitance. The electrolyte is printed across the majority of the gate and the entire indium oxide semiconductor while avoiding having much contact with the source and drain electrodes. b) The harp-shaped change of JGS with VGS is an indication of accumulation and depletion of charges at the semiconductor surface. c) From the slope of the straight lines the specific capacitance values can be computed. d) Shows the CSP vs. VGS plot.


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The capacitance measured using cyclic voltammetry is also verified using LCR method for a frequency of 1 Hz and the value matches with the capacitance obtained using cyclic voltammetry (Fig. S5).

Calculation of contact resistance

An important device parameter, which significantly affects the transistor performance, especially at low input voltages, is the contact resistance between graphene and semiconductor. In order to analyze the performance of the transistor, the contact resistance between graphene and the In2O3 channel, while using electrolyte gating, needs to be accounted for29. Therefore, the contact resistance is measured in the EGT using the so called transmission line model (TLM)30. In the linear region of the output drain current (e.g., Fig. 2b), the total resistance (𝑅𝑇𝑊), as a linear function of channel length (𝐿), is defined by Eq. 2, in which 𝑅𝐶𝑊 represents the contact resistance, while 𝑟𝑆ℎ is the channel sheet resistance. 𝑅𝑇𝑊 =

∂𝑉𝐷𝑆

∂𝐼𝐷𝑆 |𝑉𝐺𝑆

= 𝑟𝑆ℎ𝐿 + 𝑅𝐶𝑊

(2)


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To calculate the contact resistance, devices, with varied channel lengths, but of fixed width (𝑊), were prepared and the inverse of the slope, in the linear region of the output curve, (total resistance,

∂𝑉𝐷𝑆

∂𝐼𝐷𝑆 )

was plotted against the channel length. According to the

TLM, 𝑅𝑇𝑊 vs 𝐿 is plotted and presented in Fig. 4a. The contact resistance, plotted against

VGS in Fig. 4b, is calculated from the intercept of the linear curves with the Y-axis, amounts to 33 Ωcm for a gate-source potential of 0.6 V, which cannot be neglected in the mobility estimation in Eq. 1 (the channel resistance in comparison is about 70 Ωcm, for the channel length of 150 μm). The device mobility is therefore calculated, after correcting for the contact resistance. It is of note that this contact resistance value is significantly lower than the contact resistances typically obtained using dielectric gating13. The channel sheet resistance (Fig. 4c), which is obtained from the slope of the individual linear fits in Fig. 4a, it marginally decreases with gate voltage and it has a value around 4 kΩ between 0.6 V and 1V. Additionally, the device parameters, with varied channel dimensions, are presented in Table 1. Further device details, including the measurement reliability factor31, can be found in the supporting information section of the paper.


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Figure 4. Contact resistance measurements carried out via the transmission line method. a) The total resistance is plotted as a function of channel length. From the slope, in the linear region of curves, and the Y-intercept, respectively yield, the channel sheet resistance and the contact resistance. b) Contact resistance sharply decreases with increasing gate bias. c) Channel resistance is obtained from the slope of the 𝑅𝑇𝑊 vs. channel length curve.


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Channel Dimension,

On/Off Ratio log(ION/IOFF)

W/L

Subthreshold Slope

Threshold Voltage Mobility, µlin (V)

(cm2V-1s-1)

(mV/dec)

1

2.7

70

-0.11

2.7

0.8

4

140

-0.07

2.6

0.6

5.25

130

0.15

10.8

0.4

5.75

120

0.23

16

0.2

5.5

86

0.32

17.6

Table 1. Device performance for varied channel dimensions

Using the above results, the mobility is calculated by implementing the Equation 2 in Equation 1 and amounts to a constant mobility value of 16 cm2V-1s-1. This value is comparable to that obtained in devices with printed ITO electrodes17 and it outperforms the value that has been reported for all-printed devices with amorphous oxide semiconductors9,10,13,17,32,33.

Top gated devices


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To examine the impact that changed transistor geometry has on the performance, the architecture of the devices was changed from in-plane to top-gate configuration. As topgate electrode, room temperature processed PEDOT:PSS was utilized, being that the temperature necessary for the processing of graphene would render the electrolyte unusable. As can be seen in Fig. 5a, the ION/IOFF for a top-gate device is about 106. This is one order of magnitude higher than that of an in-plane device. Additionally, a reduced hysteresis can be also observed. A subthreshold slope (SS) of 70 mVdec-1 was measured, which is very close to the theoretical value. In addition, the top-gate devices demonstrate high output current (Fig. 5b) of 115 μA at a gate-source voltage of 1V. The reduced SS is the result of the minimized gate-channel distance34 that is determined by the thickness of the printed electrolyte (Fig. 5c). The reduction from 50 µm to 5 µm for inplane and top-gate architectures, respectively, reduces the time needed for the electrical double layer formation, resulting in a higher switching frequency. To roughly estimate the switching speed difference between the two geometries, pulsed potential measurements have been performed and the time needed for the formation of the electrical double layer (τRC) was obtained. Fig. 5d shows the comparison of the current increase during pulsing.


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It can be clearly seen that the top-gate devices display much higher sensitivity against the potential change than that of in-plane devices. The current in the top-gated device rises to 10-4 A between 0.3 and 0.4 s whereas in the in-plane device, the current rises to 10-5 A from 0.3 to 0.6 s. Overall, the current in the top-gated device rises to one order higher IDS as compared to the in-plane device within a time frame of 0.5 s. By fitting the measured curves to an exponential function, a time constant for top-gate devices of 80 ms and 220 ms for in-plane devices could be calculated. The fitting equations are provided in the supporting information.


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Figure 5. Transistor characteristics of the top-gated devices. a) Transfer characteristics of a top-gated device are displayed, showing an increased ION/IOFF ratio of 106 and a reduced hysteresis when compared to in-plane devices. b) The output IDS vs VDS curves at different VGS for the top-gated geometry. c) PEDOT:PSS is printed and used as the top-gate electrode. d) The switching speed measurements show that top-gate geometry, over time, leads to higher currents compared to that of the in-plane geometry. A gate voltage pulse, from -1 V to +1 V, is supplied at a constant VDS of 1 V and then IDS is measured for both geometries. The obtained curves are fitted into an exponential function, from which to the switching time constant is computed.

Conclusions


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In summary, fully printed high performance transistors based on oxide semiconductor were fabricated using graphene as the passive electrodes. The performance of these electrolyte-gated devices is comparable to state of the art transistors with the additional advantage of having low leakage currents and very low operation voltages. The mobility of the printed devices is computed after incorporating the contact resistance value between graphene electrodes and the oxide semiconductor. Additionally, top-gate devices, fabricated with PEDOT:PSS as gate electrode, display improved device performance, in terms of current and speed, compared to their in-plane counter parts. Thus, the graphene-based transistor constitutes an important first step towards achieving flexible electronics, using direct writing methods.

Experimental Ink Preparation: For the semiconductor ink, a precursor solution of 0.05 M of In(NO3)3.xH2O (99.99% Sigma Aldrich) diluted in a 4:1 mixture of de-ionized water and glycerol is used, as previously reported16 . The solution is then sonicated for 20 minutes and filtered through


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0.45 and 0.2 μm PVDF filters. Graphene source and drain electrodes are printed using a commercially available graphene ink (Sigma Aldrich). The ink consists of graphene flakes (0.2-3 μm), stabilized by ethyl cellulose in cyclohexanone and terpineol. The composite solid polymer electrolyte (CSPE) is prepared by a previously reported method35. 0.3 g Poly(vinylalcohol) (PVA, average MW =13-23 kDa, 98% hydrolyzed, Sigma-Aldrich) is mixed in 6 g of dimethyl sulfoxide (DMSO, anhydrous 99.9%, Sigma-Aldrich) solvent and stirred at 90 ˚C for 1 hour. 0.07 g of lithium perchlorate (LiClO4, anhydrous, 98%, Alfa Aesar) is dissolved in 0.63 g of propylene carbonate (PC, anhydrous, 99.7%, SigmaAldrich) plasticizer. Both the solutions are mixed together and stirred continuously for 1224 hours, at room temperature. The final solution is filtered through a 0.2 μm PTFE filter. The top-gate electrode is printed using a commercially available Poly(3,4ethylenedioxythiophene)-poly(styrene sulfonate) (PEDOT:PSS) ink (0.8% in H2O, Sigma Aldrich)

Device Fabrication:


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The precursor solution, the polymer electrolyte, and PEDOT:PSS are printed, using a Dimatix 2831 ink-jet printer. While printing the semiconductor, the drop spacing is set to 5 µm. A drop spacing of 25 µm is used, at a 3.5 inch water meniscus and the stage heated to 60˚C; the piezoelectric voltage is 40 V. The printed oxide precursor films are heated to 400 °C in two hours and annealed at the same temperature for a further two more hours. The graphene ink is printed using a Sonoplot® microplotter and processed at 250 °C for 30 minutes. The capillaries required for microplotting the graphene ink are precision made to have the required tip diameter (3-5 µm). For the electrolyte, the drop spacing is fixed at 55 µm and the stage heated to 40˚C; the voltage given is 40 V. The electrolyte dried within few minutes of printing. As the top-gate, several layers of electrolyte (thickness 5 µm) are printed and dried before printing PEDOT:PSS on top of it. The PEDOT:PSS was dried at room temperature. The gate-channel distance is limited to 50 µm in the in-plane devices, whereas in the top-gated geometry, the gate-channel distance is determined by the thickness of the electrolyte.

Material and Device Characterization:


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For SEM imaging, a Leo 1530 scanning electron microscope (SEM) was used. Electrical measurements (two-probe and transistor characteristics) were performed at ambient conditions, using a precision probe station (SUSS MicroTec MLC-150C) and they are carried out with a precision semiconductor analyzer (Agilent 4156C). For the transfer curves, the drain voltages are fixed at 1 V and the gate voltage is swept from -0.5 to 1 V. Each measurement point takes 3 seconds (3 second measuring time, 1 second hold time, and 1 second delay time). For the output characteristics, the gate voltage varied from 0 to 1 V with a step of 0.1 V and the drain voltage swept from 0 to 1 V. To estimate the channel/electrolyte capacitance, cyclic voltammetry measurements are performed, using a Bio-Logic SP-150 potentiostat.

Acknowledgements HH and JAH acknowledge the funding received from Helmholtz Association under the Virtual Institute VI-530 “Printed electronics based on inorganic nanomaterials: From atoms to functional devices and circuits”. SAS acknowledges the Ministry of Science, Research and Arts of the state of Baden Württemberg for funding research through the


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MERAGEM graduate school. BB, JAH and HH appreciate the support of EnABLES, a project funded by the European Union’s Horizon 2020 research and innovation program under grant agreement no. 730957.

Supporting Information. SEM micrograph of printed silver reaction in electrolyte system (Figure S1), Comparison of the stability of silver and graphene in the electrolyte system (Figure S2), Characterization of the printed graphene ink (Figure S3), Side view of the fully printed device (Figure S4), Capacitance measurement using the LCR method (Figure S5, Equation S1), Measurement of Reliability Factor (Table S1, Equation S2), Fitting Function for the Switching Speed Time Constant (Equation S3)

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Development of Fully Printed Electrolyte Gated Oxide Transistors

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