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InO Nanowires Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and their Logic Applications Qian Xu, Xingqiang Liu, Bensong Wan, Zheng Yang, Fangtao Li, Junfeng Lu, Guofeng Hu, Caofeng Pan, and Zhong Lin Wang ACS Nano, Just Accepted Manuscript • Publication Date (Web): 06 Sep 2018 Downloaded from http://pubs.acs.org on September 6, 2018

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In2O3 Nanowires Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications Qian Xu1,2+, Xingqiang Liu1,3+, Bensong Wan1, Zheng Yang1,2, Fangtao Li1, Junfeng Lu1, Guofeng Hu1, Caofeng Pan*,1,2,4and Zhong Lin Wang1,2,5

1. CAS Center for Excellence in Nanoscience, Beijing Key Laboratory of Micro-nano Energy and Sensor, Beijing Institute of Nanoenergy and Nanosystems, Chinese Academy of Sciences, Beijing 100083, P. R. China

2. School of Nanoscience and Technology, University of Chinese Academy of Sciences, Beijing 100049, P. R. China

3. School of Physics and Electronics, Hunan University, Changsha 410082, P. R. China.

4. Center on Nanoenergy Research, School of Physical Science and Technology, Guangxi University, Nanning, Guangxi, 530004, P. R. China

5. School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta GA, 30332, USA

*Corresponding E-mail: [email protected]

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ABSTRACT

Heat dissipation is a key issue for scaling metal-oxide-semiconductor field-effect transistors (MOSFETs). The Boltzmann distribution of electrons imposes a physical limit on the subthreshold swing (SS), which impedes both the reduction of the switching energy and the further increase of the device density. The negative capacitance effect is proposed to rescue MOSFETs from this phenomenon called ‘Boltzmann tyranny’. Herein, we report In2O3 nanowire (NW)-transistors with SS values in the sub-60 mV/dec region, which utilize the ferroelectric P(VDF-TrFE) as the dielectric layer. An ultralow SS down to ~10 mV/dec is observed and spans over 5 orders of magnitude in the drain current. Meanwhile, a high on/off ratio of more than 108 and a transconductance (gm) of 2.3 µS are obtained simultaneously at Vd = 0.1 V. The results can be understood by the “voltage amplification” effect induced from the negative capacitance effect. Moreover, the steep slope FET-based inverters indicate a high voltage gain of 41.6. In addition to the NOR and NAND gates, the Schmitt trigger inverters containing only one steep slope FET are demonstrated. This work demonstrates an avenue for low-power circuit design with a steep SS.

KEYWORDS: field-effect transistors, subthreshold swing, negative capacitance, In2O3, logic circuit

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Due to their chemical stability, excellent crystallinity and low-cost synthesis, metal oxide NWs can improve device performance through enhanced gate capacitance coupling.1-7 Thus, multiple electronic devices have been demonstrated based on one dimension (1D) semiconductor nanowires (NWs), such as sensors, diodes, resistors, memory units, photodetectors, solar cells and field-effect transistors (FETs).1,

8-19

Among these metal oxide NWs, In2O3, with a high

field-effect carrier mobility, wide band gap (~3.6 eV), controllable electrical properties, and good metal–semiconductor contact, is a promising active material for integrated nanoscale electronics.2, 20-22 Meanwhile, with the ongoing scaling of FETs, it is very important to compress the power dissipation for all the switching issues. It is clear that the steep subthreshold characteristics indicate a low operation voltage and switching energy.23-24 However, the Boltzmann distribution prevents conventional MOSFETs from having an SS below 60 mV/dec at room temperature. Although transistors based on other operating principles, such as band-to-band tunneling and impact ionization, are proposed, these devices have been restricted from their compatibility or high operation voltages.25 Meanwhile, it seems that the use of negative capacitance, which is compatible with the current basic physics and standard microfabrication of MOSFETs, to solve this issue is more noteworthy. By replacing the conventional dielectric material with ferroelectrics, the change in channel surface potential can be more than that in the gate voltage, when the negative capacitance from the ferroelectrics is effectively stabilized.23-25 This “voltage amplification” effect has the potential to reduce the SS down to the sub-60 mV/dec regime.25-29

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Since the negative capacitance state is intrinsically unstable, efforts have been made to experimentally explore the negative capacitance effect.23,

30-39

Although 2D materials have

attracted researchers for their numerous advantages, the environment sensitivity and the interfacial effects often involve passivation layer deposition for a stable performance. Moreover, the nondangling bonds also lead to the challenges for dielectric deposition.20, 40 Hence, it is desirable to assemble steep slope FETs based on 1D metal oxide NWs with high performance and stability. Simpler device processing is better for low-cost, energy-saving and high-efficiency technologies. However, due to the additional capacitor divider, all the reports solving the issue of “Boltzmann tyranny” complicate the device structures. Thus, there is significant room to experimentally investigate steep slope FETs, which are still in their early research phase. In this work, In2O3 NW transistors with sub-60 mV/dec SS are fabricated utilizing organic ferroelectric P(VDF-TrFE) as the gate insulator and assembled via spin-coating. A side-gate structure is utilized to enable a simple approach, in which only one electron beam lithography (EBL) processing step is needed. The reported steep slope FETs present an ~10 mV/dec SS spanning over 5 orders of magnitude in the drain current at room temperature. The high on/off ratio of more than 108 and a gm of 2.3 µS are obtained simultaneously. In further testing for improved statistics, all the devices show sub-60 mV/dec SS. The improved SS is elucidated from a “voltage amplification” resulting from the effective negative capacitance, which is also confirmed by the negative drain-introduced barrier lowing (DIBL). When applied as inverters, the steep SS transistors lead to a voltage gain as high as 41.6, with NOR and NAND gates also

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being assembled. To functionalize the steep slope FETs further, the Schmitt trigger inverters containing only one FET are demonstrated. RESULTS AND DISCUSSION Figure 1a demonstrates the device structure of the steep slope FETs with a spin-coated ferroelectric P(VDF-TrFE). The In2O3 NWs, with a uniform radius of ~25 nm, were synthesized by a chemical vapor deposition (CVD) process and transferred subsequently onto a Si/SiO2 substrate with a 100 nm thick SiO2 layer. The source, drain and side-gate electrodes in this work were defined with only one EBL step, followed by the deposition of Cr/Au (10/50 nm) and a lift-off process. Then, the ferroelectric film was assembled by spin-coating to form a uniform thin film covering the entire substrate. Finally, the substrate with ready-made FETs was baked on a hot plate at 130 oC for 2 h. In general, a top-gate, multigate or 3D-gate with ultrathin and high-k dielectric layer are used in other reports to improve the performance.32-35, 41-42 In contrast, the fabrication process in this work has low-cost and high-efficiency. The top schematic view of the device in this work is illustrated by Figures 1b and c. Figure S1a displays the XRD pattern of the baked P(VDF-TrFE) film with a character peak corresponding to the polar β-crystalline phase,43 which is necessary for negative capacitance. When in the on-state, as depicted in Figure 1b, there will be polarization pointing from the side-gate to the In2O3 NWs in the ferroelectric layer stemming from an applied fit positive voltage at the side-gate. The polarization will accumulate electrons in the In2O3 NWs. In the same way, after a fit negative gate voltage is applied, as seen in Figure 1c, the NW channel will be depleted, and the device will be in the off-state. Although the ferroelectric polarization is also useful in this work, the key 5


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operating principle is different from the conventional ferroelectric field-effect transistors (Fe-FETs) that depend only on the high-k and the remnant polarization of the ferroelectrics.1, 20, 44-48

The motivation here is to utilize the negative capacitance effect as a “voltage amplifier” to

improve the SS, as revealed and explained in detail later. The relevant SEM image shown in Figure 1d illustrates a top view of the measured FET. In the device, the channel length is designed to be 3 µm, and the width between the channel and the side-gate is ~230 nm. Although there is an ~120 nm thick P(VDF-TrFE) film with a wave-like surface covering the device,1 the NW with an approximate diameter of 50 nm was obtained. Figures 1e and f show the typical transfer and output characteristics of the device, respectively. The output characteristics suggests good ohmic contacts between the NWs and the electrodes, according to their liner behavior at a low drain bias. As depicted in Figure 1e, when the sweeping range of the gate voltage is ±10 V, the channel is depleted fully, and an on/off ratio of more than 107 at room temperature is achieved. The results suggest that the conductivity of the In2O3 channel can be controlled effectively when a suitable gate voltage is applied. The traditional back-gated counterparts have an SS value of more than 150 mV/dec (Figure S2, with 100 nm SiO2 as dielectrics), which agree with or are even smaller the typically reported values.2, 22 In contrast, the tested side-gated steep slope FET (Figure 1g) illustrates an SS less than 60 mV/dec and spanning over 4.5 orders of magnitude in Id, at room temperature and in ambient air. The smallest SS value is below 15 mV/dec, while no evidence of gate-induced leakage is observed. Although the lowest SS value of 80 mV/dec from forward sweeping is larger than that from reverse sweeping, there is a distinct superiority to the conventional 6


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counterparts, such as those given in Figure S2 and from other reports.2, 22, 49 To compare the conventional MOSFETs and the steep slope FETs without the influence from the individuality of NWs, the P(VDF-TrFE) was spin-coated on the same device measured in Figure S2, and the relevant steep slope results are shown in Figure S3 revealing an SS value below 60 mV/dec. Thus, it is suggested that the P(VDF-TrFE) dielectric layer can significantly improve the switching performance of the In2O3 NW-based FETs and drive them towards theoretical limits. Furthermore, the enhancement from the additional back-gate voltage on the SS is also revealed. As illustrated in Figure S3c, because of the additional controls from the back gate, increasing the back-gate voltage from -15 to +15 V in 5 V steps causes the SS value to become smaller. This phenomenon indicates that the threshold voltage, SS, on/off ratio and other performances of the steep slope FETs may be modulated with a piezoelectricity that avoids changing in instinct property of the channel or modifying the device parameters. A statistical analysis of the SS value from 27 individual devices without additional back-gate voltage was also performed. Figure S4a shows that the lowest SS value is 11.3 mV/dec, and a sub-60 mV/dec SS is achieved for all the measured devices. According to Figure S4b, the average value of SS is calculated to be 28.94 mV/dec, and 37% of the measured devices demonstrate an extremely small SS of 14 ±4 mV/dec. The stability of the SS of less than 60 mV/dec from different devices is revealed from the above results and confirms the ability of the ferroelectric layer to overcome the fundamental limits of the MOSFETs. Figure 2a displays the transfer characteristics of four steep slope FETs with different P(VDF-TrFE) widths of 108.5 nm, 137.8 nm, 278.2 nm and 391.7 nm, which are based on the 7


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same NW (~50 nm diameter) and the same channel length of 3 µm (Figure S5a). The relevant output characteristics of the four devices are shown in Figures S5b ~ e. As revealed in Figure 2b, all these devices achieve a sub-60 mV/dec SS spanning over 5 orders of magnitude in the Id, and the smallest SS is ~10 mV/dec. Meanwhile, the high on/off ratio of more than 108 and a gm of 2.3 µS are simultaneously obtained. When the width of the P(VDF-TrFE) decreases, SS values are constantly lower than 60 mV/dec, and the gm and the Vpinch-off illustrate a trend of general improvement (Figures 2d and e), and the ∆Vh remain at stable levels between 0.4 ~ 1.1 V. The device with a 108.5 nm wide P(VDF-TrFE) was measured with a sweeping range of ±2.5 V due to the greatly increased gate current under higher gate voltages (Figure S5f). As is well known, it is impractical for conventional MOSFETs to overcome the lower limit of the SS since the electrons follow a Boltzmann distribution.23-24 To understand the above results of an ultralow SS, it is necessary to explain the ability of a negative capacitance to overcome the “Boltzmann tyranny” through the “voltage amplification” resulting from the effective negative capacitance, which can be provided by replacing conventional dielectrics with ferroelectrics.25 The SS can be expressed by the equation SS

∂Vg

∂Vg

∂(log 10 Id )

∂Ψ

S

∂ΨS ∂(log 10 Id )

, in which Vg is the applied

gate voltage, and Ψs is the surface potential on the channel. Since the capacitance of the insulator and semiconductor are in series, as shown in the inset of Figure 1e, the as the body factor ‘m’) can be quantified by

∂Vg ∂ΨS

=1+

CS Cins

∂Vg ∂ΨS

term (often known

. It is well known that the

∂ΨS ∂(log10 Id )

term

is ~60 mV/dec at room temperature, and due to the positive capacitances Cins, the body factor ‘m’ must exceed 1. The key function of ferroelectrics is to provide a negative value of Cins in the body factor ‘m’, thus causing ‘m’ to be less than 1. Consequently, the change in Ψs can exceed 8


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the change in Vg , and this “voltage amplification” can enhance the SS to the sub-60 mV/dec regime. There is a caveat that the ferroelectric capacitor must be in series with a normal one (e.g., the Cs in this work) so that the total capacitance is positive and the negative capacitance segment can be stabilized effectively, otherwise, the ‘voltage amplifier’ will malfunction.34 Negative DIBL have been predicted and regarded as a phenomenon stemming from the negative capacitance effect in previous reports.26, 50 As seen in Figure 2e, there are clear positive shifts in the reverse sweeping for the transfer characteristics of a device measured with Vd from 0.1 to 1 V, and the |Vpinch-off| shows an obvious decrease (Figure 2f). The negative DIBL is also observed in repeated measurements (Figure S7), from which it is revealed that although the transfer characteristics shift slightly to the right or left, a negative DIBL always appears during the reverse sweeping, corresponding with an ultralow SS (Figure S7d). This result confirms the effective negative capacitance from another perspective. Then, the steep slope FET-based inverters were fabricated. The output and transfer characteristics of the FETs used to construct the inverter are illustrated in Figures 3a and b, respectively. Figures 3c ~ f illustrate the static voltage transfer characteristic (VTC) curves of the inverter. The inverter contains one FET as a switch and one resistor as the load. When the FET is in the off-state, the voltage across the load will be very small due to the weak off-current in the channel, and the voltage across the FET (Vout) will be equal to the power supply VDD. When the FET is in the on-state, Vout will be close to 0 V resulting from the high conductivity of the FET. During the measurement, the side-gate voltage (Vin) was cycled between ±10 V to switch the FET between the on- and off-state. In this process, a voltage gain as high as 41.6 is obtained with 9


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a 500 MΩ load, as seen in Figure 3e. The results of the inverters with other load resistances are also displayed in Figures 3 and S9. Despite the relatively smaller voltage gains from forward sweeping, when considering that the load is a common resistor instead of carefully selected transistors that are usually utilized in other reports with high voltage gains,51-53 the results obtained in this work demonstrate the high performance of the steep slope FETs again. The NAND and NOR gates were also assembled by utilizing the steep slope FETs. Figures 4a and b demonstrate the switching components of a NAND and a NOR gate constructed on single In2O3 NWs, respectively. Figure 4c shows the Vout of a NAND gate depending on variations in the Vin1 and Vin2. The switching part of a NAND gate contains two FETs in series (inset of Figure 4c), with either or both inputs at the low potentials (e.g., -10 V) representing a logical 0, the output voltage will equal VDD (logical 1) due to the very low off-current of the FETs. The output voltage will be approximately 0 V (logical 0) when both FETs are turned into the on-state from the input at a high potential (e.g., +10 V), which is a logical 1. Distinct from the NAND gate, the switching part of a NOR gate consists of two FETs in parallel, as illustrated in the inset of Figure 4d. When either or both inputs are at high potentials (e.g., +10 V), representing a logical 1, the output voltage will be close to 0 V (logical 0) because of the high conductivity of the channel in the on-state. The output voltage will approximate the VDD (logical 1) when both FETs are turned into the off-state from the input at a low potential (e.g., -10 V), which are logical 0. The hysteresis loops observed in transfer characteristics of the steep slope FETs can simplify the Schmitt trigger inverters; thus, the circuits can be the same as the inverters that include only 10


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one FET (inset of Figure 3c), while the counterparts based on conventional MOSFETs usually require four to six transistors to construct the complex circuits.26, 54-55 First, the fresh FET in the inverter was polarized with a triangular waveform input signal having an amplitude of ±10 V at 0.05 Hz (Figure S10a). Then, the amplitude of the input signal was decreased to ±3 V, as shown in Figure 4e, and the output voltage switched between 0 V and the VDD of 5 V with a hysteresis of ~2 V, which is associated with the hysteresis characteristics of the steep slope FET. When the frequency of the input signal was raised to 0.1 Hz, there were no distortions in the output signal (Figure 4f). An applied input of ±2 V at 0.05 Hz gave similar results (Figure 4g). The input frequency was increased up to 1 Hz until distortions began to emerge (Figures S10b and c), due to the RC delays mainly stemming from the overlapping capacitances in the circuit. By assembling the Schmitt trigger inverters, the steep slope FETs are further functionalized. A sub-60 mV/dec SS is achieved (measured Vd ≥ 0.1 V) and logic applications are demonstrated. However, there are many challenges remaining in this field. While the Schmitt trigger inverters are easily assembled due to the hysteresis in this work, this also indicates that sub-60 mV/dec SS and attractive hysteresis-free transfer characteristics cannot be achieved simultaneously. Hysteresis and sub-60 mV/dec SS often coexist in current reports.36-39 Furthermore, high-frequency performance still needs to be investigated to understand the details of the steep slope, and ferroelectric materials with short relaxation times for high-frequency operation are necessary to access practical applications. CONCLUSIONS

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In summary, the “Boltzmann tyranny” is overcome through a negative capacitance effect provided by a ferroelectric P(VDF-TrFE) insulator in side-gated In2O3 NW-based steep slope FETs. The FETs are designed to be side-gated to realize simple, low-cost and high-efficiency fabrication using only one EBL step. These steep slope devices present better performances than conventional devices, including those employing multi- or 3D-gates with ultrathin and high-k dielectrics. The steep slope FETs in this report present sub-60 mV/dec SS spanning over 5 orders of magnitude in Id. Moreover, a high on/off ratio of more than 108 and a gm of 2.3 µS are obtained simultaneously at a Vd of 0.1 V. A statistical analysis was conducted, and all the measured FETs break through the physical limit of the SS. The average SS is estimated to be 28.94 mV/dec, and 37% of the steep slope FETs demonstrate extremely small SS of 14 ±4 mV/dec or less, with the lowest SS of 11.3 mV/dec. The effective negative capacitance provided by the P(VDF-TrFE) accounts for the ultralow SS observed from the steep slope FETs. The mechanism can be understood from the “voltage amplification” function of the ferroelectric capacitor when the negative-capacitance is effectively stabilized, and the effective negative capacitance is verified from the negative DIBL. Then, the steep slope FETs were employed to fabricate inverters with voltage gains as high as 41.6. In addition to the logic circuits of NOR and NAND gates, the Schmitt trigger inverters with the simplest circuit were also assembled to further demonstrate their logic applications. METHODS Nanowire Synthesis. The single crystalline In2O3 NWs utilized in this report were synthesized by a simple CVD method in a horizontal tube furnace. Firstly, a quartz boat containing a mixture 12


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of In2O3 powder and graphite powder (10:1 weight ratio) was put in the tube furnace. Then, Si substrates with gold catalyst (1 nm thick) were placed in the downstream location of quartz tube that was ~10 cm away from the evaporation source. Subsequently, the temperature of the source and substrates were set at 1100 and 900 oC, respectively, and then heated continually for 1 h with a fixed current of argon/oxygen (100:1) gas at 200 sccm. When the reactor had cooled down, lots of NWs were formed on the Si substrates. Steep Slope FETs Fabrication and Characterization. The In2O3 NWs were transferred onto a Si/SiO2 substrate in which the thickness of SiO2 layer is 100 nm. Then, MMA and PMMA were spin-coated at 4000 rpm and were subsequently baked on the hot plate at 160 oC. The standard EBL process (FEI Helios NanoLab 600i with Raith SEM-pattern generator) was conducted to define the electrodes, followed by the deposition of Cr/Au (10/50 nm) and the lift-off process. The P(VDF-TrFE) layer was assembled by spin-costing the P(VDF-TrFE) (70:30 mol%) powder dissolved in the diethyl carbonate, and the film was thermal annealed at 130 oC for 2 h. Electrical performance of the steep slope FETs was measured by Keithley 4200S semiconductor parameter analyzer. Keithley 6514 system electrometer and Stanford DS345 synthesized function generator were employed for measurement of the logic devices based on the steep slope FETs. SEM was conducted on FEI Helios NanoLab 600i. All electrical measurements are conducted at room temperature. AUTHOR INFORMATION

Author Contributions 13


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+Q. X. and X. L. contributed equally to this work.

Corresponding Author *E-mail: [email protected]

ACKNOWLEDGMENT The authors thank the support of national key R & D project from Minister of Science and Technology, China (2016YFA0202703), National Natural Science Foundation of China (No. 61675027, 51622205, 51432005, 61505010 and 51502018), the support of national key R & D project from Minister of Science and Technology, China (2016YFA0202703), Beijing City Committee of science and technology (Z171100002017019), Beijing Natural Science Foundation (4181004, 4182080, 4184110 and 2184131) and the "Thousand Talents" program of China for pioneering researchers and innovative teams.

ASSOCIATED CONTENT

Supporting Information

The following files are available free of charge.

The XRD pattern and the PE-loop curve of the P(VDF-TrFE) thin film; electric performance of the back-gated In2O3 NWs-based FET; electric performance of the side-gated steep slope FET constructed on the same device in figure S2; the statistical analysis of SS value from 27 individual steep slope FETs; SEM image and output curves of the devices shown in Figure 2; the 14


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relevant output curves of the device shown in figure 2 (e); the negative DIBL and ultra-low SS of a steep slope FET; the temperature-dependent measurement of transfer characteristics in a vacuum; inverters based on the steep slope FETs; dynamic measurements of steep slope FETs based Schmitt trigger inverter. (PDF)

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Figures

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Figure 1. Device structure, schematic illustrations and electric performance of the side-gated steep slope FETs based on In2O3 NWs. (a) Device structure of the steep slope FETs, while (b) and (c) illustrate the on- and off-states, respectively, with opposing of electric fields in the P(VDF-TrFE) thin film. (d) False color SEM image of the measured steep slope FET; the scale bar is 4 μm. Parts (e) and (f) present the output and transfer characteristics, respectively, of the same device measured at room temperature. The inset in (e) illustrates the equivalent circuit for the capacitive voltage divider in the steep slope FETs. (g) The SS estimated from transfer characteristics versus the drain current, showing a sub-60 mV/dec SS.

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Figure 2. Electric measurements of the steep slope FETs with a sub-60 mV/dec SS at room temperature. (a) The transfer characteristics of the steep slope FETs with different P(VDF-TrFE) widths based on a single NW. Parts (b) and (c) present the SS estimated from the relevant transfer characteristics versus the drain current and P(VDF-TrFE) width, respectively. (d) The Vpinch-off and ΔVh of the In2O3 FETs (e) Transfer characteristics of another device showing a negative DIBL. (f) Relevant SS and Vpinch-off.

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Figure 3. Inverters based on the steep slope FETs. Parts (a) and (b) show the output and transfer characteristics from the FETs as a switch in the inverter. The inset of (b) illustrate the relevant SEM image; the scale bar is 2 µm. (c ~ f) Static voltage transfer characteristic (VTC) curves and relevant gains of the inverters with different resistances of (c) 100 MΩ, (d) 300 MΩ, (e) 500 MΩ , and (f) 800 MΩ. The inset of (c) is the corresponding circuit diagram.

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Figure 4. Logic applications of the steep slope FETs. Parts (a) and (b) demonstrate the switching components in the NAND and NOR gates, respectively. Parts (c) and (d) are the output voltages of the NAND and NOR gates, respectively, depending on different inputs. (e ~ g) Transient response of the Schmitt trigger inverter under the triangular waveform input signals of (e) ±3 V at 0.05 Hz, (f) ±3 V at 0.1 Hz, and (g) ±2 V at 0.05 Hz.

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