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Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor Lin Chen, Fuxi Cai, Ugo Otuonye, and Wei D. Lu Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.5b04038 • Publication Date (Web): 16 Dec 2015 Downloaded from http://pubs.acs.org on December 17, 2015

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Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor Lin Chen, Fuxi Cai, Ugo Otuonye, and Wei D. Lu* Department of Electrical Engineering and Computer Science, the University of Michigan, Ann Arbor, Michigan 48109 ABSTRACT Vertical junctionless transistors with a gate-all-around (GAA) structure based on Ge/Si core/shell nanowires epitaxially grown and integrated on a Si substrate were fabricated and analyzed. Due to efficient gate coupling in the nanowire-GAA transistor structure and the high density onedimensional hole gas formed in the Ge nanowire core, excellent P-type transistor behaviors with of 750 µA/µm were obtained at a moderate gate length of 544 nm with minimal shortchannel effects. The experimental data can be quantitatively modeled by a GAA junctionless transistor model with few fitting parameters, suggesting the nanowire transistors can be fabricated reliably without introducing additional factors that can degrade device performance. Devices with different gate lengths were readily obtained by tuning the thickness of an etching mask film. Analysis of the histogram of different devices yielded a single dominate peak in device parameter distribution, indicating excellent uniformity and high confidence of single nanowire operation. Using two vertical nanowire junctionless transistors, a PMOS-logic inverter with near rail-to-rail output voltage was demonstrated, and device matching in the logic can be conveniently obtained by controlling the number of nanowires employed in different devices

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rather than modifying device geometry. These studies show that junctionless transistors based on vertical Ge/Si core/shell nanowires can be fabricated in a controlled fashion with excellent performance, and may be used in future hybrid, high performance circuits where bottom-up grown nanowire devices with different functionalities can be directly integrated with an existing Si platform. KETWORDS Germanium/Silicon, nanowire, vertical transistor, junctionless transistor

Corresponding Author *E-mail: [email protected]


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The exponential growth of the Silicon metal oxide semiconductor field effect transistor (MOSFET) industry in the last a few decades has been largely driven by continued scaling following Moore’s law that leads to integrated circuits with lower cost, higher density and faster speed in every new generation. However, as the device dimensions reach nanoscale, it has become increasingly challenging and less cost effective to simply shrink the device size. While conventional MOSFET scaling faces technical and fundamental difficulties due to lithography limits and performance degradation due to short channel effects (SCE), approaches using alternative, channel-replacement materials (More Moore) or new device structures and new computing architectures (More than Moore) have attracted increasing interest to extend the function scaling beyond Moore’s law.1 A number of possible candidates have been actively pursued as channel-replacement materials to extend function scaling, including nanowire transistors2–4, carbon based transistors5–7 and III-V material based devices8–10. These materials, in the form of reduced dimensionality (nanowires, carbon nanotubes, graphene and other 2D materials11–13) also enable the implementation of transistor structures with improved SCE control due to the use of ultra-thin (determined by nanowire/nanotube diameter or 2D material thickness) channels and the gate-allaround (GAA) configuration. Among them, Ge based nanowire transistors14–17 are particularly promising and offer a number of advantages. First, Ge can offer both high electron (3900 cm2/V·s) and hole (1900 cm2/V·s) mobility at room temperature18. Second, already introduced into semiconductor industry as a crucial component in strained Si,1 Ge is a proven CMOS compatible material compared with other alternatives. Third, even though Ge has a relativelylarge lattice mismatch (4%) with Si, defect-free epitaxy of Ge nanostructures such as Ge nanowires on Si is possible due to coherent strain relaxation in the reduced volume.19–22


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Additionally, the ability to form Ge/Si core/shell heterostructure nanowires leads to the formation of high density hole gas without intentional dopants in the channel23,24, further boosting the performance of Ge nanowire transistors.25 The formation of high-density hole gas in the Ge nanowire core also enables alternative transistor structures such as the junctionless transistor26,27. The basic operation principle of conventional MOSFETs depends on the formation of p-n junctions, which act as barriers to selectively block current flow. To keep up with size reduction, heavier doping is needed on both sides of the junctions to narrow the depletion width, which poses severe challenges both during fabrication (e.g. precise control of the thermal budge to avoid unnecessary diffusion) and during device operation (e.g. threshold voltage variations due to increased random dopant variations, punch-through and other high-field effects).1 The junctionless transistor structure26,27 circumvents these problems by eliminating the junctions altogether with uniform doping throughout the device including the source, channel and drain regions, thus avoiding fabrication and performance issues related to heavily doped junctions. The operation principle of a junctionless transistor is in fact quite simple: current flows through the heavily doped channel at ON state and is cut off at OFF state when the channel is fully depleted by a gate voltage, with the channel length solely determined by the gate length. Key to the operation of junctionless transistors includes high enough doping to minimize series resistance in the ungated regions, and thin enough channel that allows efficient depletion at moderate gate voltages. To this end, the Ge/Si core/shell nanowire structure with a high-density hole gas, coupled with the ultra-thin nanowire channel in a GAA structure makes it an ideal candidate for junctionless transistor implementation.


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In this study, we demonstrate vertical integration of Ge/Si core/shell nanowire junctionless transistors on Si. Besides the advantages offered by junctionless transistors, integrating the nanowire transistors vertically28–31 allows for higher packing density thus potentially further performance improvements. Another benefit of vertical transistors is that the gate length is no longer determined by lithography, but rather by the thickness of the gate metal film which can be controlled at the nanometer scale during deposition at low cost. Here we show that nanowire-based vertical, gate-all-around, junctionless transistors can be reliably fabricated with epitaxially grown Ge/Si core/shell nanowires on Si with excellent on-current ( ) and SCE control. Devices with different gate lengths can be readily obtained by controlling the metal deposition process, and device matching in a PMOS circuit can be achieved by selecting devices with different number of wires, instead of having to change device design. The device performance can be fully explained by a simple junctionless transistor model, suggesting the nanowire transistors can be fabricated reliably without introducing additional factors that can degrade device performance. The Ge/Si core/shell nanowires used in this study were synthesized using a bottom-up approach.32,33 First, vertical Ge nanowires were grown epitaxially via the Vapor Liquid Solid (VLS) method34 on a heavily doped p-type Si substrate (resistivity < 0.005 Ω·cm). 20 nm Au nanoparticle colloids (Ted Pella Inc.) were drop cast on the Si substrate surface, which was pre-treated with 1M HF prior to growth to improve vertical yield.32 Nanowire nucleation was carried out at 380 °C at a total pressure of 200 Torr (0.9% GeH4 in H2) for 1 min, followed by nanowire elongation at 320 °C and 200 Torr using the same processing gas. These conditions were chosen for optimal nucleation yield and to minimize nanowire tapering. After the Ge nanowire growth, the process chamber was cooled down and purged with GeH4/H2 gas, and a


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thin Si shell (~2 nm) was then conformally coated around the Ge nanowires at 465 °C and 2 Torr in SiH4/H2. A 20 nm Al2O3 layer conformally covering the nanowire and the substrate was then deposited by Atomic Layer Deposition (ALD, Oxford OpAL) immediately after removing the sample from the growth chamber to prevent oxidation, as well as to enhance the mechanical strength of the nanowires. A scanning electron microscope (SEM) image of the as-grown Ge/Si core/shell nanowires is shown in the inset of Figure 1a. The sample was then patterned by photolithography to allow selective removal of nanowires outside the active device regions using diluted HF solution followed by Reactive Ion Etch (RIE). Afterwards, the original protective Al2O3 layer was striped and a new layer of 10 nm fresh Al2O3 was deposited via ALD as the high-k gate dielectric, followed by sputter deposition of 50 nm Tungsten (W) as the gate electrode. It was found that sputtering resulted in a conformal coverage with the sidewall thickness roughly half of that deposited on the substrate. To define the vertical gate length, PMMA (polymethyl methacrylate) was spin coated on the sample as a masking layer, and the W film was etched by SF6 via RIE. This process was optimized for isotropic etching, ensuring complete W removal in the un-covered nanowire region. As a result, the device gate length was defined as the thickness of the remaining W surrounding the nanowire, and was in turn determined by the thickness of the mask layer. To obtain devices with different gate lengths, two types of PMMA were used (in A2 and A4 solutions, respectively), which yielded an average gate length of 414 nm and 544 nm, respectively. A second W patterning step was carried out to define the gate contact pads using photolithography and RIE, followed by another layer of 20 nm Al2O3 deposition via ALD to isolate the gate electrode from the top (drain) electrode. The sample was then planarized using spin on glass (SOG, semiconductor grade 700B) which was spin coated and cured at 300 °C for 45 min in N2 environment. Afterwards, the


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nanowire was made ready for top contact formation by selectively exposing and etching the Al2O3 layer covering the nanowire tip, followed by Ni top electrode (75 nm thick) deposition via angled evaporation and liftoff. A rapid thermal processing (RTP) at 320 °C for 2 min in forming gas (5% H2 in N2) was performed to achieve Ohmic contacts to the nanowire channel. Finally, a pad opening step was performed via lithography and wet etching to allow access the buried gate and bottom (source) electrodes. A schematic of the detailed fabrication process can be found in Supporting Information. In a complete device, the heavily doped Si substrate serves as the (global) source terminal while the top electrode is used as the drain terminal. The number of vertical nanowires in each device, which determines the number of parallel channels in the device, can be controlled by tuning the original Au nanoparticle density and by controlling the active area size during the lithography step. In general, longer nanoparticle dispensing time leads to higher nanoparticle density and greater number of nanowires in the active area on average and higher device current. In this study, we focus on devices based on single nanowires. Figure 1a shows an SEM image taken after the W gate formation step, showing a single vertically standing nanowire after gate metal etch. A cross-sectional view of one finished device can be seen in Figure 2b, where the different layers are marked by different colors, highlighting the GAA structure, the junctionless design and vertical device integration. The current-voltage (I-V) characteristics of the vertical Ge/Si core/shell nanowire junctionless transistors were measured using a Keithley 4200 semiconductor parameter analyzer. Figure 1 c-d shows typical - family curves and - transfer curves of a device with gate length of 544 nm. As expected, the device shows a depletion mode (normally-ON) p-type transistor behavior with a threshold voltage of 0.95 V. The ON state current (normalized by 7 ACS Paragon Plus Environment

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nanowire circumference) was calculated to be 750 µA/µm at 2 V , higher than previously reported values for other vertical nanowire transistors based on Si, Ge and III-V materials, including both chemically-synthesized nanowires28–31,35–37 and top-down nanofabricated devices38,39. Such a high current level achieved at a moderate gate length (544 nm) is due to the high density hole gas formed in the Ge/Si core/shell structure.23 Additionally, the device exhibits excellent current saturation behavior at high (Figure 1c), indicating minimal short-channel effects due to the use of the GAA structure and the thin nanowire channel at moderate gate lengths. We note that exceeding 2 mA/µm was reported for planar Ge/Si core/shell nanowire transistors with much shorter gate lengths (190 nm24 and 100 nm25), suggesting that of the vertical device may be improved further via gate length scaling. The device exhibits a subthreshold slope (SS) of 125 mV/dec over 3 decades. Although this value is higher than the theoretical limit of 60 mV/dec at room temperature40 and the record of 75 mV/dec for vertically orientated transistors35,38, it is comparable to typical values (85-120 mV/dec) reported for vertical nanowire transistors29–31,37,39 and can be reduced via optimizing the nanowire/insulator interface

during the processing steps. The low field hole mobility can be extracted using

= ,

where the transconductance was measured from the transfer curve shown in Figure 1d and

the gate capacitance =

! /#$

was calculated using a cylindrical model. A mobility value

of 282 cm2/V·s was extracted for this device while the average mobility for all devices is 255 ± 92 cm2/V·s. Carrier mobility in vertical transistor devices tends to have a very broad range. Depending on the channel material, mobility as high as 1170 cm2/V·s was reported for InGaAs nanowire based devices31 while 102 cm2/V·s was reported for Si nanowire based devices29.


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To better understand the device performance, a numerical model was developed for the junctionless nanowire transistor. As shown in Figure 2a, the nanowire transistor was simplified as having a heavily doped Ge channel with a wrapped-around gate and Ohmic contacts at both ends. Depending on the bias conditions, the nanowire channel may operate in the accumulation, partial depletion or full depletion mode. Accumulation occurs when the applied gate voltage is lower than the flat band voltage % , resulting in a thin layer of accumulated holes on the nanowire periphery at the oxide/semiconductor interface. At partial depletion, only the carriers (holes) near the surrounding gate are depleted while a quasi-neural region remains near the center of the nanowire. The radius of the remaining quasi-neutral region &' can be solved using the following simplified Poisson’s equation in cylindrical coordinates: 1 ) )+&$ ./ [& ]=& )& )& 0

(1)

Where + is the electrostatic potential, 0 is the semiconductor dielectric constant, and ./ is the effective doping concentration of the semiconductor channel, whose value is assumed to be constant throughout the nanowire body. For a specific set of nanowire doping concentration and diameter, a minimum gate voltage required to achieve full depletion can be calculated as (detailed derivation can be found in Supporting Information): 12 = % +

-4./ -./ 6 + 6 5 40

(2)

Where R is the radius of the nanowire and 5 is the gate capacitance per unit length assuming an ideal surrounding gate.


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The mobile charge concentration 89$ can then be calculated from the carriers in the quasi-neutral region and the accumulation layer (if exists). Finally, the drain current can be calculated in a manner similar to that used in conventional MOSFETs:40

= ; 89$) :

(3)

'

Where L is the gate length and

is the effective carrier mobility. It is imperative to first validate the results from the simplified Equation (1). Figure 2b plots the total mobile charge density obtained from solving the full Poisson’s equation18 and the simplified model across a wide range of gate voltages with doping level ./ of 5×1018 /cm3. This doping level is consistent with our previous findings from back gated planar transistors made from the same Ge/Si core/shell nanowire22 and confirms the presence of high density hole gas inside the Ge core due to the Si/Ge band line-up and quantum confinement effects23. Excellent agreement was obtained, justifying the use of the simplified model. It is also important to note that while good accuracy can be achieved when the device is in the ON state (which we focus on in this study), this simple model is not applicable in the subthreshold regime due to the exclusion of minority carriers in Equation (1) and full Poisson’s equation must be used to solve for mobile carrier concentrations in the sub-threshold region. Figures 2c-d show the experimentally-obtained - family curves along with simulation results for devices with two different gate lengths (414 nm and 544 nm, respectively) using the model discussed above. To accurately model the device operation, standard, known secondary effects including series resistance, velocity saturation and mobility degradation effects at high transverse electrical fields were incorporated into the model (details of the model can be


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found in Supporting Information).40 It is worth noting that both cases were analyzed using the same set of parameters except for the gate length (experimentally determined by SEM imaging), mobility (experimentally extracted from transfer characteristics), series resistance 6 and flatband voltage % . All parameters were determined either from known physical constants or derived from actual device dimensions (e.g., gate capacitance) except for 6 and % , which were treated as fitting parameters here. The values of the parameters used in the model are listed in Supporting Information. In general, the simulation results match well with the experimental data, suggesting that the simple junctionless transistor model has captured the key elements of the device operation and demonstrating that the devices indeed work as intended with excellent electrostatic control, while extrinsic effects such as non-linear series resistance due to Schottky metal/nanowire contacts were not dominant factors affecting the device operation. One advantage of the vertical transistor configuration is that the transistor gate length is no longer determined by lithography, but rather by the thickness of the masking layer which in principle can be readily changed and controlled at the atomic level without having to re-design expensive masks. In our process, PMMA was used as the masking layer during the W etch and gate formation process. To test the capability of gate length control, several PMMA masking layer deposition conditions were carried out and a positive correlation was clearly found between the remaining W film thickness (corresponding to the gate length of the vertical transistor) and the masking film thickness, as shown in Figure 3a. SEM images of devices after the W gate etching step using different PMMA solutions (leading to different PMMA masking layer thickness) clearly show that the W gate length is controlled by the masking layer thickness, with thicker PMMA masking layer (produced by resists with higher PMMA concentration, e.g. PMMA A6 vs. PMMA A2) leading to longer gate length. The average gate length produced via 11 ACS Paragon Plus Environment

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this method is 414 ± 69 nm (A2), 544 ± 36 nm (A4) and 772 ± 24 nm (A6), as determined from SEM measurements. Additional parameters such as the spinning speed and time during PMMA deposition can also be used to control the mask layer thickness and achieve desired gate length tuning without relying on aggressive lithography steps. To further fine tune the masking layer thickness (and consequently the device gate length), an additional etch back step such as oxygen plasma etch can be performed after the film deposition to obtain the desired masking layer thickness. 100 nm gate length has been demonstrated using this approach.30 Alternatively, the gate length can be controlled directly during gate metal deposition using an anisotropic deposition method (e.g., evaporation) and gate length down to 14 nm has been demonstrated.39 The statistical distribution of device performance for devices with different gate lengths are shown in Figures 3c-d. Several interesting observations can be made. First, both cases exhibit a dominant peak current (33 ± 6 µA for case A with 414 nm gate length, and 58 ± 12 µA for case B with 544 nm gate length) in the histogram, with a large number of devices aggregated around the peak. Assuming each nanowire was grown independently and had the same probability to land in one of the active device regions, the chances for contacting n nanowires in one device can be denoted as = where Y is the chance of obtaining a single nanowire in the device. Since the nanowire density was deliberately kept low during Au nanoparticle dispensing, the average number of nanowires in an active area was below 1, i.e. = < 1.Thus the probability of contacting multiple nanowires in one device will be lowered further due to the power law dependence on nanowire number. As a result, the dominant peak value in the distribution plot can be regarded as the typical single nanowire current. In both cases, fitting the distribution histogram with a Gaussian distribution resulted in a relatively small standard deviation (~ 20 % of the average ), indicating good uniformity in nanowire properties and reliability of the fabrication process. The


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small deviations from the peak (average) value can be explained by small variations in series resistance, threshold voltage (affected by effective doping level), nanowire diameters and gate lengths. Besides the dominate peak, a few isolated occurrences can also be found at much higher current levels, probably originating from devices containing multiple-nanowires. Comparing Figure 3c to 3d, it can be seen that the peak current level is considerably lower for the : = 414 @A device. This is somewhat counterintuitive as in MOSFET devices scaling towards shorter gate lengths generally yields higher since the on-state resistance is reduced. However, in our design, the total channel length (distance from the bottom source contact to the top drain contact) is unchanged and not scaled with the gate length. As shown in Figure 3b, reduction of the gate length leads to an increase in lengths of the ungated region, and in turn leads to an increase in series resistance. The effect of the series resistance is more pronounced in the ON state, where most of the device resistance originates from the ungated regions. As a result, the shorter gate-length device will actually have a higher ON state resistance than the longer gate-length device due to the longer ungated region and consequently lower oncurrent. This result is a consequence of the junctionless design where the concept of self-aligned gate structures is not applicable, although scaling of the ungated regions along with gate length scaling in future device optimizations should result in the expected increase in ON-current. The effect of the ungated region was also quantitatively verified in the model (Figure 2d), where a larger series resistance (15 kΩ vs. 7 kΩ) was indeed found to exist in devices with 414 nm gate length. The difference in the series resistance values in the two cases can also be quantitatively explained by the different lengths of the ungated regions. From the resistivity of the Ge nanowire estimated from the doping concentration used in the model (3.8 mΩ·cm at 5×1018 /cm3)41, a difference in series resistance of ~10 kΩ was expected from the different lengths of the ungated 13 ACS Paragon Plus Environment

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region in the two cases. This estimated value agrees well with the parameters used in our model and supports the hypothesis that the current discrepancy can be attributed to the differences of the gate length in the devices. The use of nanowires in the vertical transistor structure also allows additional freedom in the circuit design. For example, in an all-PMOS logic, an inverter consists a driver transistor B functioning as an active switch and a load transistor B acting as a resistor. The output high VH is determined by the voltage dividing effect between the on-state resistances of B and B such that C = #

#D

DE

#D

. As a result, to achieve rail-to-rail operation, it requires 6F ≫ 6F . Usually

this condition is satisfied by designing transistors with very different geometries (i.e. T1 having a much larger

H

than T2) which increases design complexity and limits the minimal size of such

logic gates. In our devices, however, the ON state current is not determined by the width of gate electrodes, but rather by the number of nanowires inside the active region. As a result, optimized circuit performance can be achieved by optimizing the number of nanowires used in different devices, while maintaining uniform transistor geometry design. This concept was tested in a PMOS inverter based on the vertical nanowire junctionless transistors with 414 nm gate lengths. The inverter schematic and bias conditions are shown in Figure 4a. The input voltage I was fed to the gate of B while the output voltage J! was read out from the drain of B (source of B ). Two different driver transistors were chosen and their output characteristics were plotted in Figure 4b. It can be seen that while both driver transistors exhibit similar OFF state current, their K differ by almost 3 times. One of them (Device A, blue lines) exhibits of 33 µA, consistent with the typical value for device with a single nanowire at this gate length, and the other (Device B, red lines) exhibits of 105 µA and is 14 ACS Paragon Plus Environment

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likely formed by 3 nanowires. The voltage transfer characteristics (VTC) of two inverters composed of these driver transistors and the same load transistor are shown in Figures 4 c-d. During measurements was set to 2 V while I was swept from 0 to 3.5 V. The higher value of I required in the measurement is due to the positive threshold voltage of the driver transistor although it is possible to offset the input waveform to obtain a 2 V window (bounded by the dashed lines in Figures 4 c-d) such that the input and output signals have the same peak-to-peak amplitude. From the VTC measurement, it is evident that both inverters function correctly although the inverter with a more conducting driver transistor (Device B, Figure 4d) was able to achieve better rail-to-rail operation (0-1.94 V) than the one with a less conducting driver transistor (0-1.83 V, Device A, Figure 4c). Additionally, the inverter in Figure 4d based on Device B also exhibits a much larger gain (11.7 vs. 4.4), supporting the idea that better matching can be achieved by controlling nanowire numbers in the vertical nanowire transistor circuits. In summary, we demonstrated the fabrication and characterization of single nanowirebased, vertical, GAA junctionless transistors epitaxially integrated on Si substrates. Excellent output characteristics with very good SCE suppression were obtained. Different gate lengths were achieved using a simple method of controlling the thickness of the etch mask film. A numerical junctionless transistor model was developed to analyze the experimental data and good agreements were obtained using known physical parameters. Statistical analysis of the devices indicates good uniformity and single-nanowire operation. An all vertical nanowire inverter was demonstrated using two nanowire junctionless transistors on the same chip and optimized by selecting high conductance driver transistors with multiple nanowire channels, with inverter gain > 10 and near rail-to-rail operation. Such vertical Ge/Si core/shell nanowire


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junctionless transistors may be an integral part in future low cost, high density, high performance electronics based on hybrid-integrated circuits.


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ASSOCIATED CONTENT Supporting Information. Schematic of the fabrication processes, additional - transfer characteristics of vertical nanowire transistors, detailed description of the model for nanowire junctionless transistors and parameters used in the model. This material is available free of charge via the Internet at http://pubs.acs.org. ACKNOWLEDGEMENT The authors acknowledge partial support of this work by the National Science Foundation (ECCS-1202126) and the Electronics and Telecommunications Research Institute.


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Figures

TOC figure


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Figure 1. (a) SEM image showing the active area of a vertical nanowire junctionless transistor after formation of the W gate electrode. Only a single free-standing nanowire is in the device. Scale bar: 3 µm. Inset: 45 degree tilted SEM image of as-grown vertical Ge nanowires on Si substrate. Scale bar: 500 nm. (b) Cross section SEM image of a finished vertical nanowire junctionless transistor. The different layers are highlighted with false colors for clarity. Inset: schematic of the device structure. Scale bar: 500 nm. (c) Typical Id-Vds output characteristics of a vertical nanowire junctionless transistor with 544 nm gate length, Vgs = -2 V to 1 V in 0.5 V steps. (d) Id-Vgs transfer characteristics of the same vertical nanowire junctionless transistor.


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Figure 2. (a) Schematic of the simplified device structure used in numerical simulation. Three different operation regimes: accumulation, partial depletion and full depletion, are illustrated. (b) Total mobile charge density per unit length calculated from solving the full Poisson’s equation (cycles) and the simplified Poisson’s equation under full depletion approximation (solid line) vs. gate voltage. (c) Experimental Ids–Vds output data of device with 414 nm gate length (cycles) vs. simulation results (solid lines). (d) Experimental Ids–Vds output data of device with 544 nm gate length (cycles) vs. simulation results (solid lines). Vgs = -2 V to 1 V in 0.5 V steps in (c)-(d).


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Figure 3. (a) SEM images showing the height of the remaining W gate regions on nanowire using different masking layers (PMMA A2,A4, and A6 for cases from left to right, respectively). Scale bar: 1 µm. (b) Schematic of devices with the same total height but different gate lengths. (c) Histogram of current difference between ON and OFF states for devices with 414 nm gate length. The solid line is a Gaussian fit with mean of 33 µA and standard deviation of 6 µA. (d) Histogram of current difference between ON and OFF state for devices with 544 nm gate length. The solid line is a Gaussian fit with mean of 58 µA and standard deviation of 12 µA.


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Figure 4. (a) Schematic of the PMOS inverter consisting of two vertical nanowire junctionless transistors sharing a common bottom contact. Inset: circuit diagram of the inverter. (b) Comparison of the output characteristics between Device A (blue lines, most likely based on a single nanowire) and Device B (red lines, most likely based on 3 nanowires) in ON (Vgs = -2 V) and OFF (Vgs = 2 V) states. (c) Voltage transfer characteristics of an inverter using Device A as the driver. Inset: inverter gain vs. input voltage. (d) Voltage transfer characteristics of an inverter using Device B as the driver. Inset: inverter gain vs. input voltage. The dashed lines in (d)-(d) highlight the 2 V operation window of the inverters.


Shell Nanowire Junctionless ... - ACS Publications

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