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Dec 6, 2016 - Seung-Hwan Kim: 0000-0002-5899-2853. Byung Jin Cho: 0000-0003-3000-5403. Changhwan Shin: 0000-0001-6057-3773. Hyun-Yong Yu: ...
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Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO2/ GeO2 Interlayer Stack Gwang-Sik Kim,† Sun-Woo Kim,‡ Seung-Hwan Kim,† June Park,‡ Yujin Seo,§ Byung Jin Cho,§ Changhwan Shin,∥ Joon Hyung Shim,⊥ and Hyun-Yong Yu*,†,‡ †

School of Electrical Engineering, ‡Department of Semiconductor Systems Engineering, and ⊥School of Mechanical Engineering, Korea University, Seoul 02841, Korea § School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 34141, Korea ∥ School of Electrical and Computer Engineering, University of Seoul, Seoul 02504, Korea S Supporting Information *

ABSTRACT: A perfect ohmic contact formation technique for low-resistance source/drain (S/D) contact of germanium (Ge) n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed. A metal−interlayer−semiconductor (M− I−S) structure with an ultrathin TiO2/GeO2 interlayer stack is introduced into the contact scheme to alleviate Fermi-level pinning (FLP), and reduce the electron Schottky barrier height (SBH). The TiO2 interlayer can alleviate FLP by preventing formation of metal-induced gap states (MIGS) with its very low tunneling resistance and series resistance and can provide very small electron energy barrier at the metal/TiO2 interface. The GeO2 layer can induce further alleviation of FLP by reducing interface state density (Dit) on Ge which is one of main causes of FLP. Moreover, the proposed TiO2/GeO2 stack can minimize interface dipole formation which induces the SBH increase. The M−I−S structure incorporating the TiO2/GeO2 interlayer stack achieves a perfect ohmic characteristic, which has proved unattainable with a single interlayer. FLP can be perfectly alleviated, and the SBH of the metal/n-Ge can be tremendously reduced. The proposed structure (Ti/TiO2/GeO2/n-Ge) exhibits 0.193 eV of effective electron SBH which achieves 0.36 eV of SBH reduction from that of the Ti/n-Ge structure. The proposed M−I−S structure can be suggested as a promising S/D contact technique for nanoscale Ge n-channel transistors to overcome the large electron SBH problem caused by severe FLP. KEYWORDS: germanium, Fermi-level unpinning, Schottky barrier height, contact resistance, plasma oxidation, germanium dioxide, titanium dioxide

1. INTRODUCTION

metal is directly in contact with Ge, the Fermi-level on the metal side is strongly pinned near the edge of the valence band of Ge which results in a large electron Schottky barrier height (SBH) of approximately 0.55 eV regardless of metal workfunctions.1,2 To alleviate FLP at the metal/n-type Ge (n-Ge) contact and reduce contact resistance, there has been much research into a metal−interlayer−semiconductor (M−I−S) structure created

As devices in silicon (Si)-based complementary metal-oxidesemiconductor (CMOS) technology have been scaled down, Si has begun to reach its physical limits. Accordingly, the need for a new channel material has become apparent, and germanium (Ge) has emerged as a sound substitute candidate due to its higher carrier mobility and good process compatibility with the current CMOS process. However, there are several barriers to the development of Ge n-channel metal-oxide-semiconductor field effect transistors (MOSFETs), particularly the high source/drain (S/D) contact resistance induced by strong Fermi-level pinning (FLP) at metal/Ge contacts. When the © 2016 American Chemical Society

Received: August 30, 2016 Accepted: December 6, 2016 Published: December 6, 2016 35419

DOI: 10.1021/acsami.6b10947 ACS Appl. Mater. Interfaces 2016, 8, 35419−35425

Research Article

ACS Applied Materials & Interfaces

deionized water. The TiO2 interlayer was deposited by atomic layer deposition (ALD) under a process temperature of 250 °C, at which the deposited TiO2 layer exhibited an anatase phase. The plasma oxidation process was carried out using an inductively coupled plasma reactive ion etcher (ICP-RIE) either prior to TiO2 deposition (plasma preoxidation) or after TiO2 deposition (plasma postoxidation). The preoxidation process had the following parameters: a source power of 500 W, zero bias power, a gas flow of O2/Ar 40/5 SCCM, a chamber pressure of 10 mTorr, and varied process time durations. It is noted that the Ge surface was treated by Ar plasma to fully remove native oxides remaining at the surface27 with a source power of 100 W, a bias power of 50 W, a gas flow of Ar 40 SCCM, a chamber pressure of 10 mTorr, and a process time duration of 10 s. A postoxidation process was performed after the TiO2 deposition at a bias power of 50 W while other conditions remained constant so that O2 plasma species could penetrate the TiO2 layer, reach the TiO2/Ge interface, and form GeO2. After the interlayer stack of TiO2/GeO2 was formed by either plasma oxidation process, a top metal contact was formed using photolithography and related subsequent processes including metal deposition (Au/Ti) by an e-beam evaporator and a lift-off process. The back-side metal contact (Ti) was also created to minimize back-side contact resistance of the substrate. The current density−voltage (J−V) characteristics of the Ti/n-Ge structures incorporating various interlayer conditions were measured to verify the effects on reverse current density (JR) improvement and electron Schottky barrier height lowering. X-ray photoelectron spectroscopy (XPS) was used to investigate the film quality of the oxide layer formed by the plasma oxidation process under varying conditions, such as the composition ratio and relative amount of GeO2. Lastly, the effective electron SBH and the specific contact resistivity of the proposed structure were extracted (more details are in the Supporting Information).

by inserting a thin interlayer, usually of insulating materials, between the metal and the Ge. Several insulators, such as SiN,3 Al2O3,4 and GeOx,5 have been tried as the interlayer. They have been experimentally shown to induce Fermi-level unpinning and reduce contact resistance by reducing the metal-induced gap states (MIGS), known as the main cause of FLP, which are formed within the band gap of Ge by electron wave functions from the metal. However, the insulators’ ability to reduce contact resistance is limited by not only their large tunneling resistance due to the large conduction band offset (CBO) to Ge but also their series resistance due to their low electrical conductivity. For this reason, materials with a CBO to Ge of nearly zero, and good electrical conductivity have emerged as good interlayer candidates. In this approach, the M−I−S structures with TiO2,6−12 ZnO,13−15 and indium tin oxide (ITO)14,15 interlayers have been researched recently. However, most previous research on M−I−S structures for Ge has not considered interface states (Dit) reduction at the interlayer/Ge interface even though it would strongly affect FLP. In order to fully alleviate FLP and reduce the effective SBH in the metal/nGe contact, reduction of both MIGS and Dit within the band gap of Ge should be considered together. Several researchers have found that Dit present at the metal/ Ge interface are a significant cause of FLP, in addition to MIGS. Fermi-level unpinning techniques for n-Ge using Ge surface passivation have been developed and include sulfur passivation by aqueous (NH4)2S solution16 and plasma passivation using CF417 and SF618 plasmas. They have experimentally shown that FLP can be alleviated and electron SBH lowered at the metal/ n-Ge contact by Ge surface passivation. However, those passivation techniques usually provide unstable passivation layer which is easily altered by other post processes. The surface passivation technique for Dit reduction on Ge substrates is mainly developed for the gate region because obtaining highquality Ge MOS interfaces is critical for high-performance Ge MOSFETs.19 The GeO2 layer, which plays very similar role with the SiO2 passivation layer on Si substrates, has been widely used as the passivation layer for Ge in the gate region of Ge MOSFETs because GeO2/Ge gives low Dit on the Ge surface.19−26 After removal of the native GeOx, the GeO2 passivation layer is regrown or even deposited through various processes: thermal oxidation,19,22,23 plasma oxidation,20,21 ozone oxidation,26 and sputtering.24,25 Among those processes, the plasma oxidation process is considered to give better interface quality than other processes. Furthermore, the GeO2 passivation layer is more stable than the passivation layers which are formed by sulfur or fluorine passivation techniques. Therefore, the GeO2 layer formed by the plasma oxidation process is the very suitable interface controlling layer in the M− I−S structure for Ge. This work develops an effective SBH lowering and contact resistance reduction technique for the metal/n-Ge contact that introduces an ultrathin TiO2/GeO2 interlayer stack into the M−I−S structure where the GeO2 layer is formed by a plasma oxidation process. It investigates the effects of the TiO2/GeO2 interlayer stack between the metal and Ge on electrical properties of the M−I−S structure. Based on experimental results, it demonstrates the role of the GeO2 layer in the M−I− S structure in further lowering SBH and its mechanism.

3. RESULTS AND DISCUSSION When an interlayer is inserted between the metal and the Ge, it can reduce MIGS formation within the energy band gap of Ge by preventing the penetration of the electron wave function from the metal side. Thereby, the FLP can be considerably alleviated such that the effective electron SBH is reduced by some degrees as shown in Figure 1. Thus, the M−I−S structure can reduce the contact resistance of the metal/n-Ge contact.

Figure 1. Energy band diagrams of (a) Ti/n-Ge contact and (b) Ti/ TiO2/n-Ge contact.

Among many interlayer material candidates, TiO2 has been widely adopted for M−I−S structures in n-Ge due to its large electron affinity and low CBO to Ge. An M−I−S structure with a TiO2 layer can reduce the effective electron SBH and the contact resistance by preventing MIGS formation with having low tunneling resistance. Furthermore, TiO2 is very favorable for reducing the series resistance of the interlayer because, due to its smaller energy band gap, it has a lower film resistivity than other oxide materials. Therefore, the contact resistance of the M−I−S structure can be further reduced by adopting a TiO2 interlayer. In addition to the low tunneling and series resistances of TiO2 interlayer, it creates very low energy barrier to electrons in

2. EXPERIMENTAL DETAILS A moderately doped n-type (100) Ge substrate (1 × 1017 cm−3) was cleaned by cyclic wet cleaning using diluted 1:25 HF solution and 35420

DOI: 10.1021/acsami.6b10947 ACS Appl. Mater. Interfaces 2016, 8, 35419−35425

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structures. Although the 2 nm-thick TiO2 layer shows the best performance for the single TiO2 interlayer structure, when introducing an additional GeO2 layer between TiO2 and Ge, a 1 nm-thick TiO2 layer is used to minimize the physical thickness of the interlayer stack (more details are in the Supporting Information). Note that when creating this structure, the preoxidation process, performed prior to TiO2 deposition, is used. As shown in Figure 3a, at a reverse bias voltage of −1 V, compared to the Ti/TiO2/n-Ge structure the Ti/TiO2/GeO2/ n-Ge structure exhibits an increase in JR of over an order of magnitude. Furthermore, as shown in Figure 3b, introducing the GeO2 layer into the M−I−S structure achieves a perfect ohmic property and a JR larger than that achieved by the optimal M−I−S structure of the single TiO2 case, the one with the 2 nm-thick TiO2 interlayer. The GeO2 layer formed by the plasma preoxidation process is considered to cause the M−I−S structure to have an ohmic characteristic by alleviating FLP and reducing effective SBH even further. The GeO2 layer in the M−I−S structure reduces the effective SBH in two ways, as follows. A. Interface Controlling Effect. The first and the main effect of the GeO2 layer is the interface controlling effect at the TiO2/n-Ge interface. The TiO2 layer can efficiently alleviate FLP by reducing MIGS with its very small tunneling and series resistance; however, with a single TiO2 interlayer, an ohmic property is hard to achieve because the TiO2/n-Ge interface has a poor interface quality, which means a large Dit so it still induces FLP in the M−I−S structure. Therefore, to fully alleviate FLP in the M−I−S structure requires an interface controlling technique to reduce Dit at the interface.12 Figure 4 shows Ge 3d XPS spectra of n-Ge with different interlayer stacks. The core levels of the four oxidation states of Ge are shifted by 0.8 eV (Ge1+), 1.6 eV (Ge2+), 2.6 eV (Ge3+), and 3.2 eV (Ge4+), respectively, and the full width at half maxima (fwhm) of every oxide spectrum is fixed at 1.4 eV.31 It is well-known that GeO2/Ge provides better interface quality and electrical properties than GeOx/Ge does, so it is important to ensure the oxide layer has more GeO2 content. As shown in Figure 4a, the bare n-Ge substrate has a thin GeOx layer of which the GeO2 content is relatively small, ∼57%, indicating native oxide formation at the Ge surface. As shown in Figure 4b, when the TiO2 layer is deposited on the n-Ge substrate by ALD after a wet cleaning process, significant GeOx (or Ge−O bonds) forms, leading to a GeO2 content of ∼62%. Thus, GeOx formation during TiO2 deposition in unavoidable and the GeO2 ratio is similar to that of native oxide. This unwanted and uncontrollable GeOx induces high Dit at the TiO2/n-Ge interface and complicates the full alleviation of FLP in the M−I−S structure. This is one reason why the M−I−S structure with a single TiO2 layer shows only a quasi-ohmic property. In contrast and as shown in Figure 4c and d, the GeOx layer formed by plasma oxidation has a film quality closer to GeO2. Of all the plasma oxidation treatment times, the 30 s one provides the GeOx layer with the largest GeO2 content, 80.3%. These results correspond with the JR results of the Ti/TiO2/ GeO2/n-Ge structure created with different plasma oxidation time durations as shown in Figure 5a. For the proposed structure, the largest JR can be obtained with the GeO2 layer formed by the 30 s plasma oxidation because this duration has the best interface controlling effect on the TiO2/n-Ge interface. Longer process times than 30 s give less GeO2-like thicker layers, which induce slightly lower JR (more details are in the Supporting Information). The thickness dependency of JR for

the metal side when in contact with the metal due to FLP at the metal/TiO2 interface. In the M−I−S structure, the effective SBH is determined by many factors including the FLP at the interlayer as well as at the Ge. Assuming the FLP at Ge is alleviated by the interlayer, the Fermi-level of the metal would move toward the charge neutrality level (ECNL) of the interlayer due to the FLP at the metal/interlayer.9,28 Fortunately, with nGe, the FLP at the Ti/TiO2 interface reduces electron SBH because the ECNL of TiO2 is close to its conduction band edge.29,30 These reasons make TiO2 a very suitable interlayer material in M−I−S structures in n-Ge. Figure 2a shows the J−V characteristics of Ti/n-Ge and Ti/ TiO2/n-Ge with a 2 nm-thick TiO2 interlayer. When the TiO2

Figure 2. (a) J−V characteristics of Ti/n-Ge and Ti/TiO2(2 nm)/nGe contacts and (b) reverse current density at a bias voltage of −0.7 V of Ti/TiO2/n-Ge contact for different TiO2 thicknesses. (inset) Crosssectional schematic diagram of Ti/TiO2/n-Ge structure.

layer is inserted between Ti and n-Ge, JR increases by 4 orders of magnitude for a 2 nm TiO2 interlayer because the TiO2 layer can alleviate FLP and reduce effective electron SBH of the Ti/ n-Ge contact by preventing MIGS formation.6−9 The largest JR is with 2 nm TiO2 as shown in Figure 2b and caused by the trade-off between the reduction in SBH and the increase in series resistance.6 As the interlayer thickness increases, more MIGS can be reduced; however, the thicker interlayer has a larger series resistance, which degrades current flow at the contact. In this work, 2 nm is considered the optimum thickness for obtaining the largest JR, by balancing effects on SBH and series resistance. However, only quasi-ohmic characteristics can be obtained by the M−I−S structure with a single TiO2 interlayer as shown in Figure 2a because the Dit at the Ge surface cannot be properly reduced or even increased by the TiO2 layer, and thus the FLP is not fully alleviated. For this reason, a GeO2 layer formed by plasma oxidation is introduced as an interface controlling layer to passivate the Ge surface. Figure 3a shows the J−V characteristics of Ti/n-Ge, Ti/ TiO2(1 nm)/n-Ge, and Ti/TiO2(1 nm)/GeO2(1.5 nm)/n-Ge

Figure 3. J−V characteristics of (a) Ti/n-Ge, Ti/TiO2(1 nm)/n-Ge, and Ti/TiO2(1 nm)/GeO2(1.5 nm)/n-Ge structures and (b) Ti/n-Ge, Ti/TiO2(2 nm)/n-Ge, and Ti/TiO2(1 nm)/GeO2(1.5 nm)/n-Ge structures. (inset) Cross-sectional schematic diagram of the Ti/TiO2/ GeO2/n-Ge structure. 35421

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Figure 4. Ge 3d XPS spectra of (a) bare n-Ge, (b) TiO2/n-Ge, (c) TiO2/GeO2/n-Ge with 30 s of plasma oxidation, and (d) TiO2/GeO2/n-Ge with 70 s of plasma oxidation. The thickness of the TiO2 layer is fixed at 1 nm.

process. In contrast to the preoxidation process generally used in this work, the postoxidation process undertakes plasma oxidation with a plasma bias power after TiO2 deposition. As Figure 6a shows, JR decreases significantly when the oxide layer

Figure 6. (a) J−V characteristics of Ti/n-Ge, Ti/TiO2(1 nm)/n-Ge, and Ti/TiO2 (1 nm)/post-GeOx(30 s)/n-Ge and (b) Ge 3d XPS spectra of TiO2/post-GeOx(30 s)/n-Ge. (a inset) Cross-sectional schematic diagram of the Ti/TiO2/post-GeOx/n-Ge structure. Figure 5. JR at a bias voltage of −0.7 V of (a) Ti/TiO2(1 nm)/GeO2/ n-Ge structures created by different plasma oxidation time durations and (b) Ti/TiO2/GeO2/n-Ge structures for different total interlayer thicknesses and (c) the oxide thicknesses formed by different plasma oxidation time durations. (c inset) Cross-sectional TEM image of Ti/ GeO2/n-Ge structure formed by 50 s of plasma oxidation time durations.

is formed between the TiO2 and n-Ge substrate by the postoxidation process. Why the oxide layer formed by the postoxidation process (post-GeOx) induces JR degradation is explained by the XPS result shown in Figure 6b. The postGeOx layer has a low GeO2 content of approximately 45.3%, which is lower even than the GeO2 content of the native oxide and contrasts even more strongly with the high GeO2 content formed by preoxidation. It is noted in this case that the JR degradation is due to the poor interface quality, rather than alteration of the TiO2 layer during the postoxidation process or the formation of a thicker oxide layer; the TiO2 layer is not etched or altered by the postoxidation process (more details are in the Supporting Information) and the post-GeOx layer is not significantly thicker according to current level since in the J−V characteristics of the structure the forward current (JF) shows no serious degradation. The XPS results and corresponding J−V results for the preoxidation case show that the GeO2-like oxide layer the process creates can increase the JR of the contact through its interface controlling effect on the TiO2/n-Ge interface. This leads to the decrease of Dit, alleviation of FLP, and reduction of effective electron SBH. Furthermore, the results obtained with

TiO2 and TiO2/GeO2 stack can be compared on the same plot in Figure 5b. From the plot, it is found that the TiO2/GeO2 stack provides better JR than the single TiO2 at every fabricated interlayer thickness point. This is because the TiO2/GeO2 stack gives a better interface quality resulting in more alleviation of FLP although their MIGS reducing effects are not quite different. The actual thicknesses of the GeO2 layers formed by different plasma oxidation time durations were measured by transmission electron microscopy (TEM) and the results are shown in Figure 5c. It can be seen that GeO2 thickness has a logarithmic relationship with plasma oxidation time duration and that the 30 s plasma oxidation produces a GeOx layer on the n-Ge substrate approximately 1.5 nm-thick. The interface controlling effect of the GeO2 layer formed by plasma oxidation can be also verified by the postoxidation 35422

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8e, the GeO2 layer minimizes both interface dipole formation and the related increase in the effective SBH. The effective electron SBH and the contact resistance can be reduced by adopting the M−I−S structure with a TiO2/GeO2 interlayer stack, of which the GeO2 layer is formed by the plasma oxidation process. Figure 9a shows the effective electron

the structure made using the postoxidation process strongly support the importance of proper interface control to reduce effective SBH. B. Minimization of Interface Dipole. The second effect is the minimization of interface dipole formation at the TiO2/ GeO2 interface, which causes the M−I−S structure to have increased effective SBH. When two oxide materials are in contact with each other, oxygen atoms diffuse in a certain direction according to the oxygen areal density theory.32−34 M−I−S structures with a single TiO2 layer have an interface dipole at the interface between the TiO2 and the very thin, lessGeO2 like, low-quality GeOx layer which is inevitably formed during TiO2 ALD. The TiO2 has a larger oxygen areal density (σ) than the four kinds of germanium oxides shown in Figure 7.32 Therefore, as shown in Figure 8a, oxygen atoms move from

Figure 9. (a) Effective electron SBH and ideality factor for Ti/n-Ge and Ti/TiO2(1 nm)/GeO2(1.5 nm)/n-Ge structures and (b) corrected total resistance (RT) for C-TLM spacing in the C-TLM measurement of Ti/TiO2(1 nm)/GeO2(1.5 nm)/n-Ge structure. (a inset) Cross-sectional schematics of each structure. (b inset) Top view of the structure showing the C-TLM measurement.

SBH reduction using the M−I−S structure with the TiO2/ GeO2 interlayer stack. It is noted that the SBH of the Ti/TiO2/ GeO2/n-Ge structure was extracted from the p-type Ge (p-Ge) substrate because it is difficult to extract the SBH when the J−V characteristic develops an ohmic property rather than Schottky one (more details in Supporting Information). The effective electron SBH of the Ti/n-Ge structure is 0.548 eV corresponding well with its conventional value1 and it decreases to 0.193 eV when the proposed interlayer stack is inserted. Furthermore, the proposed structure has a specific contact resistivity (ρc) of 3.5 × 10−5 Ω·cm2 as obtained through the circular transmission line model (C-TLM) measurement, as shown in Figure 9b. The measurement was made on an n+-Ge substrate with a heavy body doping level and a moderate surface doping level (1 × 1017 cm−3) matching the carrier concentration of the n-Ge substrate used in J−V measurement (more details are in the Supporting Information). This ρc value is smaller than that of Ti/n+-Ge contact (5.1 × 10−5 Ω·cm2) of which the surface carrier concentration is over 1 × 1019 cm−3.

Figure 7. σ values of four kinds of germanium oxides normalized to that of the TiO2.

TiO2 to GeOx inducing positive and negative potentials at the TiO2 and GeOx sides, respectively. In the M−I−S structure with a single TiO2 layer, the interface dipole increases effective electron SBH through transforming its energy band diagram from Figure 8c to d. However, the insertion of the GeO2-like oxide layer formed by the plasma oxidation process between the TiO2 and Ge decreases the σ difference between two interlayers because GeO2 contains much more oxygens than other germanium oxides as shown in Figure 7. Therefore, compared to the case with TiO2 only, less oxygen atoms will move from the TiO2, so a smaller dipole will develop at the TiO2/GeO2 interface as shown in Figure 8b. Thus, as depicted in the energy band diagram of the proposed structure in Figure

Figure 8. Schematic diagrams showing the oxygen diffusion and the interface dipole formation for (a) the TiO2 only case and (b) the TiO2/GeO2 case where the GeO2 is formed by plasma oxidation and simplified energy band diagrams of (c) ideal Ti/TiO2/n-Ge, (d) practical Ti/TiO2/n-Ge, and (e) Ti/TiO2/GeO2/n-Ge structures. Δ indicates the increase in effective SBH caused by the interface dipole. 35423

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ACS Applied Materials & Interfaces The proposed M−I−S structure exhibits lower contact resistivity even at the moderate Ge doping level, than the M−S structure does with a heavily doped Ge surface. This result proves that if the proposed structure is incorporated into the S/D contact scheme, the S/D doping concentration can be lowered while maintaining or even reducing S/D contact resistance. This is a significant advantage for nanoscale Ge transistors because with the nanoscale CMOS process it is usually difficult to obtain a high electron concentration and form ultrashallow and abrupt junctions. Furthermore, performance variation or mobility degradation can be reduced by decreasing the S/D doping level. In addition, the proposed contact structure is especially recommended for junctionless field-effect transistors (JL FETs), which have smaller S/D doping levels than those of conventional MOSFETs. The JL FET is promising for advanced nanoscale CMOS technology, possessing many advantages over conventional MOSFET such as simplicity, improved short-channel effects, and relaxed mobility degradation.35 However, its drawback has been the degradation of S/D contact resistance because it has a lower S/ D doping level than conventional MOSFET. Fortunately, adopting the proposed M−I−S structure in the S/D region easily solves this problem without the need to increase S/D doping level.

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. ORCID

Gwang-Sik Kim: 0000-0002-9329-4006 Sun-Woo Kim: 0000-0002-2041-1451 Seung-Hwan Kim: 0000-0002-5899-2853 Byung Jin Cho: 0000-0003-3000-5403 Changhwan Shin: 0000-0001-6057-3773 Hyun-Yong Yu: 0000-0001-9446-5981 Notes

The authors declare no competing financial interest.

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4. SUMMARY AND CONCLUSION The M−I−S structure incorporating a TiO2/GeO2 interlayer stack in which the GeO2 layer is formed by the plasma oxidation process has been developed to lower the effective electron SBH and reduce the contact resistance of metal/n-Ge contacts for nanoscale Ge n-channel FETs. In the M−I−S structure, the TiO2 interlayer is adopted as the main interlayer because it has very low tunneling and series resistances and builds a very small energy barrier for electrons at the metal/ TiO2 interface. However, a perfect ohmic contact cannot be obtained by a single TiO2 interlayer because the TiO2/Ge interface exhibits very poor interface quality corresponding to a high Dit level and the interface dipole at the TiO2/unwanted GeOx interface induces an increase in SBH. Therefore, the GeO2 layer is introduced as an interface controlling layer on the n-Ge surface, with the added benefit that it also reduces effective electron SBH by minimizing the interface dipole. The M−I−S structure with the TiO2/GeO2 interlayer stack shows, without any JF degradation, a perfect ohmic J−V characteristic and much larger JR than those of M−I−S structures incorporating a single interlayer (TiO2 only or GeOx only). By adopting the TiO2/GeO2 interlayer stack having their own specialized advantages, the Ti/TiO2/GeO2/n-Ge structure shows not only 0.193 eV of effective electron SBH, meaning that the interlayer stack perfectly unpins the FLP at the Ti/nGe contact, but also 3.5 × 10−5 Ω·cm2 of specific contact resistivity on an n+-Ge substrate with a moderate surface electron concentration (1 × 1017 cm−3). The developed M−I− S structure is a very promising S/D contact structure for overcoming the high S/D contact resistance problem of nanoscale Ge n-channel FETs, and is also recommended for device applications that have S/D doping levels which are not greatly heavy such as JL FETs.

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Doping profile of n+-Ge substrates and method of specific contact resistivity extraction, effect of the postoxidation process on the TiO2 layer, dependency of plasma oxidation time durations on J−V characteristics, electrical analysis of the M−I−S structure with a single GeO2 layer, J−V characteristics of Ti/TiO2/GeO2/ n-Ge substrate with 2 nm-thick TiO2 layer, extraction of the effective SBH through the M−I−S structure on p-Ge substrate (PDF)

ACKNOWLEDGMENTS This work was supported in part by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT, and Future Planning under Grant 2014R1A1A1036090 and in part by the Technology Innovation Program (10048594, Technology Development of Ge nMOS/pMOS FinFET for 10 nm Technology Node) funded by the Ministry of Trade, Industry & Energy (MI Korea).

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REFERENCES

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.6b10947. 35424

DOI: 10.1021/acsami.6b10947 ACS Appl. Mater. Interfaces 2016, 8, 35419−35425

Research Article

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DOI: 10.1021/acsami.6b10947 ACS Appl. Mater. Interfaces 2016, 8, 35419−35425