Integrated Circuits: Chemical and Physical Processing Downloaded from pubs.acs.org by 91.204.15.69 on 11/23/18. For personal use only.
Author Index Anderson, T. J., 276 Aselage, T. L., 276 Baerg, B i l l , 12 Batchelder, Tom, 108 Biefeld, R. M., 297 Chang, K. M., 276 Cho, A. Y., 118 Crisman, E. E., 178 G i l l , William N., 47 Gregory, 0. J., 178 Huber, D., 310 Irene, Eugene A., 31 Kazarinoff, Nicholas D., 47
Olsen, G. H., 221 Plunkett, Joseph C , 127 Pogge, H. B., 241 Reffle, J., 310 Richards, Albert D., 164 Sawin, Herbert H., 164 Schindler, R., 310 Soong, David S., 70 Stroeve, Pieter, 1 Sukanek, Peter C , 95 Thompson, Brian E., 164 Verhoeven, John D., 47
Subject Index A
Abrupt emitter, schematic energy-band diagram under equilibrium, 123f Absorption spectra, SLSs, 304f AC-DC amplitude r a t i o s , r e s i s t development process, 86,87 Acceleration, electron and hole transport, semiconductor, 18 Activation, e l e c t r i c a l , annealing, ion-implanted integrated c i r c u i t s , 138 A c t i v i t i e s , stoichiometric l i q u i d component, Group III-V materials, 286-88 A c t i v i t y c o e f f i c i e n t s , r a t i o of l i q u i d to s o l i d , determination, 288 Aluminum etching procedure, ionimplanted integrated c i r c u i t s , 161 Aluminum-gallium-antimony system, ternary phase diagrams, 292 Amplifiers, monolithic microwave advantages of ion implantation, 156 Amplitude r a t i o s , AC-DC, r e s i s t development process, 86 Anisotropic and isotropic etching, p r o f i l e s , I66f Anisotropic vapor phase epitaxy growth, 233-35 335
Annealing e l e c t r i c a l a c t i v a t i o n , ion-implanted integrated c i r c u i t s , 138 preparation and properties of Ge0 , 192 wafer design defects, 316 Anodic oxidation of germanium, 194 Antimony-gallium system, reduced standard state chemical potential, 283-86 Applications, ion implantation, 142 Assembly, unit processes, 5t Atoms, implanted, depth d i s t r i b u t i o n i n an amorphous target, 130f Axial v e l o c i t y vs. height above support surface, zone r e f i n i n g , 63f 2
B
Baking conditions research opportunities i n r e s i s t technology, 88 wafer fabrication process, 7 Band gap, SLS, v a r i a t i o n , with layer composition and thickness, 302f Band structure, SLS, 301 Bipolar devices i s o l a t i o n processes, 245f
