Nanodicing Single Crystalline Silicon Nanowire Arrays - Nano Letters

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NanoDicing Single Crystalline Silicon Nanowire Arrays Alon Kosloff, Omri Heifler, Eran Granot, and Fernando Patolsky Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.6b03028 • Publication Date (Web): 18 Oct 2016 Downloaded from http://pubs.acs.org on October 23, 2016

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NanoDicing Single Crystalline Silicon Nanowire Arrays Alon Kosloff1, Omri Heifler2, Eran Granot1 and Fernando Patolsky1,2*

1

School of Chemistry, the Raymond and Beverly Sackler Faculty of Exact Sciences Tel-Aviv University, Tel Aviv 69978, Israel

2

Department of Materials Science and Engineering, the Iby and Aladar Fleischman Faculty of Engineering, Tel Aviv University, Tel Aviv 69978, Israel

* To whom correspondence should be addressed: [email protected]

Keywords: Nanowire, nanodicing, single crystal, arrays, semiconductor.

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Abstract Here, we demonstrate a novel method for the production of single-crystal Si nanowire arrays based on the top-down carving of Si-nanowall structures from a donor substrate, and their subsequent controlled and selective harvesting into a sacrificial solid material block. Nano-sectioning of the nanostructures-embedding block by ultramicrotome leads to the formation of size, shape and orientation-controlled high quality nanowire arrays. Additionally, we introduce a novel approach that enables transferring the nanowire arrays to any acceptor substrate, while preserving their orientation, and placing them on defined locations. Furthermore, crystallographic analysis and electrical measurements were performed, proving that the quality of the sectioned nanowires, which derive from their original crystalline donor substrate, are remarkably preserved.


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Introduction Nanotechnology deals with the construction of objects with dimensions in the length scale of 1–100 nm, which are therefore confined to either 0D quantum dots, 1D nanowires, nanotubes and nanoribbons, or 2D nanofilms. The novel properties of matter at these dimensions enable the conception of unique devices applicable in numerous fields1–3. One-dimensional (1D) nanomaterials, e.g. nanowires and nanotubes, represent flexible building blocks that can be applied in a myriad of applications in the fields of electronics 4,5, optics 6 , biological sciences 7–9, medical diagnosis 12,13

devices

, efficient photovoltaic devices

14–17

10,11

, and Li-ion batteries

, thermoelectric

18,19

. Their unique

physical properties, originating from their dimensionality, offer significant advantages over conventional planar materials. The integration of nanowires and nanotubes as core device elements onto virtually any substrate may facilitate the future fabrication of faster and smaller electronics. Numerous fabrication methods have been developed for generating controllable and scalable arrays of 1D nano-materials 20–24. Nevertheless, moving beyond proof-ofconcept of single device fabrication into mass-production of large-scale integrated arrays still poses a significant handicapping challenge. There are two paradigms for the fabrication of nanomaterials: top-down and bottom-up approaches25. The top-down approach refers to the sculpting, or etching, of a bulk source substrate for carving structures down to the nanoscale. The key advantage of topdown based methods is that no further assembly is required; the nanostructures being built in situ. Furthermore, these approaches are routinely applied with high precision and scalability. Notwithstanding their advantages, in all top-down based approaches the composition of the 1D nano-materials is strongly limited to the bulk source substrates (such as silicon, silicon-on- insulator and germanium). The bottom-up approach, instead, aims to create structures by assembly of their elemental building blocks. Importantly, a wide range of materials is therefore available, with no restrictions related to materials derived from available wafer or thin film forms26–28. Based on this approach, the nanostructures can be grown and placed on various surfaces, through assembly-based steps 23.


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During the last two decades, several assembly methods in the framework of the bottom-up approach were demonstrated 23,24. The two main strategies for the bottomup assembly of 1D-nanomaterials are the “grow-and-place” (or post-growth assembly) and the “grow-in-place” (in situ array formation). The former comprises the synthesis of the 1D nano-materials on a donor substrate, followed by their harvesting and transfer to the ‘acceptor’ substrate, with the desired location and orientation. The later “grow-in-place” approach aims to the growth of aligned 1D nano-materials directly on the chip substrate, on specific locations and with predetermined orientation, without the involvement of assembly steps. However, in both strategies, the control over the dimensions, orientation and composition of the resulting nanostructures is not easily achieved, and several handicapping issues such as scalability and reproducibility remain to be solved. Recently, a novel nanofabrication strategy called ‘nanoskiving’29 has been demonstrated. This method involves the deposition of materials onto either: i) a flat sacrificial epoxy block directly

30,31

, or ii) through lithography-shaped structures

located on a release-layer material such as gold 31,32. In both cases, after the deposited material is embedded within the sacrificial epoxy block, the process is followed by a microtome cutting step which yields in case i) long segments of nanowires, or in ii) arrays of nanostructures with the composition of the originally-deposited material 33. These resulting sectioned nanowires/nanostructured arrays exhibit particular characteristics which are derived from their arrangement, composition and innerconfined nano-dimensions. Accordingly, they were applied in interesting optical 29,31,32,34–36

and electronic applications 37–40. Furthermore, the nanoskiving process has

demonstrated the ability to form multiple sections of complex nanostructures arrays, and to transfer them to different acceptor substrates. However, the composition of these nanostructures is usually limited to metals and polycrystalline materials

30

.

Recently, coin-like sectioning of GaAs vertical core-shell nanowire arrays was reported as well 41. Unlike previous nanoskiving studies, in order to obtain long segments of singlecrystalline silicon nanowires, one needs to develop methods that overcome the great difficulty in detaching intact nanomaterials arrays from the donor single-block crystalline wafers. This method should focus on approaches to selectively deblock, through surface-chemistry patterning strategies, top-down etched nanomaterials arrays


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from their mother substrate. This goal should be achieved without affecting the morphology of the de-blocked nanostructures. In this work, we demonstrate a novel approach for the fabrication of onedimensional silicon nanowires/nanoparticles arrays, based on the selective deblocking of the nanostructure arrays from their original crystalline substrate, followed by the nano-slicing of the de-blocked arrays into multiple thickness-controlled slices of the nanomaterial arrays. Additionally, we show how the resulting self-standing sliced nanomaterials arrays can be further transferred onto another acceptor surfaces with a high degree of alignment control, thus allowing the formation of more complex structures such as electrically-active suspended nanowire and wire-on-wire crossbar devices.

Results and Discussion The process for the fabrication of silicon nanowires arrays is depicted in details in Figure 1. First, an array of lines with nanoscale width and of desired length is patterned by e-beam direct writing, on an electron resist film coated on a silicon substrate, Figure 1a. Second, a 100nm thick Ni layer is e-beam evaporated, followed by the resist film lifted-off, thus revealing Ni lines that serve as etching mask elements, Figure 1b. Third, the formation of high nano-wall elements is performed by Deep Reactive Ion Etching, Figure 1c, through a Bosch Process. In order to facilitate the further de-blocking of the nano-walls, we perform an under-etched profile at the bottom section of the nanostructures, Figure 1c inset. This is made by modulating the time-ratio between the two consecutive "Bosch” process steps of etching and deposition 42,43. After removal of the Ni masks, a 30nm thick Au layer was deposited over the nanostructure array by e-beam evaporation, Figure 1d. During the next step, the residual Au-layer located on the top nanostructures surface and on its sidewalls is selectively removed, Figure 1e. This is done by applying a 100nm thick PMMA layer, through spin coating, followed by immersing the sample in an Au-etchant solution. As a consequence, only the nanowalls surface is exposed to the Au-etchant solution, while ensuring that the bottom surface Au-layer remains intact. This step allows the selective strong adhesion of the epoxy resin matrix to the nanostructures surface only. The residual Au layer on the bottom of the donor substrate serves as an


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anti-adhesion agent, which later facilitates the selective de-blocking of the nanostructures arrays from the donor substrate. Fourth, an epoxy-based resin was casted over the nanowalls array, followed by a thermal curing step leading to the formation of a solid epoxy-block, Figure 1f, which is then detached from the surface along with the embedded nanowalls arrays, Figure 1g. Finally, the block containing the nanostructure array is parallel-sectioned by ultramicrotomy, Figure 1h, using a 35-degree inclination angle diamond knife. The sectioning of the block leads to the formation of nanowire arrays embedded within epoxy lamellas of nanoscale thickness. The thickness of the lamella is determined by the ultra-microtome parameters, and can reach a size down to several tenths of nanometers. After a lamella is sliced, it slides onto the surface of a water bath coupled to the knife. In order to transfer the resulting nanowire array onto an acceptor substrate, its embedding epoxy-lamella is lifted by the help of a loop tool, which picks it inside a formed water meniscus-sheet, and then placed on another surface. After the water sheet, located inside the loop, evaporates, the loop is removed, leaving behind the epoxy nano-slab in contact with the acceptor substrate, Figure 2A-1 and 2B-1. This simple procedure produces an array of Si nanowires, embedded within an epoxylamella onto a variety of substrates, such as a) SiO2, b) soft PDMS and c) TEM grids for further morphological characterization. In a), after the direct transfer onto a SiO2 surface (Figure 2A-1), the sample is finally treated by oxygen plasma. This results in the removal of the embedding epoxy medium, and complete exposure of the nanowire elements (Figure 2A-2). In case (b), the PDMS soft block serves as a stamp, by which the epoxy slab can be aligned and transferred onto a precise location along the acceptor substrate (Figure 2B-1), followed by a thermal bonding step (Figure 2B-2) to ensure adhesion of the lamella to the acceptor substrate. After the bonded PDMS stamp is lifted, the epoxy slab remains on the acceptor SiO2 surface (Figure 2B-3), and finally, the nanowires are exposed from their embedding epoxy medium by oxygen plasma treatment (Figure 2B-4). The described alignment and transfer method is carried out using an autocollimator system, by which the orientation of the embedded-nanostructures can be aligned to specific features over the acceptor surfaces. Figure 3 shows scanning electron microscope (SEM) images of the etched nanowall structures on a silicon wafer. These structures consist of nano-walls of different 6 ACS Paragon Plus Environment

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lengths of 15µm (Figure 3A) and 50µm (Figure 3B), and a height and width of 9µm and 300 nm, respectively. Figure 3C reveals the side profile of these structures, where the under-etch profile is observed by a narrower base thickness of 75nm. The under-etch geometry, serves as a breaking point that facilitates the following harvesting step, and increases the array’s transfer yield. The under-etch step importance was confirmed by a comparison of two embedding epoxy blocks, one which contained structures with under-etch profile and the other without under-etch profile (see Supporting Figure S1). In addition, in order to provide a clear demonstration of the applicability of this method to other structures, an array of nanopillars array was created, Figure 3D. However, due to the lower-area-of contact of the nanopillars to the under-surface, the under-etching step is not required (see Supporting Information Section). Figure 4 shows the sectioning results achieved by the ultra-microtomy of the nanowires-embedded epoxy block, after complete etching of the epoxy resin. Notably, continuous Si nanowire, or nanoparticle, arrays are readily formed. Their arrangement and dimensions reflect the geometry of the original de-blocked nanostructure arrays (Figure 3), while their height is defined by the ultra-microtome sectioning parameters selected. Notably, nanowire elements of any desired shape can be obtained by this proposed approach (see Supplementary Figure S2). The shape-controlled nanowall structuctures, of any desired shape, are achieved similarly to the process performed for the straight nanowalls structures, by lithographically-designed etching mask shapes, as illustrated in the original Figure 1. Figure 5 depicts the results of the aligned nanowire transfer approach. Figure 5A shows the formation of nanowire-on-nanowire crossbar structures by the sequential layer-by-layer deposition of aligned lamella-embedded nanowire arrays, while Figures 5B and C show suspended nanowire structures, aligned and placed over a 2 micron-deep step (5B) and channel (5C), respectively. The most striking feature of this newly-developed alignment approach lies in its remarkable capability to align and place the sectioned epoxy-lamellas on any acceptor substrate of interest, without the requirement of external fields, such as magnetic forces 44. Accordingly, it can be considered as a universal approach that applies to various types of nanosectioned semiconducting materials. Furthermore, it opens the possibility to form interconnected complex nanostructures of different chemical compositions. Indeed, 7 ACS Paragon Plus Environment

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this method allows for a better control over array orientation and dimensions, due to the fact that alignment is performed only once for the whole sectioned nanowires array, and does not require the individual alignment of single nanowire elements as per most reported methods 23. However, as for all processes involving nano-sectioning, their throughput mainly depends on the morphological quality of the diamond knife, and might be subjected to scoring and delamination effects 30. The scoring effect might lead to the fragmentation of the formed nanowires, nonetheless, it is significantly reduced by performing the sectioning in a parallel direction to the epoxy-based block orientation. The delamination effect mainly occurs when forming thin sections (200nm thick lamella sectioning, followed by a controlled post-thinning dry etching process (using SF6 plasma chemistry, see Supporting Figure S4) aimed at controllably reducing the nanowire down to the desired dimensions. This post-alignment process step allows for a tight control over the nanowires lateral dimension, while removing surface defects which might result from the sectioning process. Moreover, the direct transfer of thin sections (ca. 70nm) onto holey carbon grids allows the further TEM characterization of the resulting nanowires. Figure 6A and inset shows HRTEM micrographs of sectioned nanowires, each nanowire exhibiting dimensions of 70nm height, 300nm width and 15µm length. Accordingly, the two dimensional Fourier transform of the lattice-resolved images, Figures 6B and D (insets), can be indexed to the diamond structure of silicon, at its [111] (Figure 6B) and [112] (Figure 6D) zone axis direction. Consequently, these results confirm that the sectioning process does not affect the nanowires crystallographic characteristics. Furthermore, the nanowire crystallographic direction is dictated by the donor substrate from which these nanostructures are formed. In order to prove the applicability of the resulting nanowire elements we investigated the electrical properties of a nano-sectioned nanowires through the fabrication of FET-type devices, Figure 7. The electrical measurements were made under water gate conditions. Figure 7A depicts the source-drain voltage Ids vs Vsd curve of a single nanowire device, under different gate voltages (Vg), and Figure 7B 8 ACS Paragon Plus Environment

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shows its transconductance curve (Isd vs Vg), at a constant Vds of 0.1V. The observed electrical properties indicate on gate-sensitive devices, which resemble typical nanowire-based FET devices (see Supplementary Figure S5 for the characterization of five representative nanowire FET devices on single chip)45,46. In summary, we have successfully demonstrated a new-slicing method for the fabrication of single crystalline silicon nanowire arrays. The success of this method mainly depends upon two key parameters: a) forming nanostructures with an underetch profile, and b) adding an area-selective release layer that contacts the substrate surface area while leaving the surface area of the etched nanostructure exposed. Both parameters promote the successful selective de-blocking, by which silicon etched nano-wall structures arrays can be harvested within epoxy-based blocks at a high yield. The width and length of the fabricated nanowires correlates to the dimensions of the initially etched and sectioned structures. Their height is controlled by the ultramicrotomy sectioning. However, in order to increase the yield and reduce damaging effects, such as scoring and delamination, we suggest sectioning thicker nanowire elements followed by reducing their dimensions using a post-sectioning etching process. Also, the orientation of the nanowires array is determined by the position of the original etching masks, which in turn, are defined by the EBL process. In addition, we have demonstrated a novel aligned-bonding method that allows a further control over the orientation and location of the array at its transferred location. The resulting sectioned nanowires display excellent crystallinity and electrical properties. Their crystalline quality was confirmed by TEM analysis. Electrical measurements of single nanowire-based devices show a distinctive gate-voltage dependent behavior, thus, they may serve a variety of potential future applications, such as biosensors. Although in nano-slicing approaches the sectioned area is limited to ~7x7mm (the available knife dimensions), this proposed method presents significant advantages, as it enables to perform multiple nano-sections transfers of high quality single-crystal nanowire arrays, while positioning them at defined locations onto the acceptor substrate.


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Supporting Information The Supporting Information is available free of charge on the ACS Publications website at DOI:….. (I) Materials and methods; (II) The effect of under-etch breaking point on the harvesting process; (III) Shape-controlled nanowalls structures (IV) The sectioning thickness; (V) Electrical characterization of five representative nanoFET devices.

Acknowledgements This work was in part financially supported by the Legacy Fund, Israel Science Foundation (ISF).


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Figure Captions

Figure 1. Process steps of the selective deblocking-nanoslicing method. (a) A Si substrate is spin-coated with PMMA electron resist, followed by a line-array formation by e-beam lithography. (b) Deposition of 100nm Ni metal lines that serve as etching masks. (c) Substrate dry-etching with under-etch profile, creating nanowalls structures. (d) 30nm anisotropic Au deposition. (e) 100nm PMMA coating and selective Au removal from sidewalls. (f) Epoxy casting and hardening. (g) Deblocking of epoxy-embedded nanostructures, and (h) Sectioning Si nanowires by ultra-microtomy.

Figure 2. Placement of nanowire arrays. Route A- Non-oriented alignment. (1) Loop placement and water evaporation which places the lamella in an arbitrary position. (2) O2 plasma treatment for epoxy lamella removal, exposing the nanowire array. Route B- Bonding-oriented alignment to a precise location. (1) Lamella transfer to PDMS substrate similar to the way described in A1. (2) Alignment and bonding to a precise location over a SiO2 surface patterned with alignment marks. (3) Following the bonding step the lamella remains on the surface and (4) Nanowire array exposure by O2 plasma treatment (as in A2).

Figure 3. Nanostructures made by DRIE. SEM images (at 30 degrees tilt) showing (A) Nano-walls array of 8 microns height, 300nm width, 15 microns length and (B) 50 microns length (scale bars of A and B: 25 µm). (C) Front view of a single nano-wall structure showing under-etch profile (scale bar: 1µm). (D) Array of Si nanopillars of 200nm diameter and 5 microns height (scale bar: 10 µm). The inset image show a higher magnification of the array (scale bar: 2 µm).


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Nano Letters

Figure 4. Si nanostructures sectioning results. SEM images (at 30 degrees tilt) showing (A) Sectioned nanowires having 300nm thickness and a length of 50 microns. (B) 15 microns, 300 nm long sectioned nanowires. The insets show low-magnification images of the corresponding arrays. Scale bars: A.10 µm (inset 25 µm), B. 2.5 µm (inset 10 µm). (C) 70nm thick, 15 microns long nanowire (scale bar 3 µm). Inset image: sectioned kinked nanowire (scale bar 10 µm). (D) Nanoparticles array (having a 200nm diameter and 250nm thickness) fabricated by the sectioning of a vertical nanopillars arrays (scale bar 10 µm).

Figure 5. SEM images (at 45 degrees tilt) showing the alignment and placement of (A) a 50um-long nanowires crossbar array, (B) Suspended nanowires tips over a 2microns deep step, and (C) Suspended nanowire over a 2 micron-depth trench.

Figure 6. TEM micrographs showing the crystalline structure of the resulting nanowire sections. (A) Low magnification of a representative single nanowire (scale bar: 100 nm). Inset: Low magnification image of a representative 70nm-thick sections array. (B) High resolution image of the nanowire with its corresponding FFT micrograph (inset) showing a representative pattern of [111] Si zone axis (scale bar: 5 nm). (C) Low magnification image of a single nanoparticle (scale bar: 20 nm). Inset: Low magnification image of a nanoparticles array having 50 nm thickness (scale bar: 500 nm). (D) High resolution image of the nanoparticle with its corresponding FFT micrograph (inset), showing a pattern of [112] Si zone axis.

Figure 7. Electrical properties of the resulting 50nm-thick nanowires. (A) Ids vs Vsd curves measured under different applied gate voltages: -0.6 V (black), -0.4 V (red),0.2V (blue), 0 V (green), +0.2V (purple). The inset image shows a side view of the electrical device (scale bar 2.5 µm). (B) Transconductance curve (Isd vs Vg), at a constant Vds of 0.1V.


Nano Letters

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a

b Ni evaporation and lift-off

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Si EBL Resist Ni Au PMMA

Anisotropic dry etch with under-etch profile

Epoxy Resin

d

c Au evaporation

e

PMMA coating and selective Au etching.

f Epoxy resin casting

Deblocking

g

h Sectioning by ultramicrotome

Figure 1 ACS Paragon Plus Environment

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Route A: Non-oriented array transfer. 1)

Section transfer by loop placmentand water dehydration.

Route B: Aligned array transfer.

1)

PDMS SiO2 acceptor substrate

2)

Epoxy removal by O2 plasma treatment.

Alignment and thermal bonding.

2)

PDMS lifting.

3)

4)

Figure 2

ACS Paragon Plus Environment

Epoxy removal by O2 plasma treatment.

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Figure 3


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Figure 4


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Figure 5

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TOC graphics 64x34mm (300 x 300 DPI)


Nanodicing Single Crystalline Silicon Nanowire Arrays - Nano Letters

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