Non-Destructive Readout Complementary Resistive Switches Based

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Non-Destructive Readout Complementary Resistive Switches Based on Ferroelectric Tunnel Junctions Zhongnan Xi, Chunyan Zheng, and Zheng Wen ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b18363 • Publication Date (Web): 25 Jan 2018 Downloaded from http://pubs.acs.org on January 26, 2018

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ACS Applied Materials & Interfaces

Non-Destructive Readout Complementary Resistive Switches Based on Ferroelectric Tunnel Junctions Zhongnan Xi,† Chunyan Zheng,† and Zheng Wen†,* †

College of Physics and National Demonstration Center for Experimental Applied Physics

Education, Qingdao University, Qingdao, 266071, China *Corresponding author. E-mail: [email protected] Abstract: Recently, complementary resistive switches (CRS) have attracted considerable attention due to the effective suppression of the sneak leakage that is an inherent problem of crossbar memory arrays. In this work, we propose a new CRS device enabling non-destructive readout based on back-to-back in series Pt/BaTiO3/Nb:SrTiO3 ferroelectric tunnel junctions (FTJs). The FTJ elements exhibit not only a non-volatile resistance switching but also a typical diode-like transport in the high resistance state (HRS), due to the ferroelectric-enhancement on the Schottky barrier of the BaTiO3/Nb:SrTiO3 interface. With the rectifying characteristic, the complementary HRS+LRS (low resistance state) and LRS+HRS states can be well distinguished and non-destructively read out by a subthreshold voltage. In addition, the sneak current is significantly suppressed in the Pt/BaTiO3/Nb:SrTiO3 CRS crossbar array and the maximum scaling size is increased by about 50 times, in comparison to the array constituted by only the single-FTJ devices. These results facilitate the design of high-performance resistive memories based on the crossbar architecture. KEYWORDS: Resistive switching, Complementary resistive switches, Crossbar array, Sneak leakage, Ferroelectric tunnel junction, Ferroelectric field effect, Schottky barrier

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1. INTRODUCTION Nowadays, the mainstream Si-based FLASH memories have been expected to run into physical limits of scaling in the near feature. As prominent alternatives, resistive switching memories have emerged and attracted great attention.1-3 In general, the resistive memory consist of two metallic electrodes separated by an insulator layer, which exhibits electrically-switchable resistance state between a high (HRS) and a low (LRS) level in a non-volatile fashion.1-3 Based on various materials and different mechanisms, many resistive devices have been proposed in past decades, such as the resistance random access memories that are functioned by the formation/rupture of conductive filaments inside the insulators1-4 and the ferroelectric-resistive memories that are realized by the polarization-modulation on the band alignment across the metal/ferroelectric/metal devices5-11. An important feature of the resistive switching memories is the two-terminal structure, making the integration of them into passive crossbar array feasible.12-17 The resistive devices therefore have great potential to achieve fast write/read access, low power consumption, and, more importantly, high data-storage density with the cell size reduced to 4F2 (F=minimum feature size). However, sneak path is an inherent problem of the passive crossbar array13,14,18, as depicted in Figure 1a. When reading, a sneak current (Isneak) takes place and flows through the unselected cells, which becomes the most pronounced if the selected cell is in HRS while the surrounding unselected ones are in LRS, i.e., the so-called the worst case.14 In addition, the Isneak can be further broadened when the scaling-size of crossbar array (N rows × M columns) is extended.14 With increasing Isneak that superposes on the cell current (Icell), the read margin

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between the HRS and the LRS degrades and the readout may be failure eventually. These drastically limit the integration density of crossbar array. A number of approaches have been proposed to solve the crosstalk issue.13,19-24 For example, incorporation of selectors in series with the resistive memories20,23,24 or adopting rectifying cells19,21,25 have been reported effective to suppress the sneak current because of the enhancement in nonlinearity of the LRS current-voltage (I-V) curve. In 2010, Linn et al. have pioneered complementary resistive switches (CRS), which are composed of two conductive-filament Pt/SiO2/GeSe/Cu elements connected antiserially with an intermediate electrode18, as schematically shown in Figure 1b. Complementary switching of the CRS devices gives rise to bistable HRS+LRS and LRS+HRS combined states (Figure 1b), representing the binary numbers “0” and “1”, respectively, which differs from the traditional resistive memory that adopts the LRS and HRS for programming. The Isneak is hence suppressed since the two storage states are all close to the HRS (assuming RHRS>>RLRS). As a result, significantly enhanced data-storage density has been achieved in the Pt/SiO2/GeSe/Cu CRS crossbar array.18 Recently, similar CRS devices have also been realized in oxides by carefully controlling the migration of charged defects, such as the TiOx/Al2O3-based 3D hybrid devices26, the Pt/Ta2O5/Ta/Pt[ref. 27], the Pd/Ta2O5-x/TiOy/Pt[ref. 28], the all Ti-oxide homo- and hetero-stacks29, and the W/Nb2O5-x/NbOy/Pt[ref. 30]. As shown in Figure 1c, the conductive-filament-type CRS device is read by a pulse Vread larger than the Vth, where the Vth is the switching threshold of a single resistive element.18 With this large Vread, one of the complementary states is switched to an intermediate

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LRS+LRS combination and hence a large readout current (Iread) is detected, while the other state still stays at a high resistance close to the HRS.18 By comparing the Iread, the stored HRS+LRS and LRS+HRS can be distinguished, even though the two states exhibit similar resistor-like I-V curves27,28,30-33 (Figure 1b). However, this kind of readout scheme is destructive and an extra rewrite operation is required to recover the information18 (Figure 1c), which degrades the effective reading time and the write/read endurance of the CRS devices. Hurk et al. have proposed a non-destructive readout approach by utilizing volatile resistive elements.34 But the overall operation time is increased as an extra interval is required for the reverting of the volatile LRS back to the HRS. Tappertzhofen et al. have suggested a non-destructive capacitance readout.35 It, however, increases the complexity of both the programming and the crossbar circuit. Here, we propose a new CRS device enabling non-destructive readout, which is constituted by the elements that exhibit diode-like transport in the HRS. As shown in Figure 1d and 1e, the rectifying I-V curves of the HRS+LRS and LRS+HRS states can be easily distinguished by a Vread far below the Vth and the stored information is read without the destructive switching to the intermediate LRS+LRS state. Metal/ferroelectric/semiconductor (MFS)-type ferroelectric tunnel junctions (FTJs) are adopted as the CRS elements since the transport characteristics can be artificially engineered by controlling the ferroelectric barrier thickness and the doping concentration of the semiconducting electrode.36-38

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Figure 1. (a) Schematic of a passive CRS crossbar array, where only the sneak path from the nearest neighboring cells is drawn. The CRS cell can be composed of the conductive-filament resistive switches (b) or the MFS-type FTJs (d). Semi-log I-V characteristics (b,d) and the corresponding write/read protocols (c,e) for the conductive-filament-type and the FTJ-type CRS devices, respectively. In (c) and (e), the LRS+HRS and HRS+LRS states are assumed to denote "0" and "1", respectively, and only the Iread are drawn for clarity. 2. EXPERIMENTAL SECTION Device Fabrication. The 4 unit-cell-thick BaTiO3 (BTO) films were used as the barriers, which were epitaxially grown on n-type single-crystalline (001) Nb:SrTiO3 (NbSTO, Nb: 0.1wt%) substrates by pulsed laser deposition, as reported previously.38 The Pt top electrode layers were deposited on the surface of BTO/NbSTO using DC magnetron sputtering. The Pt/BTO/NbSTO heterostructures were then fabricated by multiple-step photolithography and Ar ion milling to form the FTJ devices with the junction area of 5 µm in diameter and the capped Pt contact pad of 200 µm in diameter. A 100 nm-thick SiO2 insulating layer was deposited to separate the Pt pad and the NbSTO electrode, as schematically shown in Figure

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2a and Figure S1 (Supporting Information). The Pt/BTO/NbSTO CRS devices were defined by connecting two fabricated FTJs externally with a common NbSTO electrode (see Figure 3a). The 2×2 crossbar arrays were formed by connecting four discrete FTJ or four CRS cells on homemade holders with patterned Pt lines as the word- and the bit-line, respectively, as shown in Figure S2 (Supporting Information). Characterization. The piezoresponse force microscopy (PFM) hysteresis loops were performed on an Asylum Research Cypher scanning probe microscope in a DART (dual a.c. resonance tracking) mode with triangle pulse waveforms applied on the Pt/Ti-coated tip. A Keithley 2400 SourceMeter was used to measure resistance switching of the FTJ and the CRS devices. The capacitances were recorded using an Agilent 4294A impedance analyzer with a frequency of 4 MHz and an oscillation level of 30 mV. For the Pt/BTO/NbSTO FTJs, the testing pulses were applied on the Pt top electrodes and the NbSTO substrate was grounded through an indium ohmic contact pad. For the CRS devices, the voltage was applied on one of the Pt electrodes and the other electrode was grounded. 3. RESULTS AND DISCUSSION

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Figure 2. (a) Schematics of the Pt/BTO/NbSTO FTJ device (left) and the band diagrams (right) for the LRS and the HRS, respectively, in which the thick red arrows denote the BTO polarization and the dotted arrows indicate the transport of electrons. (b) PFM hysteresis loops and (c) hysteretic R-V and C-V loops of the Pt/BTO/NbSTO device. The inset in (c) depicts the pulse sequence applied on the Pt top electrode, in which the resistance is read by a 0.5 V pulse and the capacitance is recorded by an oscillation (see Experimental section), following each write pulse. (d) The I-V curves for the LRS and the HRS. According to our pervious work, the 4 unit-cell-thick Pt/BTO/NbSTO FTJ can be regarded as a metal/semiconductor diode with the interfacial Schottky barrier modulated by the polarization reversal in ultrathin BTO barrier via a ferroelectric field effect.38 As depicted in Figure 2a, when the BTO polarization is pointing to the n-type NbSTO electrode (see the upper band diagram), the positive ferroelectric charges are screened by the major electrons 7



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and the space charge region is narrowed. The interfacial Schottky barrier is hence suppressed and the FTJ device is switched to the LRS with the transport dominantly controlled by the BTO barrier. As the polarization is switched pointing to the Pt electrode, the space charge region is widened since the negative ferroelectric charges sweep the electrons away from the BTO/NbSTO interface. The Pt/BTO/NbSTO tunnel junction is switched to the HRS with enhanced Schottky barrier in both the width and the height (see the bottom band diagram). Figure 2b shows PFM hysteresis loops of the Pt/BTO/NbSTO device measured on the Pt electrode. The coercive voltages are +1.9 and -3.9 V, as indicative of the minima of the amplitude. The large negative coercive voltage can be ascribed to the existence of space charge region, which increases in width when the polarization is pointing away from the NbSTO and shares the applied voltage together with the BTO barrier. Figure 2c shows capacitance-voltage (C-V) measurement of the Pt/BTO/NbSTO, where the device is preset to the HRS and then written by a triangular pulse train of 0 → +V → 0 → -V → 0 (see the inset). The capacitance is acquired following each write pulse. In the MFS-type FTJ, the BTO barrier (CBTO) is in series with the space charge region (CSC) and the measured capacitance (C0) is given by

=

+

. As shown, the Pt/BTO/NbSTO device exhibits a hysteretic

C-V loop between ~54 pF in the HRS and ~72 pF in the LRS with the threshold voltages of +2.0 and -4.0 V, in consistent with the coercive voltages of the PFM hysteresis loops. These indicate the ferroelectric modulation of the space charge region and hence the Schottky barrier. Accompanying with the modulation, a typical resistance-voltage (R-V) loop is observed in the device following the triangular pulse sequence, as shown in Figure 2c. The

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RHRS/RLRS ratio extracted is ~5000. Figure 2d shows the I-V curves in a subthreshold range of -1.0 ~ +1.0 V. In the LRS the transport is dominated by electron tunneling through the BTO barrier and a resistor-like symmetrical I-V curve is observed. In the HRS, the Schottky barrier is enhanced with the widening of the space charge region, which can be ~1.0 eV in height and ~10 nm in width, as reported previously.38 The tunneling current is suppressed and a diode-like transport behavior is observed with a large rectification ratio of ~103.

Figure 3. (a) Schematics of the Pt/BTO/NbSTO CRS device (left) and the band diagrams (right) for the HRS+LRS and the LRS+HRS, respectively, in which the thick red arrows denote the BTO polarization and the dotted arrows indicate the transport of electrons. (b) Hysteretic I-V loop and (c) the HRS+LRS and the LRS+HRS I-V curves of the CRS device. (d) Reproducible write/read operation of the device, where the upper and the bottom panels are the applied voltage and the resulting current, respectively. With the rectifying feature of the HRS, the proposed non-destructive readout CRS device can be achieved by connecting two Pt/BTO/NbSTO tunnel junctions antiserially, as 9



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depicted in Figure 3a. The FTJ-based CRS exhibits complementary HRS+LRS and LRS+HRS states upon polarization direction of the two BTO barriers (see the band diagrams). When switching, the write voltage firstly drops over the HRS element (as RHRS>>RLRS, due to the large RHRS/RLRS ratio) until it is switched to the LRS with the BTO polarization towards the common NbSTO electrode. Then the LRS element starts to respond the applied voltage and is switched to the HRS with the polarization pointing away from the NbSTO. As a result, the CRS device is switched from the HRS+LRS to the LRS+HRS, or vice versa. The complementary resistance switching is demonstrated by hysteretic I-V measurement following a voltage waveform of 0 → +V → 0 → -V → 0. As shown in Figure 3b, the Pt/BTO/NbSTO CRS device experiences continuous switching of HRS+LRS → LRS+LRS → LRS+HRS and LRS+HRS → LRS+LRS → HRS+LRS, respectively, by applying positive and negative voltage with the amplitude larger than |-2Vth|. This resembles that reported previously in the conductive-filament-type CRS devices.18 Figure 3c shows I-V curves of the FTJ-based CRS in the HRS+LRS and the LRS+HRS states, respectively, in which the device behaves like two diodes but with opposite rectifying direction since the transport is alternatively governed by the HRS Schottky barrier of each Pt/BTO/NbSTO element. Owing to the diode-like character, the complementary states can be well distinguished by a subthreshold voltage, such as +1.0 V, giving rise to the non-destructive readout. The RHRS+LRS/RLRS+HRS ratio is ~103, determined by the rectification ratio. Write and read operations of the CRS device are shown in Figure 3d. The device is, in prior, set to the HRS+LRS and then written by alternating -14.0 and +14.0 V pulses to

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reproducibly achieve the LRS+HRS ("0") and the HRS+LRS ("1") state, mimicking the practical devices. The written states are read by +1.0 V following each write pulse. The resulting current indicates that the stored information can be non-destructively read out, as expected, and a RHRS+LRS/RLRS+HRS ratio ~1000 is achieved, in agreement with the observation in the I-V curves (Figure 3c).

Figure 4. Sneak leakage issue for the worst case of the crossbar arrays that are constituted by the single-Pt/BTO/NbSTO FTJs (a) and by the FTJ-based CRS devices (b), respectively, where the upper panels are the schematics of the arrays and the bottom panels are the equivalent circuits. The I-V curves of the 2×2 crossbar arrays of the single-Pt/BTO/NbSTO (c) and the CRS (d) devices, respectively, where the I-V curves of the HRS and the LRS+HRS for the discrete devices are also shown for comparison. (e) Normalized readout

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margin ∆V/Vpu as a function of number of rows N (where M=N) for the single-FTJ and the CRS arrays. Figure 4a and 4b demonstrate the sneak path issue of the worst case for the crossbar arrays (M=N=2) constituted by the single-Pt/BTO/NbSTO FTJs and the CRS devices (Figure S1), respectively. We adopt the one bit-line pull-up read scheme, that is, only one bit line is pulled up and all other bit lines are floating when each word line is selected.14,18 The corresponding readout I-V curves of the selected HRS (LRS+HRS) cell and an unselected LRS (HRS+LRS) cell are shown in Figure 4c (Figure 4d), where the HRS (LRS+HRS) I-V curve for the discrete device is also shown for comparison. In the crossbar array, when the selected cell is read at Vread, Vread/2 is applied across the unselected cells that are connected in parallel with the selected one (see the equivalent circuits in Figure 4a and 4b). The nonlinearity factor of the I-V curve, that is, the ratio of the current at Vread to that at Vread/2, plays a critical role in the sneak leakage through the unselected LRS cells. As shown in Figure 4c, the nonlinearity extracted from the LRS I-V curve is only ~13, resulting in low parasitic resistance of the unselected cells at Vread/2. As a result, the single-FTJ crossbar array suffers from serious sneak leakage, in which the readout current of the selected HRS cell in just a 2×2 size is even increased by two orders of magnitude in comparison to that of the discrete device. In the CRS crossbar array the transport is predominantly controlled by the Schottky barrier and the diode-like I-V curve exhibits a large nonlinearity factor of ~300, as shown in Figure 4d. The parasitic resistance of unselected CRS cells at Vread/2 is thus increased, resulting in the suppression of the sneak current. As shown, the selected

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LRS+HRS cell exhibits only a slight increase in current, compared to the discrete counterpart. The readout margin ∆V normalized to the pull-up voltage Vpu (∆V/Vpu) for the two crossbar arrays are calculated by solving the Kirchhoff equation23, ∆V

=

) ""( ) ) ( "" ( )× # $ "" !" ( !") ""( ) ""( ) ( # ""% &# !" ( !") '

*

−

) ""( ) ) ( "" ( )× # $ """ !" ( !") ""( ) ""( ) ( # """% &# !" ( !") '

(1) *

where Vread = +1.0 V, Rpu is set to RLRS (RHRS+LRS) and R"0" and R"1" are RLRS (RHRS+LRS) and RHRS (RLRS+HRS), respectively, for the single-FTJ (CRS) array. All the parameter values are extracted from the I-V curves shown in Figure 4c and 4d. As shown in Figure 4e, the calculated maximum scaling size with at least 10% readout margin is only N=11 for the single-FTJ array, which increases significantly to N=530 for the CRS counterpart due to the suppression of the sneak leakage. 4. CONCLUSIONS In summary, a non-destructive readout CRS device has been proposed and implemented in back-to-back in series Pt/BTO/NbSTO FTJs. The Pt/BTO/NbSTO element exhibits a RHRS/RLRS ratio of ~5000 between a resistor-like LRS and a diode-like HRS due to the ferroelectric-modulation of the interfacial Schottky barrier. Owing to the large resistance ratio and the rectifying feature, the complementary HRS+LRS and LRS+HRS states can be well distinguished by a subthreshold Vread, enabling the non-destructive readout scheme. In addition, the sneak leakage is significantly suppressed in the CRS crossbar array due to the enhanced nonlinearity of the I-V curve. The maximum scaling size is thus increased by about 13



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50 times, compared to the array constituted by only the single-FTJ cells, suggesting great potential of the FTJ-based CRS devices in high-density data storage. The suppression of the sneak leakage also makes the CRS crossbar array a promising candidate to achieve low power consumption, which, together with the previous accomplishments, such as the voltage control of magnetism due to intriguing interface coupling39, facilitates the design of high-performance memory devices. On the other hand, the proposed CRS scheme can be widely expended to other types of resistive devices that have the diode-like transport, for example the most recently proposed in-plane ferroelectric domain wall resistive memories.40 Besides, it is worth noting that typical rectification characteristics have been observed in the LRS of p-n junction-like Co/BTO/(La,Sr)MnO3 FTJs due to the migration of oxygen vacancies and the corresponding change in band alignment, which provides another approach to suppress the sneak leakage.25 The resistive switching because of the oxygen vacancies has also been reported in Pt/BTO/NbSTO FTJs and a secondary R-V hysteresis loop with a RHRS/RLRS ratio ~10 is observed at room temperature.41 Here, the secondary loop isn’t observed in our FTJ devices, suggesting that the ionic migration may not be a dominant reason responsible for the memory properties in the present work even though the existence of oxygen vacancies can’t be completely ruled out. Recently, the ferroelectric-driven resistance switching has been proved experimentally in the Pt/BTO/NbSTO tunnel junctions by studying the junction transport as functions of temperature and strain, in which the resistive memory effect decreases and tends to vanish with decreasing polarization of the BTO barrier.42,43

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ACKNOWLEDGMENTS This work was jointly sponsored by National Natural Science Foundation of China (Grant No. 11574169), Natural Science Foundation of Shandong (ZR2017JL001), and an innovation project of Qingdao (17-1-1-71-jch). Supporting Information. Device structures for the Pt/BTO/NbSTO FTJ and the 2×2 crossbar arrays constituted by the single-FTJ and the CRS devices, respectively.

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Non-Destructive Readout Complementary Resistive Switches Based

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