Proton-Conductor-Gated MoS2 Transistors with Room Temperature

Subscriber access provided by UNIVERSITY OF TOLEDO LIBRARIES

Article

Proton-Conductor-Gated MoS2 Transistors with Room Temperature Electron Mobility of >100 cm2V-1s-1 Yongsuk Choi, Hyunwoo Kim, Jeehye Yang, Seung Won Shin, Soong Ho Um, Sungjoo Lee, Moon Sung Kang, and Jeong Ho Cho Chem. Mater., Just Accepted Manuscript • DOI: 10.1021/acs.chemmater.8b00568 • Publication Date (Web): 19 Jun 2018 Downloaded from http://pubs.acs.org on June 19, 2018

Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.

is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.

Page 1 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Chemistry of Materials

Proton-Conductor-Gated MoS2 Transistors with Room Temperature Electron Mobility of >100 cm2V-1s-1 Yongsuk Choi,† Hyunwoo Kim,† Jeehye Yang,# Seung Won Shin,‡ Soong Ho Um,†,‡ Sungjoo Lee,† Moon Sung Kang,*,# and Jeong Ho Cho*,†,‡, § †

SKKU Advanced Institute of Nanotechnology (SAINT), ‡School of Chemical Engineering, §Department of

Nano Engineering, Sungkyunkwan University, Suwon 440-746, Republic of Korea. #

Department of Chemical Engineering, Soongsil University, Seoul 156-743, Republic of Korea.

*Corresponding author: M. S. Kang ([email protected]) and J. H. Cho ([email protected])

ABSTRACT Room temperature electron mobility of >100 cm2V-1s-1 is achieved for a few-layer MoS2 transistor by use of a polyanionic proton conductor as the top-gate dielectric of the device. The use of a proton conductor that inherently exhibits a cationic transport number close to 1 yields unipolar electron transport in the MoS2 channel. The high mobility value is attributed to the effective formation of an electric double layer by the proton conductor, which facilitates electron injection into the MoS2 channel, and to the effective screening of the charged impurities in the vicinity of the device channel. Through careful temperature-dependent transistor and capacitor measurements, we also confirm quenching of the phonon modes in the proton-conductor-gated MoS2 channel, which should also contribute to the achieved high mobility. These devices are then used to assemble a simple resistive-load inverter logic circuit, which can be switched at high frequencies above 1 kHz.

ACS Paragon Plus Environment

Chemistry of Materials 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Page 2 of 20

Two-dimensional layered materials (2D materials) have emerged as promising semiconductor candidates in the post-silicon era.1-4 Since the isolation of single-layer graphene, a series of 2D materials have been developed, ranging from transition metal dichalcogenides (TMDCs) to the most recent black phosphorus.5-8 In particular, molybdenum disulfide (MoS2) is one of the most extensively investigated TMDC materials owing to its distinctive band gap and superior carrier mobility;1,

4, 9-14

MoS2 was

theoretically predicted to have a room temperature (RT) electron mobility higher than 100 cm2V-1s-1.15, 16 The first reported MoS2 field-effect transistors (FETs) based on a conventional SiO2 gate dielectric exhibited prominent electrical characteristics with an electron field-effect mobility (µ) in the range of 0.1–10 cm2V-1s-1 at RT.4, 12, 17 A higher µ of up to ~50 cm2V-1s-1 could be obtained by adopting suitable contact materials or by removing undesirable traps on the material surface via annealing.9, 13, 18-22 Further research efforts were made by employing high-k gate dielectric layers such as Al2O318, 23, 24 and HfO212, 25, 26 grown by atomic layer deposition (ALD). These high-k gate dielectric layers provided a suitable dielectric environment as well as and a way to engineer the charge carrier density effectively, which, in turn, would significantly suppress the influence of charged impurities. Consequently, RT electron mobility ranging from 20 to 150 cm2V-1s-1 could be attained.27 Simple lamination of the high-k layer as either a buffer layer inserted between MoS2 and the substrate or a top encapsulating layer also led to a substantial enhancement of the carrier mobility of MoS2. Even though the high-k layer itself did not act as the gate dielectric material of the devices, it caused enhancement of the carrier mobility through effective screening of the detrimental charged impurities.24 Alternatively, utilization of electrolyte materials as the gate dielectric for MoS2 and other 2D materials has also been attempted.28-37 The electric double layer (EDL) formed in an electrolyte is capable of inducing accumulation of an ultra-high charge density in the contacting 2D materials at low operation voltages. For example, ionic-liquid-gated MoS2 devices provided a significant carrier mobility of over 40– 60 cm2V-1s-1.33 However, the devices reported thus far have yielded ambipolar characteristics including both electron transport and hole transport capabilities.28,

33

Achievement of ambipolar characteristics using a

single-channel material may lead to the development of transistors with novel features, such as possible light emission from the transistor channel based on the radiative recombination of the injected electrons and holes;38, 39 nevertheless, realization of a unipolar transport channel is also critical from the viewpoint of development of transistors for use in the fabrication of complementary logic circuits with low power consumption.39, 40 This is because logic circuits with ambipolar transistors typically suffer from a poor signal-to-noise margin owing to the high OFF-state current of the devices. Another unresolved issue pertaining to electrolyte gating is that the resulting devices often suffer from a slow switching speed owing to the sluggish motion of ions. In view of these problems, utilization of protons (H+)—the smallest and the most abundant ions—as the gating ions for operating EDL transistors may be a clever way to fully harness the benefits of gating of MoS2 with an electrolyte. In particular, thin, solid-state proton conductors (a polyanionic polymer network counter-balanced with numerous counter-cations, i.e., protons) are a promising class of high-capacitance dielectrics for gating MoS2 and 2D materials.41-43 Because the transport number of ACS Paragon Plus Environment

Page 3 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


protons in a proton conductor film is nearly unity, only the electron density in the contacting channel would be modulated effectively; mobile anions would be necessary for modulation of the hole density via formation of the EDL.44 Therefore, MoS2 transistors with unipolar n-type characteristics can be prepared. In addition, proton conductors typically exhibit high ionic conductivity as they rely on the smallest ion possible. Thus, the switching speed of the transistor could be enhanced. Herein, we report achievement of an electron mobility of >100 cm2V-1s-1 for a few-layer MoS2 transistor at RT through use of a polyanionic proton conductor as the top gate dielectric of the device. The high mobility value is attributed to the following: i) effective thinning of the injection barrier from the electrode to the MoS2 channel via accumulation of an enormous amount of charge by the electrolyte, ii) powerful screening of charged impurities by the excessive ions present in the gate, and iii) quenching of undesired phonon modes that prevent efficient band transport. In addition, we confirmed that a simple resistive-load inverter logic circuit comprising the MoS2 transistor could be switched at high frequencies above 1 kHz. Figure 1a shows a schematic cross section of a top-gate MoS2 FET with a proton conductor as its gate dielectric. A benchmark poly(styrenesulfonic) acid (PSSH) was selected as the proton conductor for gating the MoS2 transistors. The chemical structure of PSSH is shown in Figure 1b. The capacitive properties of the PSSH layer were first investigated using a conventional metal-insulator-metal (MIM) capacitor testbed (the inset in Figure 1c). The testbed was prepared by spin coating of an aqueous PSSH solution (9 wt%) onto Cr/Au metal pads and subsequent thermal evaporation of the Au electrode on top. The thickness of the PSSH film deposited between the electrodes was ~300 nm. The electrical response of protons was analyzed by applying AC voltage with a frequency of 20 Hz to 1 MHz to the capacitor and measuring the device impedance (Z) under high vacuum (below 10-4 Torr). The effective capacitance (Ceff) and phase angle (θ) of the PSSH film were plotted as functions of the AC voltage frequency (ƒ) (Figure 1c). The effective capacitance of the device was estimated using the out-of-phase impedance (Z″ = 1/2πfCeff) according to previous works.44 At f = 20 Hz, Ceff = 1.1 µF/cm2 was obtained, which corresponded to the specific capacitance of the EDL capacitor (CEDL) for the PSSH proton conductor. This value is higher than that achieved from conventional high-k oxide dielectrics such as Al2O3 and HfO2. Such a high value is attributed to the formation of an ultrathin EDL at the interface by the migration of positively charged protons (R1 in Figure 1d). The high Ceff value remained until the frequency reached 20 kHz. Up to this frequency, θ remained close to -90°; a θ value closer to 0° indicates that the resistive components in the device dominated the operation, whereas a θ value closer to -90° indicates that the capacitive elements were more dominant. θ approached 0° with increasing frequency, and θ was -45° at 80 kHz, which serves as the criterion for separating the dynamic response modes of the proton conductor. At frequencies above 80 kHz, the AC voltage response of our PSSH proton conductor was governed by the resistive behavior of the electrolyte, rather than its capacitive behavior (R2 in Figure 1d). The explanation remained valid until f = 200 kHz, at which frequency the θ value became -45° again. Above 200 kHz, the electrical response would be dominated by a capacitive process again, but this time, it would be based on the dipolar relaxation of the component ACS Paragon Plus Environment


Page 4 of 20

materials. Thus, the response in this high-frequency regime should reflect the pure dielectric properties of the layer excluding ionic motion (R3 in Figure 1d). The appearance of the three distinct dynamic regions is consistent with those reported for previous EDL capacitors.44-47 To fabricate transistors, a few-layer MoS2 flake was mechanically exfoliated from a bulk MoS2 crystal and then transferred onto a SiO2/Si wafer through the Scotch-tape method.48 The thickness of the flake, estimated via atomic force microscopy (AFM), was around 2 nm (Figure 1e), corresponding to the trilayer of MoS2. The Raman spectrum also confirmed the trilayer MoS2 flake (Figure 1f). The difference between the vibration peak positions for the in-plane E12g mode (379 cm-1) and the out-of-plane A1g mode (403 cm-1) was around 24 cm-1, which agreed well with the previously reported difference for trilayer MoS2. Cr/Au metallic contacts were formed on top of the MoS2 layer by electron beam lithography. The width (W) and length (L) of the channel were 2.3 µm and 2.1 µm, respectively. To laminate the proton conductor layer, the same aqueous PSSH solution as that described above (9 wt%) was spin-coated onto the MoS2 layer. Finally, a Au gate electrode was thermally deposited onto the channel region. Figure 1g shows the transfer characteristics (drain current (ID) versus gate voltage (VG)) of the MoS2 transistor gated by the PSSH proton conductor under a fixed drain voltage (VD = 0.1 V). The device turned on at a gate voltage close to 0 V and ID increased sharply with a positive increase in VG, which is typical behavior of an n-type transistor channel. Importantly, the PSSH-gated MoS2 transistors exhibited unipolar electron transport within 2 V, which is different from the ambipolar behavior, i.e., both electron transport and hole transport capabilities, exhibited by previous electrolyte-gated MoS2 devices.28, 33 For example, use of an ionic liquid yielded multilayer MoS2 transistors with a typical V-shaped transfer characteristic. In these previous works, the unipolar behavior could be achieved only from monolayer MoS2, which inherently exhibits a large hole injection barrier with metal electrodes because the bandgap of the monolayer flake is larger than that of the multilayer. The unipolar behavior of our PSSH-gated MoS2 transistors in this case is attributed to the imbalance between the cation mobility and the anion mobility in the proton conductor.44 The protons are readily mobile to form the EDL, and they can contribute to the accumulation of electrons in MoS2; however, the motion of the polyanionic backbone is restricted, and thus, it cannot induce holes effectively. Despite the low operation voltages of below 2 V, ID could be modulated by more than four orders of magnitude. The large modulation is attributed to the high capacitance of the PSSH proton conductor, which permits inducing a high density of electrons in the contacting MoS2 channel at such a small gate voltage. The resulting 2D charge density (Q) is roughly equal to the product of the specific capacitance of the dielectric layer (C) and the effective gate voltage, i.e., VG - VON, where VON is the turn-on voltage of the device. In particular, the ID values in the ON state of the device, e.g., at VG = 2 V, were substantially higher than the gate current (the gray curve in the graph), indicating that the leakage current through the PSSH layer could be ignored. The results also indicate that no significant electrochemical reaction of PSSH is expected at voltages below 2 V, and therefore, stable device operation could be achieved (Figure S1 shows a series of transfer characteristics (at VD = 0.05 V) of a PSSH-gated MoS2 transistor that was obtained upon consecutive VG sweeps. Figure 1h shows the output characteristics (ID versus VD relationship measured at different fixed VG values) of the MoS2 transistor gated ACS Paragon Plus Environment

Page 5 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


by the PSSH proton conductor. A linear relation in the output characteristics was observed at VD values of up to 0.1 V. Next, we estimated the electron mobility of the trilayer MoS2 flake gated by the PSSH proton conductor from the electrical characteristics of the devices. The field-effect mobility of a given semiconducting material is typically obtained from the slope of the transfer characteristic in the linear regime, i.e., at low VD, by using the standard relation µ = (L/W)/(C·VD)·(dID/dVG).30,

32, 33

From the

transconductance at a given VG (i.e., dID/dVG from the given ID–VG relation), one can estimate µ as a function of VG. We emphasize here that the use of an appropriate value of C is critical when estimating the mobility of a 2D material. In particular, C would not be simply equal to CEDL when a 2D material is gated by an electrolyte. The overall capacitance of an electrolyte-gated 2D material should include the capacitance associated with the EDL formation and the quantum capacitance of the 2D material (Cq) connected in series. Thus, 1/C = 1/CEDL + 1/Cq. The quantum capacitance of a 2D material is associated with its density of states (DOS).49 When the transistor is in its OFF state, the Fermi level (EF) of the 2D material lies at the center of the bandgap, and thus, both its DOS and its Cq are low. In this case, 1/C ≈ 1/Cq or C ≈ Cq in consideration of the high CEDL (>1 µF/cm2). Of course, this condition is not suitable for estimating the field-effect mobility, because dID/dVG = 0 when a transistor is in its OFF state. When the transistor is in its ON state—which is the condition under which the field-effect mobility of the given 2D material is estimated—EF of the 2D material will be located near the conduction/valence band of the material, and thus, its DOS as well as its Cq would be high. If Cq is comparable to CEDL, then C would be estimated from their combined contribution. That is, C = [1/CEDL + 1/Cq]-1. Of course, the combined C value would be smaller than that of CEDL alone. Accordingly, one should not simply use the specific capacitance obtained from the MIM testbed structure (Figure 1c) to estimate the electron mobility of the device. Instead, the appropriate value of C should be obtained from the metal-insulator-semiconductor (MIS) capacitor structure embedded in the transistor. For this purpose, a separate Au-PSSH-MoS2 MIS structure was prepared separately on a heavily doped n-type Si wafer without an oxide layer. The measurement could be performed by recording the capacitance of the device while applying a bias to the gate electrode and simultaneously grounding the MoS2 layer through the heavily doped n-type Si wafer. From the measurement, we acquired C as a function of VG, and these values could be directly used to estimate µ of the device as a function of VG. Figure 2a shows the transfer characteristics of the above-described MoS2 transistor collected at three different VD values (0.01, 0.02, and 0.1 V). Figure 2b shows the C versus VG relationship of the MIS testbed that was obtained at a frequency of 20 Hz. The shape of the C–VG curve was asymmetric, wherein the capacitance values obtained at positive VG values were higher than those obtained at negative VG values. The asymmetry can be understood from the large difference in the mobilities of the protons and polyanions in PSSH that are involved in inducing electrons and holes, respectively, in MoS2. At positive VG, mobile protons can readily form the EDL at the PSSH–MoS2 interface. Here, the measured capacitance value reflects the DOS of the conduction band of the MoS2 layer; a higher C is obtained at higher positive VG values. Meanwhile at negative VG, formation of the EDL (even at a low frequency of 20 Hz) at the PSSH– ACS Paragon Plus Environment


Page 6 of 20

MoS2 interface is not achieved effectively owing to the immobile nature of the polyanions. Therefore, the measured capacitance value would remain low. In fact, a larger asymmetry in the C–VG characteristics was observed when the measurement was performed at a higher frequency, at which the different kinetic responsivities of the cations and anions in the PSSH became pronounced. From the slope of the transfer characteristic at different VG values and the capacitance value at the given VG read from the C–V characteristics, we could extract the electron mobility of the MoS2 channel as a function of VG. Figure 2c shows the mobility of the MoS2 layer that was obtained as a function of VG (which is directly proportional to the electron density) collected at different VD values. Interestingly, the electron mobility exhibited a peaking behavior with increasing gate voltage. The initial increase in carrier mobility is typically attributed to the increased density of carriers, which fill the shallow traps below the transport energy states (trap-filling effect). Additionally, it can be attributed to enhanced injection of carriers at the metal–semiconductor junction, which is considered as a major hurdle for engineering the mobility of 2Dmaterial-based FETs. The contacting MoS2 layer can be electrostatically doped through induction of a high electron density by use of an electrolyte gate dielectric, and consequently, the width of the Schottky barrier formed at the metal–MoS2 interface will reduce greatly (barrier-thinning effect). The lowering of the contact resistance at higher VGs could be independently confirmed from 4-probe transistor measurement (Figure S2). As a result, the maximum mobility was obtained at VG = 0.6 V in this study. Roughly, this condition corresponds to an electron density of 1.1 × 1012 cm-2 (= CS·(VG－Vth)/e, where Vth is the threshold voltage of the device, i.e., 0.1 V, and e is the element charge). At this gate voltage, a high RT electron mobility, as high as 131 cm2V-1s-1, was obtained, particularly at VD = 0.01 V (the drain-voltage-dependent mobility is discussed below). This value is comparable to the value (133 cm2/Vs) estimated directly from the Drude model (conductivity = charge · density · mobility). We emphasize that such a high electron mobility was obtained from a device applied with voltages smaller than 1 V. Both the trap-filling effect and the barrierthinning effect should be more pronounced at higher VG. However, at VG values higher than 0.6 V, the electron mobility was lowered with an increased induced carrier density. The appearance of such a negative mobility–carrier density relation at these VG values indicates that an additional factor needs to be considered in understanding the conduction. In fact, a similar negative mobility–carrier density relation was obtained for other semiconductor systems, particularly when they were gated by an electrolyte. These results are often attributed to the limited energy states available when more than half of the DOS in the conduction band (or valence band) is filled with induced carriers. However, the carrier density of 1.1 × 1012 cm-2 is not enough to fill half of the states of the band. Therefore, we consider that this is not the origin of the observed negative mobility–carrier density relation for our PSSH-gated MoS2 channel. Instead, the reduced mobility at high VG values can be attributed to the negative influence of the disorder induced by the EDL at the proton conductor–MoS2 interface. Because the packing of ions within the EDL is random, the resulting Coulomb field varies randomly with the location of the contacting MoS2; consequently, an energetic disorder is generated in the contacting MoS2. This negative influence of the energetic disorder induced by the EDL is known to be critical for 2D materials,29 which would become more pronounced with increasing VG, under ACS Paragon Plus Environment

Page 7 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


which condition a tighter EDL is formed. We note that the negative mobility–carrier density relation was not observed for the MoS2 channel when it was gated by the underlying SiO2 gate dielectric. Figure 2d shows a series of transfer characteristics obtained using the SiO2 gate dielectric at different fixed VD values (the output characteristics of the devices are shown in Figure S3). To extract µ this time, a fixed value of C (=11 nF/cm2) was used, instead of the use of a VG-dependent value as was done above for estimating µ from the I–V relations obtained using PSSH. This is because the capacitance of the system, which can be viewed as a quantum capacitor connected in series with a dielectric, would be determined by the smaller capacitance of the two, which is the capacitance of the SiO2 layer. The extracted mobility also increased initially with increasing VG up to 15 V (Figure 2e) and then exhibited a saturated behavior. The initial positive mobility–carrier density relation can be understood from the influence of shallow traps on transport, especially at low VG. We note that this critical gate voltage of 15 V corresponds to a condition of accumulation of an electron density of 2.9 × 1012 cm-2. The value is on the same order as that of the electron density that yields the maximum mobility for the PSSH-gated channel. We interpret that a shallow trap density of ~1012 cm-2 needs to be filled before the optimized transport occurs for both the PSSH-gated and the SiO2-gated MoS2 channels. More importantly, the observation of saturated mobility behavior above this critical gate voltage supports that the unique negative mobility–carrier density relation obtained for the PSSH-gated channel at high VG values is associated with the disorder induced by the EDL formation. Figure 2f summarizes the maximum mobility values obtained for the PSSH-gated MoS2 transistor at different VD values. Interestingly, the maximum mobility of the MoS2 channel reduced with increasing VD. In general, a higher field-effect mobility value is obtained from transistor I–V characteristics when it is collected at higher VD. This is because the charge injection rate at the metal–semiconductor junction or the hopping rate in the channel is typically enhanced with the application of an electric field according to the Poole–Frenkel effect. In fact, such an enhancement of µ with increasing VD was observed for our MoS2 channel when it was gated by the underlying SiO2 gate dielectric. The data points represented by solid black circles in Figure 2f were obtained from the transfer characteristics acquired using the SiO2 gate dielectric (Figure 2d). A clue to understanding this unusual VD dependence of mobility of the PSSH-gated MoS2 channel can be obtained by comparing its performance with that of the SiO2-gated channel. This comparison revealed that electron mobility values obtained using the PSSH-gated channel were consistently higher than those obtained by gating the same MoS2 flake through the underlying SiO2 gate dielectric. As mentioned above, the high mobility of the PSSH-gated devices can be attributed to the enhanced injection of charge carriers upon the use of the electrolyte gate dielectric. In view of the fact that the enhanced carrier injection is dependent on the EDL formation, the voltage difference that sustains the EDL should be a critical factor in determining the injection rate. This voltage difference can be expressed as VG - Vchannel, where Vchannel is the effective channel potential of the MoS2 layer. When VD is small (closer to 0 V), Vchannel would be close to 0 V, and consequently, the potential applied to the gate electrode would be used up entirely to form the EDL. When a higher VD is applied to the device, however, the effective channel potential will be higher, and ACS Paragon Plus Environment


Page 8 of 20

therefore, the EDL has to be formed under a smaller potential difference. The formation of a weaker EDL will lead to less effective charge injection into MoS2 and eventually to lower electron mobility. We note that this explanation for describing the VD dependence of mobility holds only for an electrolyte-gated channel whose electrical properties are strongly influenced by carrier injection. Another interesting finding of the comparison of the MoS2 flake gated by PSSH and that gated by SiO2 is that the turn-on voltage (VON) of the resulting transistor-defined as the voltage that induces a sharp rise in the transconductance-is substantially different. While VON for the SiO2-gated channel is -50 V, that for the PSSH-gated MoS2 channel is close to 0 V. The large negative VON for the SiO2-gated channel is attributed to the presence of positively ionized impurities at the MoS2–SiO2 interface; such negatively ionized impurities dope the MoS2 channel significantly enough to yield a normally-on channel for the device. With such defect sites, the subthreshold swing (VSS) of the device was found to be ~1280 mV/dec. VSS of a transistor is associated with the density of defects and traps at the semiconductor–dielectric interface such that =

10 (1 + )

where k is the Boltzmann constant, T is the temperature, e is the elementary charge, CS is the specific capacitance of the gate dielectric, and Dit is the interfacial defect density. Through this relation, the associated defect density was estimated to be ~1.4 × 1012 eV-1cm-2, which is consistent with the values reported for previous oxide-gated MoS2 transistors (SiO2, Al2O3, and HfO2).11, 25, 50 When PSSH was applied on top of the MoS2 flake and used as the gate dielectric, VON of the channel shifted positively to 0 V and VSS was suppressed to a value as low as 67 mV/dec (Figure S4); VSS for an ideal, defect-free channel at RT (i.e., when Dit = 0) is 60 mV/dec. The higher specific capacitance of the PSSH layer itself may alone contribute to the lowering of VSS. However, MoS2 layers gated with top HfO2 dielectric, which exhibits a comparable specific capacitance (0.4 µF/cm2) to the PSSH layer in the present study, are reported to yield VSS of 100 mV/dec.25 Therefore, other origins on the low VSS of the PSSH-gated MoS2 channel should be considered. Screening of the positively ionized impurities located on the MoS2 surface that is done by the electrolytic PSSH layer should be one of the key additional factors in lowering VSS as well as Dit (~0.3 × 1012 eV-1cm-2), which should be also associated with the apparent positive shift of VON. Note that Dit for the MoS2 channel gated with a top HfO2 dielectric layer is ~2.3 x 1012 cm-2,25 supporting that MoS2 channel undergoing weaker influence of impurities can be formed when it is interfaced with PSSH layer. Under these circumstances, it is obvious that the mobility of the MoS2 channel should be higher when it is gated by PSSH than by SiO2. To further analyze the enhanced charge transport in the PSSH-gated MoS2 transistors, temperature (T)-dependent mobility measurements were performed. We emphasize that temperature-dependent mobility values have to be estimated carefully from transistor measurements, especially when devices are gated by an electrolyte. This is because not only the carrier mobility term in the transistor I–V relation but also the specific capacitance of an electrolyte varies considerably with temperature, as the capacitive process of an ACS Paragon Plus Environment

Page 9 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


electrolyte relies on the motion of ions. This is not the case for conventional transistors gated by an oxide gate dielectric layer; the dielectric polarization is less sensitive to temperature variation, and thus, the specific capacitance of oxide gate dielectric layers can be assumed to be invariant with respect to temperature. Accordingly, we also performed a separate experiment to monitor the temperature-dependent variation of the capacitance of the PSSH layer; additionally, we recorded the C–V characteristics of the MIS devices at different temperatures (300–210 K) (Figure 3a). All the C–V characteristics were consistently asymmetric, just as they were at RT (Figure 2b). Figure 3b shows a plot of the specific capacitance values as a function of temperature, obtained at different VG from the Au-PSSH-MoS2 MIS capacitor. Because the ionic motion becomes slower at lower temperatures, the capacitance of the PSSH reduced gradually with decreasing T. We attribute the sharp transition below 240 K to the freezing of ionic motions, which prevents EDL formation. Therefore, we focused our analysis in the temperature regime above this freezing temperature (240–300 K). Using the temperature-dependent C–V characteristics (Figure 3a) and the temperature-dependent I– V characteristics (Figure 3c), we could obtain the mobility of the PSSH-gated MoS2 flake as a function of temperature (Figure 3d). For obtaining these data, we used the maximum mobility value at a given temperature, which was obtained at a nearly fixed carrier density of ~1 × 1012 cm-2 over the given temperature range. The PSSH-gated MoS2 channel was found to show a negative temperature–mobility correlation such that µ ~ T-γ with the scaling factor γ equal to 0.7. The results indicate that the mobility is limited by phonon scattering. Such phonon-limited mobility behavior was also observed in our MoS2 channel when it was gated by the underlying SiO2 dielectric (solid black circles in Figure 3d), but its scaling factor was much larger (γ = 1.1). The smaller γ value obtained for the PSSH-gated device indicates quenching of the phonon modes in the MoS2 channel in the presence of PSSH. Quenching of phonon modes in the MoS2 channel in the presence of a top-gating material was reported previously. Top gating of a MoS2 flake with a high-k dielectric was known to suppress the homopolar phonon mode specifically. Presence of an ionic liquid on top of a MoS2 flake was also reported to quench phonon modes. Finally, the PSSH-gated MoS2 transistor was utilized in assembling a resistive-load inverter to examine the operation speed of the device. An electrical circuit diagram of the resistive-load inverter is shown in Figure 4a. Different resistors (with resistance ranging from 1 MΩ to 20 MΩ) were connected to a PSSH-gated MoS2 transistor (the single device yielded VSS = 69 mV/dec and µ = 61 cm2V-1s-1 at VD = 0.5 V; see Figure 4b), and the voltage response of the resulting circuit was examined. At a fixed VDD of 0.5 V, an output voltage (VOUT) that coincided well with the magnitude of VDD (corresponding to the output logic state 1) was obtained at a negative input voltage (VIN) (corresponding to the input logic state 0) and VOUT close to 0 V (corresponding to the output logic state 0) was obtained at a positive VIN (corresponding to the input logic state 1). A sharp signal inversion was observed near 0 V, with a signal gain close to 4 (Figure 4c and S5). Both the output signal and the gain of the logic scaled with VDD. Figure 4d shows the inversion behavior of the resistor (5 MΩ)-load inverter at different VDD levels (from 0.2 to 1.0 V) over the given VIN range. The gain was expected to be larger when a complementary inverter was assembled. The dynamic ACS Paragon Plus Environment


Page 10 of 20

response of the inverter was also investigated. VIN was switched between +1 V and -1 V at different speeds (ranging from 1 Hz to 1 kHz), whereas VDD was fixed at 0.5 V. Figure 4e shows the resulting signal inversion for the resistive-load inverter at various frequencies. A clear signal inversion was observed up to 1 kHz. This result implies that our PSSH-gated MoS2 transistors have good potential for more complicated logic applications. The results are comparable to what are achieved from other electrolyte-gated inverters based on other 2D materials.51 Further improvement in the switching speed of the device can be achieved by engineering the device geometry (such as the channel length).52, 53 We also note that the results obtained from the resistive-load invertor established the minimum operation speed. The operation speed would improve further if a complementary inverter were assembled using an n-type PSSH-gated MoS2 channel and a p-type channel with equivalent mobility. In summary, we demonstrated a high electron mobility (>100 cm2/Vs) of a few-layer MoS2 flake at RT. This mobility was achieved by employing a proton conductor, PSSH, as the gate dielectric of the transistor. Effective formation of an EDL by the protons resulted in enhanced electron injection from the electrode to the MoS2 flake, and this, in turn, led to an enhancement of the gate-voltage-dependent. In addition, the use of an electrolyte aided in screening of the charged impurities in the vicinity of the MoS2 channel and the undesired phonon modes of MoS2, which together yielded transport properties superior to those when the flake was gated simply by a conventional oxide dielectric. The high capacitance of the proton conductor as well as its simple processability would be of great benefit for practical applications of the device.

METHODS Device fabrication: To fabricate transistors, high quality MoS2 (SPI Supplies, Inc) flakes were mechanically exfoliated and transferred through the Scotch-tape method onto a heavily n-doped Si/SiO2 wafer (SiO2 layer thickness = 300 nm). After the exfoliation, MoS2 flakes with uniform thickness (2-5 nm) were selected by using optical and atomic force microscopes. Following e-beam lithography and subsequent thermal deposition of the contact metals, the source and drain electrodes (2/40 nm of Cr/Au) were defined onto the selected MoS2 flakes. The resulting MoS2 transistors were annealed at 200 °C under H2:Ar (1:9) flow for 3 h. The thermal treatment was to remove adsorbed impurities such as PMMA residues from the e-beam lithography. A 100nm thick proton conductor layer was deposited onto the channel by spin casting (at 3000 rpm for 1 min) a 9 wt% dilute solution of poly(styrenesulfonic) acid (PSSH) in DI water (Aldrich). Residual water was removed from the film by subsequent thermal treatment at 110°C for 90 sec. The thickness of the resulting PSSH layer was 100 nm. Finally, the top gate electrode was formed by thermally evaporating the contact metal (50 nm of Au) through a shadow mask that was carefully aligned manually under optical microscope. The fabrication processes to prepare the metal-insulator-semiconductor capacitor were same as those described above, except that a heavily n-doped Si wafer without the oxide layer was used as the substrate and that steps to form the source/drain contacts were skipped. ACS Paragon Plus Environment

Page 11 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Device Characterization: The electrical impedance of the PSSH dielectric was measured by a Hewlett Packard 4284A precision LCR Meter. The electrical characteristics of the MoS2 transistors were measured by a Keithley 4200-SCS instrument. All the measurements were carried out in dark and vacuum (

Proton-Conductor-Gated MoS2 Transistors with Room Temperature

Recommend Documents