Selective Deposition of Multiple Sensing Materials on Si Nanobelt

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Selective deposition of multiple sensing materials on Si nanobelt devices through plasma-enhanced chemical vapor deposition and device-localized Joule heating Ru Zheng Lin, Kuang-Yang Cheng, Fu-Ming Pan, and Jeng-Tzong Sheu ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b13896 • Publication Date (Web): 07 Nov 2017 Downloaded from http://pubs.acs.org on November 8, 2017

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ACS Applied Materials & Interfaces

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Selective deposition of multiple sensing materials on

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Si nanobelt devices through plasma-enhanced

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chemical vapor deposition and device-localized

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Joule heating

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Ru-Zheng Lin1, Kuang-Yang Cheng2, Fu-Ming Pan1, and Jeng-Tzong Sheu2* 1

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Graduate Program for Nanotechnology/Department of Materials Science and Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 30050, Taiwan

*2

Institute of Biomedical Engineering, College of Electrical and Computer Engineering, National

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Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 30050, Taiwan

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KEYWORDS: Silicon nanobelt, Localized Joule heating, Plasma-enhanced atomic layer

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deposition, Plasma-enhanced chemical vapor deposition, Selective deposition

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ABSTRACT

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This paper describes a novel method, using device-localized Joule heating (JH) in a plasma

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enhanced atomic layer deposition (PEALD) system, for the selective deposition of platinum (Pt)

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and zinc oxide (ZnO) in the n– regions of n+/n–/n+ polysilicon nanobelts (SNBs). COMSOL

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simulations were adopted to estimate device temperature distribution. However, during ALD

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process, the resistance of SNB device decreased gradually and reached to minima after 20-min

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JH. As a result, thermal decomposition of precursors occurred during PEALD process. Selective

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deposition in the n- region was dominated by CVD instead of ALD. Selective deposition of Pt

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and ZnO films has been achieved and characterized using atomic force microscopy, scanning

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electron microscopy, and transmission electron microscopy.

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Because of their high sensitivity in response to changes in surface potential, several silicon

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nanodevices [e.g., silicon nanowire (SiNW) field-effect transistors and silicon nanobelt (SNB)

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devices] have been developed for sensing applications1–6. Without specific modifications,

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however, silicon nanodevices do not exhibit significant selectivity toward most chemical or

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biological species. Therefore, modification of the surfaces of silicon nanodevices with sensing

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membranes or materials is mandatory for sensing applications. Suitable modification of the

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surfaces of nanodevices can also increase the limits of detection and shorten the response times7–

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10

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of sensing materials onto silicon nanodevices has been achieved using self-assembled monolayer

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(SAM) techniques11, lift-off processes12, shadow masks13, device Joule heating (JH) plus SAMs14,

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and device JH plus lift-off processes15. Nevertheless, SAM processes, lift-off processes, and

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shadow mask techniques is very hard to modify selectively only at specific regions of the device

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surface, especially when device is further scaled down. Moreover, selective deposition of

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multiple sensing materials on Si nanobelt devices through device-localized Joule heating and

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PECVD can reduce process complexity and cost in device preparation. Sensing materials are

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self-aligned and selectively deposited in the n- region.

, especially when the target species is present at a very low concentration. Surface modification

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Driven by the modern integrated chip (IC) industry, thermal atomic layer deposition (ALD)

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and chemical vapor deposition (CVD) have emerged as important techniques for the deposition

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of a variety of materials16–18 for many applications19-20. In addition, plasma-enhanced ALD

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(PEALD) and plasma-enhanced CVD provide more freedom in terms of processing conditions21-

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electronic behavior26. Therefore, in this study, selective deposition of sensing materials at the n–

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region of SNB was accomplished using SNB device JH in a PEALD system. Figure 1a provides

and can lead to superior properties in terms of film density23-24, impurity content25, and

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a schematic representation of the selective deposition of materials on an SNB. With control over

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the JH bias of an individual SNB device in a PEALD chamber, Pt and ZnO can be selectively

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deposited at the surface of the hot spot of an individual SNB channel. Because of the long

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semiconductor Debye length in the n– region, SNB devices with sensing materials deposited in

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the n– region provided the highest responses to changes in the surface potential. Moreover, each

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SNB device could operate under self-heating in the n– region through the application of a JH bias,

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such that the best sensing response to various specific species could be obtained for gas sensing.

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The structure of the SNB and the fabrication process flow have been presented

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previously15; each device featured five SNBs in parallel and connected to two metal pads. There

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were 36 devices a single same chip. The channel thickness of the SNB was 59 nm. The SNB

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included three doping regions: a 2-µm-long n– region in the middle and two 5.5-µm-long n+

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distal regions. The n- regions were implanted with 8 × 1013 cm-2 of phosphorus at 20 keV. The n+

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regions were implanted with 3 × 1015 cm-2 of arsenic at 30 keV, respectively. The resistance of n-

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, n+, and contact via was 30.3 kΩ, 6.06 kΩ, and 1.84 kΩ, respectively, which implies the power

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dissipation at n- regions is ca. 5-fold larger than that at the n+ regions. To estimate the

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temperature under JH at various DC voltages, the ID–VD curves (Vds = ±0.1 V) were measured for

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device resistances via a thermal chuck under various temperatures, as displayed in Figure 1b (the

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ID–VD curves was shown in Fig. S1a). Based on these data, the resistances under JH biases were

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measured so that the device surface temperature could be estimated. The biased voltages to JH

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temperatures were 20 V–474 K, 24 V–517 K, 28 V–544 K, and 32 V–586 K (Fig. 1c). We were

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aware, however, that there could be difference between the real device temperature and the

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estimated JH device temperature. Such a discrepancy might result from JH occurring not only in

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the n– region but also in the two n+ regions, and from the temperature coefficients of resistance


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(TCRs) of the n– and n+ regions being different when the SNB device was measured via thermal

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chuck. Therefore, the surface temperature distribution of the SNB device under DC bias JH was

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simulated through three-dimensional (3D) finite-element analysis using COMSOL Multiphysics

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4.2 (see Fig. S1b, S1c and S1d in the Supporting Information). The settling time of the

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temperature distribution around the device was also observed using COMSOL (Fig. S1e). It took

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10 µs to stabilize the temperature distribution around the SNB device when applying JH. Despite

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that the settling time of device JH temperature did not affect our DC JH, it is important for future

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pulse mode JH application.

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To investigate the possibility of selective deposition using device-localized JH in a PEALD,

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a

PEALD

system

was

modified

to

provide

an

external

bias

(see

Fig.

S2a).

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Trimethyl(methylcyclopentadienyl)platinum (MeCpPtMe3) and diethylzinc (DEZ) were used as

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precursors for the selective deposition of Pt and ZnO, respectively, in the n– regions of SNB

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devices. In PEALD, typical H2O ligand-exchange reactions were replaced O2 plasma treatment.

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Figure 2 presents atomic force microscopy (AFM) and top-view scanning electron microscopy

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(SEM) images of SNBs under a bias of 20 V after PEALD (details of ALD parameters see

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Figure S2b) for selective deposition for various numbers of cycles (10, 20, and 30). The top-view

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SEM images reveal Pt and ZnO nanoclusters on the surface of the SNBs after 10 cycles of

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deposition. Both the Pt and ZnO nanoclusters were formed through Volmer–Weber growth27.

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When the number of cycles of PEALD increased to 20 and 30, the aggregation of the

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nanoclusters intensified. AFM was also used to characterize the material average thickness and

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average coverage in the n– region. The average profile of AFM scans in the area of 3µm x 0.5µm

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was measured. The arithmetic average of surface roughness, Ra, outside the n- region was also

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calculated. The average thickness was calculated in terms of ∆Z (peak-to-Ra) along the SNB


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device (from X to X´) (see Fig. S3); The coverage length was then estimated from the length

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above Ra in the n- region (see Fig. S3). For Pt, the average thicknesses were 3.85 ± 1.1 nm after

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10 cycles, 15.23 ± 1.23 nm after 20 cycles, and 24.12 ± 1.02 nm after 30 cycles; the growth per

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cycle (GPC) was 8.04 Å/cycle. For ZnO, the average thicknesses were 4.12 ± 0.83 nm after 10

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cycles, 23.12 ± 1.27 nm after 20 cycles, and 57.64 ± 0.82 nm after 30 cycles; the GPC was 19.21

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Å/cycle (Fig. 2d). For Pt, the average coverages were 0.656 ± 0.03 µm after 10 cycles, 0.734 ±

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0.02 µm after 20 cycles, and 0.97 ± 0.02 µm after 30 cycles; for ZnO, they were 0.48 ± 0.03,

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0.694 ± 0.02, and 1.103 ± 0.03 µm, respectively (Fig. 2e). A comparison of the profiles in

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Figures S1c and S3 reveals a corresponding relationship with the temperature distribution in the

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n– region for both Pt and ZnO. As a result of the faster deposition rate (ca. 2.3 times), the sizes of

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the ZnO nanoclusters were greater than those of the Pt nanoclusters under otherwise identical

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deposition conditions. Figure 3 presents the temperature effect upon JH with a fixed number of

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PEALD deposition cycles (10 cycles). Agglomeration of the nanoclusters became evident upon

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increasing the temperature in the n– region. For Pt, the average thicknesses were 5.18 ± 1.01 nm

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at 24 V, 11.2 ± 1.01 nm at 28 V, and 26.7 ± 1.02 nm at 32 V; for ZnO, the average thicknesses

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were 7.8 ± 1.02 nm at 24 V, 18.8 ± 1.02 nm at 28 V, and 38.8 ± 1.23 nm at 32 V at the two sides,

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as well as 4.4 ± 1.02 nm at the middle of n– region (Fig. 3d). For Pt, the average coverages were

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1.09 ± 0.02 µm at 24 V, 1.36 ± 0.04 µm at 28 V, and 0.88 ± 0.02 µm at 32 V; for ZnO, these

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values were 1.14 ± 0.03, 1.437 ± 0.06, and 0.09 ± 0.03 µm, respectively (Fig. 3e).

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The average coverages reached their maxima for the selective depositions of both Pt and

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ZnO under a bias of 28 V. At a bias of 32 V, the high device surface temperature resulted in high

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mobility, such that the average coverage of Pt was lower, but larger nanoclusters were observed

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in the middle of the n– region. Moreover, the ZnO thickness was characterized by two different

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thicknesses in the n– region: a thinner structure in the middle of the n– region and thicker

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structures at the two sides of the n– region (Fig. S3e). We used cross-sectional transmission

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electron microscopy (TEM) to investigate the lateral morphologies after PEALD Pt selective

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deposition (10 cycles) on the SNB at JH powers of 20, 24, 28, and 32 V (Fig. S4a); the

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compositions of Pt and ZnO were confirmed through TEM-EDX analysis (Fig. S4b). The TEM

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images revealed that the SNB channels were completely covered by a thin Pt layer when the JH

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power was 24 or 28 V, forming trigate-like structures. For JH biases of 20 and 32 V, the SNB

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appeared to be covered by Pt nanoparticles, rather than thin films (Fig. S4a). At low bias and

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cycle number, the TEM images reveal similar trigate-like surface coverage after the selective

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PEALD deposition of Pt and ZnO (24 V, 10 cycles), as displayed in Figure S4b.

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Pt and ZnO were also deposited onto a 6-inch wafer having the same structure

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(Si/SiO2/Si3N4) by thermal chuck, and under the same PEALD conditions with a chuck

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temperature of 474 K (see SI for the PEALD parameters). Figure 4a comparisons the deposition

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rates for PEALD under the device JH and thermal chuck heating. The deposition rates for both Pt

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and ZnO using device JH plus PEALD were much higher than those obtained using PEALD with

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thermal chuck. Moreover, because of the very short precursor pulse times (Pt, 50 ms; ZnO, 10

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ms), Pt deposition using the thermal chuck required 1000 cycles to deposit Pt at a thickness close

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to 1 nm (inset to Fig. S5a). To determine the cause of the different deposition rates under thermal

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chuck heating and device JH in the PEALD chamber, COMSOL simulations were conducted to


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monitor the temperature distributions for the thermal chuck with a temperature of 474 K and for

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device JH with n– hot spots reaching 474 K. The heat transfer rate was described using the

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equation28

4

ௗ்

‫ݍ‬௫" = −݇ ௗ௫

(1)

5

where ‫ݍ‬௫" is the total rate of heat transfer per unit area along the x direction and k is the thermal

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conductivity (W/m•k). The temperature boundary condition at a value of x of 50 µm was set at

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298 K. Figure 4b displays the temperature distributions in the PEALD chamber for both the

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thermal chuck and JH device (from the middle of the five devices to the chamber boundary). The

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simulation results in Figures 4b reveals that the temperature decreases linearly away from the

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wafer surface when using a thermal chuck. As a result, during PEALD deposition, the precursor

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molecule was transferred one-dimensionally and interacted with the wafer surface. Figures 4b

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reveals, however, that when the device was under JH, the temperature decreased dramatically and

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non-linearly from 474 K to near 300 K when 5 µm away from the surface of the hot spot of the

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device, resulting in much higher mass transfer through convection around the surface of the

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device. Moreover, unlike the case in the thermal chuck, the hot spot of the device experienced

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more than one-dimensional impingement of the ALD precursor onto the device surface, such that

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a much higher rate of reaction would be expected at the surface of the JH device. However, the

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GPC =8.04 Å/cycle for Pt and GPC= 19.21 Å/cycle for ZnO is too high for ALD process as

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compared with previous studies16,29. We suspect that the device JH temperature were higher than

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that estimated in Figure 1c. Therefore, time-lapse device resistance was investigated over a

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period of PEALD process (20~30 min) (Fig. 4c). The resistance of SNB device decreased

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gradually and reached to minima in 20 min of JH. The biased voltages to the change of device

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resistance after 20-min device JH were 20 V– -24.43%, 24 V– -30%, 28 V– -31.14%, and 32 V–


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-32.7% (inset Fig. 4c). We suspect the decrease of device resistance during JH period was

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resulted from the hole trapping in the Si3N4/SiO2 dielectric stack so that the conductance of

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device active channel increased. Figure 4d compared estimated device temperature before and

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after 20-min JH (device resistances via a thermal chuck under various temperatures.) As a result,

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thermal decomposition of precursors occurred during PEALD process. Selective deposition in

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the n- region was dominated by CVD instead of ALD. The surface temperature distribution of the

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SNB device was simulated based on the resistance obtained after JH through 3D COMSOL

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Multiphysics 4.2. The estimated device temperature was higher than 543 K for JH bias larger

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than 20 V. (see Fig. S6 in the Supporting Information). On the other hand, due to lack of

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technique for direct monitoring the SNB device surface temperature, SNB device coated with 40-

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nm PMMA was biased at various voltages for 20 minutes. The surface profile was then

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characterized by AFM (see Fig. S7). PMMA melting was observed at 15V indicating the device

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surface temperature at n- region was at least 433 K. At 20 V, ablation of PMMA at n- region was

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observed suggesting that the surface temperature at n- region was higher than 673K30. Therefore,

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the selective deposition in the n- region is mainly dominated by CVD.

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In summary, we have used PEALD system and localized JH to selectively deposit ZnO and

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Pt in the n– regions of correspondent SNB devices in the same chip. The n– region of the SNB

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device possessed the longer semiconductor Debye length; therefore, it exhibited higher capability

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of sensing changes in surface potential. AFM, SEM, and cross-sectional TEM allowed us to

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investigate the average thickness and average coverage, the surface morphology, and the

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composition after the selective deposition of Pt and ZnO through device JH in a PEALD system.

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The high growth rates of both Pt and ZnO during device JH and PELAD were analyzed through

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COMSOLE simulations. Because of a higher temperature gradient around the JH device, the


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SNB devices experienced high precursor mass transfer and a high degree of precursor

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impingement, such that a much higher deposition rate was observed than that during thermal

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chuck deposition. Moreover, we also found that the resistance of SNB device decreased

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gradually and reached to minima in 20 min of JH. Surface temperature of SNB device during

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PEALD is expected higher than 543K for JH bias larger than 20 V. As a result, thermal

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decomposition of precursors occurred during PEALD process and selective deposition in the n-

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region was mainly dominated by CVD. However, selective deposition of multiple sensing

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materials on an individual device in the same chip has still been achieved.

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AUTHOR INFORMATION

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Corresponding Author

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*E-mail: [email protected]

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Notes

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The authors declare no competing financial interest.

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Supporting Information

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Details on COMSOL simulations, PECVD process, surface analysis via AFM, SEM and TEM;

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SNB device coated with PMMA under JH at various biases; SEM-EDX elemental analysis for

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selective Pt and ZnO depositon in n- regions of SNBs.

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ACKNOWLEDGMENT

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The authors would like to thank MOE-ATU program and National Science Council (NSC 101-

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2120-M-009-011-CC1) in Taiwan for financial support.


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Figure Captions

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Figure 1. (a) Schematic process flow for selective deposition through localized device JH and

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PEALD. (b) Device resistance at various temperatures, via thermal chuck at a bias of 0.1 V. (c)

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Estimated JH temperature of an SNB device under various JH biases, estimated from the

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resistance measured under thermal chuck, as displayed in (b). Five individual devices were

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measured (N=5).

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Figure 2. Surface morphologies after selective deposition of Pt and ZnO through localized JH

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under 20 V and PEALD for various deposition cycles. (a–c) AFM images (five parallel SNBs)

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and SEM images (single SNB) revealing the selective deposition of both Pt and ZnO in the n–

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regions after (a) 10, (b) 20, and (c) 30 PEALD cycles. (d) Average thicknesses (top-to-bottom)

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and (e) average coverages (X to X´ direction) of Pt and ZnO after various numbers of PEALD

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cycles. Three individual devices were measured (N=3).

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Figure 3. Surface morphologies after selective deposition of Pt and ZnO through 10-cycle

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PEALD and device-localized JH under various bias voltages. AFM images (five parallel SNBs)

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and SEM images (a single SNB) revealing the selective deposition of both Pt and ZnO under bias

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voltages of (a) 24, (b) 28, and (c) 32 V in the n– regions. (d) Average thicknesses (peak-to-

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bottom of AFM scans) of Pt and ZnO; the ZnO film was thinner in the middle of the n– regions

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and thicker close to the n–/n+ junctions when the JH bias was 32 V. (e) Average coverages (along


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the X to X´ direction) of Pt and ZnO after applying various localized JH biases. Three individual

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devices were measured (N=3).

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Figure 4. Plots of the average thickness with respect to the number of PEALD cycles. (a)

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Average thicknesses of Pt and ZnO deposited on SNB devices and a 6-inch wafer (Si/SiO2/Si3N4)

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using the thermal chuck; results of 1000 cycles of Pt and ZnO deposition using the thermal chuck.

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(see Fig. S5a) (b) COMSOL simulations of temperature distribution from the chip surface to the

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chamber boundary for both the device-localized JH and thermal chuck; 1-D temperature

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distribution from the device surface to a distance of 5 µm from the surface (see Fig. S5b,c). (c)

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Time-lapse resistance observation under JH biases. (Inset shows the resistance change of each

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SNB device after 20-min JH.) (d) Estimated device temperature before and after 20-min JH

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based on Figure 1b measurement. Temperature marked in open square( □ ) was obtained by

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extrapolation.

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Figure 1. (a) Schematic process flow for selective deposition through localized device JH and PEALD. (b) Device resistance at various temperatures, via thermal chuck at a bias of 0.1 V. (c) Estimated JH temperature of an SNB device under various JH biases, estimated from the resistance measured under thermal chuck, as displayed in (b). Five individual devices were measured (N=5). 254x190mm (300 x 300 DPI)



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Figure 2. Surface morphologies after selective deposition of Pt and ZnO through localized JH under 20 V and PEALD for various deposition cycles. (a–c) AFM images (five parallel SNBs) and SEM images (single SNB) revealing the selective deposition of both Pt and ZnO in the n– regions after (a) 10, (b) 20, and (c) 30 PEALD cycles. (d) Average thicknesses (top-to-bottom) and (e) average coverages (X to X´ direction) of Pt and ZnO after various numbers of PEALD cycles. Three individual devices were measured (N=3). 254x190mm (300 x 300 DPI)


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Figure 3. Surface morphologies after selective deposition of Pt and ZnO through 10-cycle PEALD and devicelocalized JH under various bias voltages. AFM images (five parallel SNBs) and SEM images (a single SNB) revealing the selective deposition of both Pt and ZnO under bias voltages of (a) 24, (b) 28, and (c) 32 V in the n– regions. (d) Average thicknesses (peak-to-bottom of AFM scans) of Pt and ZnO; the ZnO film was thinner in the middle of the n– regions and thicker close to the n–/n+ junctions when the JH bias was 32 V. (e) Average coverages (along the X to X´ direction) of Pt and ZnO after applying various localized JH biases. Three individual devices were measured (N=3). 254x190mm (300 x 300 DPI)



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Figure 4. Plots of the average thickness with respect to the number of PEALD cycles. (a) Average thicknesses of Pt and ZnO deposited on SNB devices and a 6-inch wafer (Si/SiO2/Si3N4) using the thermal chuck; results of 1000 cycles of Pt and ZnO deposition using the thermal chuck. (see Fig. S5a) (b) COMSOL simulations of temperature distribution from the chip surface to the chamber boundary for both the devicelocalized JH and thermal chuck; 1-D temperature distribution from the device surface to a distance of 5 µm from the surface (see Fig. S5b,c). (c) Time-lapse resistance observation under JH biases. (Inset shows the resistance change of each SNB device after 20-min JH.) (d) Estimated device temperature before and after 20-min JH based on Figure 1b measurement. Temperature marked in open square(□) was obtained by extrapolation. 254x190mm (300 x 300 DPI)


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Selective Deposition of Multiple Sensing Materials on Si Nanobelt

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