LETTER pubs.acs.org/NanoLett
Silicon Nanotube Field Effect Transistor with CoreShell Gate Stacks for Enhanced High-Performance Operation and Area Scaling Benefits Hossain M. Fahad, Casey E. Smith, Jhonathan P. Rojas, and Muhammad M. Hussain* Integrated Nanotechnology Lab, Electrical Engineering, Division of Physical Science and Engineering, King Abdullah University of Science and Technology, Thuwal 23955-6900, Saudi Arabia
bS Supporting Information ABSTRACT: We introduce the concept of a silicon nanotube field effect transistor whose unique coreshell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The coreshell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. KEYWORDS: Silicon, field effect transistor (FET), nanotube, nanowire, drive current, high performance, volume inversion, short channel effect
A
dvancement in today’s modern world is catalyzed by the growth of information technology that inherently depends on the sustained progress of transistor technology. Yesterday’s microelectronics technology has become today’s nanoelectronics industry by scaling the device dimension to meet consumers’ need for high-performance devices. At the same time, rise in leakage power consumption and short channel effects restrict attaining the “sweet spot” where a charge transport device can provide high performance at lower power consumption especially when it is off. Some fundamental driving relationships that are extracted from the classical metal oxide semiconductor field effect transistor (MOSFET) can help us understand the situation Id ≈ μCox
W ðVg Vt Þ2 L and
and
τ¼
Cg Vdd Id
Pof f ¼ Wtotal Vdd Iof f
where Id denotes drive current, μ symbolizes channel material mobility, Cox represents gate dielectric capacitance, which is directly dependent on the permittivity or dielectric constant (k) of the gate dielectric and inversely proportionate to its thickness (tox), and Vg and Vt represent gate voltage and threshold voltage, respectively. Empirically, an inverter delay (τ) is commonly used as a means of assessing transistor speed where Cg represents gate capacitance and Vdd is the drive-in voltage.1 Finally, the stand-by power (Poff) of a CMOS chip due to sourceto-drain subthreshold leakage is measured by the product of total turned-off device width (Wtotal) with Vdd across the source and drain, and Ioff is the average off-current per device width at 100 °C r 2011 American Chemical Society
(worst-case temperature).2 All these relationships indicate that we need to increase the drive current Id but not the Vdd, nor the width of the device (this arrangement is counterproductive to drive current enhancement but beneficial for scaling). In the recent past, Cox has been significantly increased by introducing high-k gate dielectrics into planar and nonplanar transistors to increase the drive current as well as to reduce leakage power by reducing probability of unintentional gate tunneling.3 Mobility (μ) of silicon is limited and as we move toward shorter channel devices, it is compromised because of higher impurity concentration and carrier scattering. At the same time, if appropriately designed, we can take advantage of quantum ballistic transport by leveraging velocity saturation of a short channel device. Finally, fundamental nonscaling effects are caused by the fact that neither the thermal voltage (kT/q), nor the silicon band gap changes with scaling. The former results in nonscaling of the subthreshold swing parameter (indicator of how quickly a transistor can change its state from off to on or from on to off) and the later results in nonscalability of built-in junction potential, depletion layer width, and short channel effects. To address these issues, decade long advancement in semiconductor nanowire-based FET research has produced interesting results.4 Nonetheless, bulk semiconductor-based nanoelectronics technology is too well established and matured to adopt a scientific niche but technologically unproven nanowirebased device. Although a nanowire device presents ultrascaled Received: July 26, 2011 Revised: September 9, 2011 Published: September 16, 2011 4393
dx.doi.org/10.1021/nl202563s | Nano Lett. 2011, 11, 4393–4399
Nano Letters
LETTER
Figure 1. A pictorial depiction of the conceptualized silicon nanotube FET where (a) shows a 3D cross section cut through the middle (from top view) of the nanotube FET; (b) shows a cross-section (for decoration purpose a transmission electron microscopy (TEM) image of a real stack of Si3N4PolySi SiO2 is used); and (c) shows a top view when the silicon nanotube FET is cut through the channel area.
Figure 2. Carrier distribution profile of (a) Si planar metal oxide semiconductor field effect transistor (MOSFET); (b) Si gate-all-around nanowire FET; and (c) full volume inversion in Si nanotube FET.
real estate consumption per device, per device current is low and also contact formation technology hinders its true potential for high density device integration. Moreover, maximum integration density is limited by the power density while maximum circuit speed is limited by the parametric variability. Because of the field dependence of the mobility the device speed will not increase linearly with scaling and there is adverse impact on device reliability due to high electric field stress. Thus, the challenges that the bulk semiconductor industry is approaching with fundamental device scaling and the issues that unpredictable bottom-up nanowire FET devices are facing can be addressed if a device structure is built that takes advantage of the unique property control by bottom-up processes and nearly perfect alignment controlled, well organized, ultrahigh-density circuit compatible top-down processes based on the state-of-the-art complementary metal oxide semiconductor (CMOS) flow. Hence,
in this letter we introduce the concept of silicon nanotube field effect transistor (SiNT) whose (i) intrinsic undoped channel will be grown using chemical vapor deposition based epitaxy (bottom-up) for better control of source/channel/drain properties; (ii) unlike widely used Schottky barrier nanowire devices, formation of ultrasteep source/drain junctions in SiNT will be through in situ heavy doping during bottom-up epitaxial growth; (iii) aggressively scaled short channel (Lg) by deposition thickness controlled gate length definition without any preor postetch processing; and (iv) flexible choice of channel materials and its orientation. At the same time, by introducing coreshell gate stacks that mimic the all-around or surround gate nanowire devices by having an outer (shell) gate, we also incorporate an inner (core) gate inside the nanowire structure making it a hollowed cylindrical shaped nanotube structure shown in Figure 1ac. 4394
dx.doi.org/10.1021/nl202563s |Nano Lett. 2011, 11, 4393–4399
Nano Letters
Figure 3. (a) Comparison of transfer (IdVg) characteristics of Si nanotube FET, Si gate-all-around nanowire FET, and Si planar MOSFET; (b) carrier concentration vs silicon nanotube channel thickness plot shows volume inversion trend; and (c) comparison of short channel characteristics of Si nanotube FET, Si gate-all-around nanowire FET, and Si planar MOSFET (effective widths are same as Figure 3a).
Unlike conventional planar transistors, the SiNT encounters new device physics mostly due to the tight control of carriers by the coreshell gate stacks. In the classical situation, biasing the gate and drain terminals of the transistor induces a channel of charge carriers causing a planar 2D current flow. These charges have distinctive distribution that resembles a Gaussian profile shown in Figure 2a with a peak near the drain edge and tailing off into the bulk substrate. Most of the current flow in the channel is due to the minority carriers localized near the interface while the minority carriers in the bulk (quasi-neutral region) do not
LETTER
contribute to output current flow. Now, if we consider the SiNT with the inner core gate removed and a solid rather than hollow interior, it effectively resembles a gate-all-around nanowire (NW) FET shown in Figure 2b. On biasing this device, similar 2D carrier profiles are generated along the interface of the nanowire and the all-around-gate. From the top-view perspective, the shell (outer) ring gate can be approximated as four effective gates that generate four distinct carrier profiles. These carrier profiles interact with each other causing them to shift away from the Si/SiO2 interface and move toward the center of the nanowire body. This interaction translates into a surge of available carrier density of states (DOS) toward the nanowire center. Introducing an inner (shell) gate at the core of the nanowire shown in Figure 2c increases the effect of carrier profile interactions to the point that now the density of states (and consequently the carrier concentration) resembles a parabola peaking at the center of the silicon nanotube. This phenomenon is the same as full volume inversion on account of charge carriers being distributed throughout the nanotube thickness.5 In the SiNT, because of volume inversion, the minority carriers in the lower energy states are able to participate in current conduction along with the surface charges. As the nanotube thickness is reduced, the inversion layer charge centroid shifts away from the interfaces and peaks somewhere in the center of the nanotube. In addition, it is anticipated that full volume inversion enables increased carrier mobility due to reduced scattering associated with oxide/interface trapped charges and surface roughness.6 All of these lead to an enhanced output drive current (Id), reduced leakage and better immunity to short channel effects. Using a commercially available device simulator (Synopsis Sentaurus Device), we carried out performance assessment studies of a 3D n-type Si nanotube FET depicted in Figure 1. Quantum carrier transport models and quantization effects for ultrashort channel devices are used for the simulations. In order to account for high lateral E-field effects in the ultrashort channel such as velocity overshoot and impact ionization rates, we replaced the conventional drift-diffusion mechanics with the energy balance equation for carriers (default hydrodynamic transport model) and solved together with the Poisson continuity equation. Besides this, we dealt quantization effects arising due to carrier confinement effects by the density-gradient quantization model. Using conventional drift-diffusion equations in the simulations leads to an underestimation of the output drive current. More information regarding the simulation details and models used are provided in the Supporting Information (Simulation Models: Carrier Transport Model). A normalized transfer characteristics (IdVg) plot for an n-type Si(100) nanotube FET with source and drain regions having a constant arsenic (As) doping level of 1020 cm3 everywhere and undoped channel area (this nin profile is used here to model extremely steep doping profiles at the sourcechannel and drainchannel junctions achievable through in situ doping process) is shown in Figure 3a where it is compared to a planar transistor and a gateall-around NWFET. Output current normalization in the nanotube is done by considering the average of the core gate and shell gate circumferences. From a 20 nm gate length (Lg) and 10 nm thick (channel thickness) SiNT, a drive current of 2.56 mA/μm can be achieved. We used a gate stack consisting of a midgap metal with 4.53 eV work function, a 1.8 nm Hafnium Oxide (HfO2) high-k gate dielectric and a 0.5 nm interfacial silicon oxide (SiO2) layer. Compared to this, a classical planar silicon MOSFET of similar Lg achieves approximately 1.8 mA/μm of 4395
dx.doi.org/10.1021/nl202563s |Nano Lett. 2011, 11, 4393–4399
Nano Letters
LETTER
Figure 4. (a) Band diagram of an n-type Si nanotube FET at symmetric gate biasing (Vgs) of 1.0 V and (Vds) drain biasing of 1.0 V and Si planar MOSFET for gate length, Lg = 30 nm and effective width of 345.5 nm and 1 μm, respectively. The figure also shows the near ballisticity a nanotube FET can achieve through band-engineering. (b) Effect of nanotube shell (channel) thickness on the band gap.
Figure 5. Cross section and top view layout with contacts are shown in (a,b) for Si gate-all-around nanowire FET and Si nanotube FET, respectively shows area scaling benefit of Si nanotube FET. The minimum gate-to-gate pitch, λ = 7080 nm; minimum contact gate pitch, ζ = 5 nm; and minimum contact width, W = 20 nm. We have also assumed that source contact will be formed from substrate backside as we have used isolation.
drive current. A Si gate-all-around NWFET of similar gate length and diameter of 10 nm achieves 0.542 mA/μm. At the same time, it is to be noted that with increasing channel length Lg (metal gate thickness) we expect the off state current Ioff to drop down and drive current Ion to reduce as well. This is a well-known characteristic for field effect transistors when moving from the short-channel regime to the long-channel regime. Figure 3b shows the carrier distribution profile as a function of the Si nanotube channel thickness. Because of the presence of multiple gates, all the inversion layers interact with each other resulting in the volume inversion phenomenon discussed earlier. In addition to this analysis, we have shown that with increased nanotube channel thickness although drive current (Ion) increases, off state current (Ioff) increases too (Supporting Information Figure S2a). This happens because the volume inversion
phenomenon disappears beyond the channel thickness of 15 nm and there is very little or no tail-end carrier profile interaction. Basically for a multiple gate device, in order to maintain sufficient gate control, it is imperative to have a nanotube channel thickness of less than or equal to half of gate length (Lg/2). We also analyzed the transistor’s short channel effects by the subthreshold swing (SS) and the drain-induced barrier lowering (DIBL). The SS metric describes the transistor switching speed. For ideal planar transistors, this value is limited to 60 mV/dec The DIBL metric is a measure of how threshold voltage scales with gate length. In Figure 3c, it is clear that the SiNT has very low SS and DIBL when compared to classical transistors and is comparable to gate-all-around NWFETs. With further analysis, we have also shown that with reduced channel thickness short channel characteristics improves for SiNT that is due to its 4396
dx.doi.org/10.1021/nl202563s |Nano Lett. 2011, 11, 4393–4399
Nano Letters
LETTER
Table 1. Comparison of Various Planar and Nonplanar Field Effect Transistors (FETs) (includes refs 8 and 1215)
*
The inner gate diameter of the silicon nanotube FET is 100 nm. The current normalizations that were carried out were done by taking the average of the inner and outer circumference. ** A detail comparison between silicon nanotube FET and refs 12 and 15 are shown in Tables S1 and S2.
unique coreshell gate structures (Supporting Information Figure S2b). Finally the channel length variation impact on device threshold voltage (Vt) characteristics shows very negligible Vt roll-off for short channel (down to Lg = 10 nm) devices, another sign of excellent short channel characteristics confinement (Supporting Information Figure S2c). The high drive current and well managed short channel effects in the Si nanotube FETs can be accounted for by the ballistic transport theory as well as their unique structure. According to this theory, the saturated drain current (Id,sat) for such devices is given by Id, sat ≈ Cinv ðVgs Vt ÞWvt Here we can see that the drive current depends on two terms: the inversion charge density [Qi = Cinv.(Vgs Vt)] and the thermal injection velocity, vt. However, in reality such short channel devices will never achieve full ballisticity as a small
portion of carriers will always be scattered by interfaces and lattice collisions. At the same time, the mobility term cannot be solely used to describe the drive current. A certain percentage of charge carriers will undergo scattering events (due to interfaces and spatial electric-field variation) while others will be injected from the source with a high velocity (approaching the ballistic limit), sweeping quickly to be collected by the drain. To put a realistic perspective on carrier transport in ultrashort channel devices it is necessary to include both injection and scattering effects. As a result, a more appropriate output drive current equation for the Si nanotube FETs can be approximated by Id, sat ≈ βCinv ðVgs Vt ÞWvt W þ ð1 βÞμn Cox ðVgs Vt Þ2 , ð0 < β < 1Þ 2L Here, β is the coefficient of ballisticity. The goal then for an ultra short channel device is to achieve a high β value. 4397
dx.doi.org/10.1021/nl202563s |Nano Lett. 2011, 11, 4393–4399
Nano Letters As mentioned earlier, the Si nanotube FET has a constant doping profile with an abrupt roll-off at the source/channel and drain/ channel interfaces. In terms of a band diagram (shown in Figure 4a), this translates to a large number of carriers at the point of highest barrier near the source. Ideally, in the band diagram of an n-type ballistic device, the barrier to electrons is largely flat under high gate bias. Because of this, carriers roll-off (injected) from the source to drain with very large velocities. Furthermore, abrupt doping junctions create steeper slopes enabling higher carrier injection velocities. On comparing the band diagram of the SiNT with a planar transistor, it is evident that energy barrier to electrons is very close to being flat (a very tiny bump) under high gate bias enabling near-ballistic charge transport. Compared to this, the energy barrier in a classical transistor is much larger. It is to be noted that in the band diagram within the undoped nanotube channel, the band gap is 1.101816 eV, whereas within the source and drain the band gap reduces to around 0.98 eV. Because the donor concentration (As) of 1020 cm3 is very high, the band gap narrowing will be larger from the conduction band side as opposed to the valence band side (as hole density is not large). In addition to this, we have analyzed the effect of nanotube shell thickness reduction on the band gap (Figure 4b). It can be seen that as the thickness reduces, the barrier at the sourcechannel junction reduces with the band edges tending to slope downward. This is visibly noticeable in the 5 nm thick SiNT device. The Supporting Information contain further information regarding the Band gap Model used for the simulations. Classical short channel transistors require channel doping to fix the desired threshold voltage. As this is process dependent, dopant positions and distribution in the channel can vary between devices.7 Consequently, this causes threshold voltage variation and being short channel transistors; this can translate to both negative and positive shifts affecting the on and off currents as well as the subthreshold slope. SiNTs can be immune to such random dopant fluctuations (RDF) because of its formation through controlled bottom-up epitaxial process. Performance in gate-all-around NWFETs is mainly attributed to excellent carrier confinement properties leading to higher degrees of energy quantization. The non-normalized output drive currents from most single NWFETs are several orders of magnitude lower than current planar transistors. To address this, several groups7,8 have incorporated single nanowires into arrays with a gate-all-around topology to improve the cumulative drive current at the cost of area penalty and integration complexity. Therefore, we characterize a single SiNT having a nanotube thickness of 10 nm with an inner core gate diameter of 100 nm from area scaling perspective. The effective area through which the output current flows (due to volume inversion) is approximately 3455.749 nm2. A gate-all-around NWFET of 10 nm thickness has an effective area of 78.54 nm2 shown in Figure 5. Comparing these effective areas of the SiNT and the gate-allaround NWFET suggests that a single SiNT is equivalent to 44 nanowires. The non-normalized output drive currents from the SiNT and the gate-all-around NWFET with the above dimensions are approximately 0.9653 mA and 17.07 μA, respectively. The current ratios indicate that a single SiNT is equivalent to stacking 56 Si gate-all-around NWFETs together. Furthermore, unlike most NWFETs where a metal (preferably noble metal) catalyst seed of gold or platinum is required, the SiNTs can be grown via selective epitaxy9 directly on the silicon substrate. This avoids electrical shorts and charge trapping common in most
LETTER
bottom-up NWFETs due to contamination by residual seed particles.10,11 Finally, we present a comparative study of various Si based FETs and SiNT to show the potential of SiNT (Table 1). To summarize, this paper introduces a novel concept of Si nanotube FET (SiNT). Through rigorous quantum mechanical simulation we show that its unique coreshell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive currentinduced performance per device with efficient real estate consumption.
’ ASSOCIATED CONTENT
bS
Supporting Information. Additional information, figures, and tables. This material is available free of charge via the Internet at http://pubs.acs.org.
’ AUTHOR INFORMATION Corresponding Author
*E-mail:
[email protected]. Phone: +966544-700072.
’ ACKNOWLEDGMENT We deeply appreciate the valuable technical discussion with Professor Frank Register of the University of Texas at Austin, useful logistic support by Kelly Rader, and generous baseline research funding from King Abdullah University of Science and Technology (KAUST). ’ REFERENCES (1) Taur, Y. CMOS design near the limit of scaling. IBM J. Res. Dev. 2002, 46, 213. (2) Nowak, E. J. Maintaining the benefits of CMOS scaling when scaling bogs down. IBM J. Res. Dev. 2002, 46, 169. (3) Hussain, M. M.; Smith, C. E.; Harris, R.; Young, C.; Sassman, B.; Tseng, H.-H.; Jammy, R. Gate first integration of high-k/metal gate CMOS FinFET with multi-VTh engineering. IEEE Trans. Electron Devices 2010, 57, 626. (4) Lu, W.; Lieber, C. M. Nanoelectronics from the bottom up. Nat. Mater. 2007, 6, 841. (5) Balestra, F.; Cristoloveanu, S.; Benachir, M.; Brini, J.; Elewa, T. Double-Gate Silicon-on-Insulator Transistor with Volume Inversion: A New Device with Greatly Enhanced Performance. IEEE Electron Device Lett. 1987, 8, 410. (6) Gamiz, F.; Fischetti, M. V. Monte Carlo simulation of doublegate silicon-on-insulator inversion layers: The role of volume inversion. J. Appl. Phys. 2001, 89, 5478. (7) Yan, H.; Choe, H S.; Nam, S.; Hu, Y.; Das, S.; Klemic, J. F.; Ellenbogen, J. C.; Lieber, C. M. Programmable nanowire circuits for nanoprocessors. Nature 2011, 470, 240. (8) Bangsaruntip, S.; Majumdar, A.; Cohen, G. M.; Engelmann, S. U.; Zhang, Y.; Guillorn, M.; Gignac, L. M.; Mittal, S.; Graham, W. S.; Joseph, E. A.; Klaus, D. P.; Chang, J.; Cartier, E. A.; Sleight, J. W. Gate-allaround silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm. Symp. VLSI Technol., Dig. Tech. Pap. 2010, 21. (9) Ribot, P.; Dutartre, D. Low-temperature selective epitaxy of silicon with chlorinated chemistry by RTCVD. Mater. Sci. Eng., B. 2002, 89, 306. 4398
dx.doi.org/10.1021/nl202563s |Nano Lett. 2011, 11, 4393–4399
Nano Letters
LETTER
(10) Xiang, J.; Lu, W.; Hu, Y.; Wu, Y.; Yan, H.; Lieber, C. M. Ge/Si nanowire heterostructures as high-performance field-effect transistors. Nature 2006, 441, 489. (11) Wang, Y.; Schmidt, V.; Senz, S.; G€osele, U. Epitaxial growth of silicon nanowires using an aluminium catalyst. Nat. Nanotechnol. 2006, 1, 186. (12) Singh, N.; Lim, F. Y.; Fang, W. W.; Rustagi, S. C.; Bera, L. K.; Agarwal, A.; Tung, C. H.; Hoe, K. M.; Omampuliyur, S. R.; Tripathi, D.; Adeyeye, A. O.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. L. UltraNarrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance. IEEE Int. Electron Devices Meet., Tech. Dig. 2006, 1. (13) Packan, P.; Akbar, S.; Armstrong, M.; Bergstrom, D.; Brazier, M.; Deshpande, H.; Dev, K.; Ding, G.; Ghani, T.; Golonzka, O.; Han, W.; He, J.; Heussner, R.; James, R.; Jopling, J.; Kenyon, C.; Lee, S.-H.; Liu, M.; Lodha, S.; Mattis, B.; Murthy, A.; Neiberg, L.; Neirynck, J.; Pae, S.; Parker, C.; Pipes, L.; Sebastian, J.; Seiple, J.; Sell, B.; Sharma, A.; Sivakumar, S.; Song, B.; St. Amour, A.; Tone, K.; Troeger, T.; Weber, C.; Zhang, K.; Luo, Y.; Natarajan, S. High Performance 32nm Logic Technology Featuring 2nd Generation High-K + Metal Gate Transistors. IEEE Int. Electron Devices Meet., Tech. Dig. 2009, 28.4.1. (14) Kavalieros, J.; Doyle, B.; Datta, S.; Dewey, G.; Doczy, M.; Jin, B.; Lionberger, D.; Metz, M.; Rachmady, W.; Radosavljevic, M.; Shah, U.; Zelick, N.; Chau, R. Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering. Symp. VLSI Technol., Dig. Tech. Pap. 2006, 50. (15) Hashemi, P.; Teherani, J.; Hoyt, J. Investigation of Hole Mobility in Gate-All-Around Si Nanowire p-MOSFETs with High-k/ Metal-Gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape. IEEE Int. Electron Devices Meet., Tech. Dig. 2010, 34, 5.1.
4399
dx.doi.org/10.1021/nl202563s |Nano Lett. 2011, 11, 4393–4399
