Small Hysteresis Nanocarbon-Based Integrated Circuits on Flexible

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LETTER pubs.acs.org/NanoLett

Small Hysteresis Nanocarbon-Based Integrated Circuits on Flexible and Transparent Plastic Substrate Woo Jong Yu,† Si Young Lee,† Sang Hoon Chae,† David Perello,‡ Gang Hee Han,† Minhee Yun,‡ and Young Hee Lee*,† †

Sungkyunkwan Advanced Institute of Nanotechnology, Department of Energy Science, BK21 Physics Division, Center for Nanotubes and Nanostructured Composites, Sungkyunkwan University, Suwon 440-746, South Korea ‡ Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, Pennsylvania 15261, United States

bS Supporting Information ABSTRACT: We report small hysteresis integrated circuits by introducing monolayer graphene for the electrodes and a singlewalled carbon nanotube network for the channel. Small hysteresis of the device originates from a defect-free graphene surface, where hysteresis was modulated by oxidation. This uniquely combined nanocarbon material device with transparent and flexible properties shows remarkable device performance; subthreshold voltage of 220 mV decade-1, operation voltage of less than 5 V, on/off ratio of approximately 104, mobility of 81 cm2 V-1 s-1, transparency of 83.8% including substrate, no significant transconductance changes in 1000 times of bending test, and only 36% resistance decrease at a tensile strain of 50%. Furthermore, because of the nearly Ohmic contact nature between the graphene and carbon nanotubes, this device demonstrated a contact resistance 100 times lower and a mobility 20 times higher, when compared to an Au electrode. KEYWORDS: Carbon nanotube, graphene, flexible, transistor, logic, hysteresis

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lexibility and transparency are the key components for next generation displays and electronic devices. Various flexible and transparent devices have been developed for next generation displays and electronic devices using carbon nanotubes,1-7 inorganic materials,8-10 and organic materials.11-13 Among them, the carbon nanotube (CNT) has been regarded as a strong candidate, due to its high mobility, high on/off ratio, excellent mechanical properties, and transparency.1-7 Recently, the development of medium-scale integrated circuits, using single-walled CNTs (SWCNTs) with an Au electrode, showed the application possibility of a CNT transistor to flexible electronic devices.4 In addition, a transparent flexible transistor was fabricated using the SWCNT network channel and indium tin oxide electrode (ITO).5,6 However, the electrodes used within these devices were vulnerable against strain.14,15 In particular, indium tin oxide is transparent and highly conductive but allows a small strain of less than 1%. Recent development of a large area monolayer graphene with high transmittance (i.e., approximately 97.5%) and a low sheet resistance (i.e., approximately 270 Ω 0-1) provides an advantage of using graphene for electronics.16-19 The use of graphene as an electrode material is promising due to its high transmittance, high electrical conductivity, and superb mechanical properties. Recently, a flexible and transparent transistor using graphene electrode and carbon nanotube network channel was demonstrated.28 However, the device performance was poor compared to the existing flexible transparent devices.2,5,6 r 2011 American Chemical Society

In this paper, we demonstrated flexible and transparent transistors and logic gates using a monolayer graphene electrode and CNT network channel. This device showed no hysteresis dependent on the gate voltage sweeping range, which was attributed to the defect-free graphene surface. Because of the monolayer graphene, only 3.6% transmittance was decreased compared with poly(ethylene terephthalate) (PET) substrate. No appreciable change was observed in the transconductance in 1000 times of bending test and only 36% resistance decrease was revealed at 50% tensile strain. An additional advantage of using graphene electrodes was the significant reduction of the contact resistance. Figure 1a shows a thin-film transistor (TFT) using graphene electrodes, with a source, drain, and gate, and an SWCNT network channel on a flexible transparent PET substrate. A graphene monolayer was synthesized on copper using the chemical vapor deposition (CVD) method (Figure S1a,b, Supporting Information).18,19 The grown graphene showed a small D-band and a high G0 -band intensity within the Raman spectra, as shown in Figure S1c (Supporting Information). The sheet resistance was approximately 270 Ω 0-1 and the transmittance was 97% at 550 nm, which was reduced by 3% by adding an additional layer, indicating high-quality monolayer graphene. The monolayer graphene was transferred using poly(methyl methacrylate) (PMMA) onto the PET substrate and then Received: December 23, 2010 Published: February 15, 2011 1344

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Figure 1. (a) The fabrication schematics of a graphene electrode and a SWCNT network channel on the PET film. (b) Transparent graphene-CNT integrated circuit array (16  9). (c) Optical image of a single graphene-CNT transistor with five channels, where the dark square indicates the oxide layer. (d) Magnified SEM image of channel area with the inset of the SWCNT network channel. Different layers are indicated by color.

patterned to the electrode via O2 plasma etching. A 20 nm Al2O3 gate dielectric layer was deposited using an e-beam evaporator followed by a 30 nm atomic layer deposition. After deposition, the gate oxide layer was patterned via HF etching. The SWCNT network used for the channel was grown via the CVD method, as shown in Figure S2 (Supporting Information). The SWCNT network showed good quality with a small D-band intensity and radial breathing mode in Raman spectra. The SWCNT network was transferred via PMMA to the graphene electrode-patterned PET substrate and then patterned within the channel via O2 plasma etching. No significant morphological change in the SWCNT network was observed after transfer, as shown in Figure S2e,f (Supporting Information). Fabrication details were further described in the Supporting Information. The completed graphene-CNT flexible transparent integrated circuit array is shown in Figure 1b. The opaque area of the sample’s outer side is the metal align marker (i.e., ITO 10 nm and Au 40 nm) and the transparent area of the sample consists of a 16  9 graphene-CNT integrated circuit array. Figure 1c shows the graphene-CNT TFT, which is composed of five channel strips. Monolayer graphene was used for source, drain, and bottom gate, which is covered by a 50 nm Al2O3 layer. The SWCNT network channel was magnified by scanning electron microscopy (SEM), as shown in Figure 1d. The three horizontal blue lines represent the source, gate, and drain graphene electrodes, and the SWCNT network channel with five vertical strips connects the source and drain electrodes.

One intriguing advantage of using graphene electrodes is the small hysteresis that is usually caused by the interface trap states parasitized between the gate electrode and dielectrics. Figure 2a shows the transfer characteristics of our nanocarbon device. An initially small hysteresis was shown at low gate voltage sweeping. This was attributed to the presence of ionic charges in the gate dielectrics.21 Interestingly, this small hysteresis was not altered with increasing gate voltage sweeping range. In order to confirm this, Au gate electrode instead of graphene electrode was constructed via the identical oxide formation process. A large hysteresis was observed within the same gate voltage sweep range, as shown in Figure 2b, which contrasted well with the graphene gate electrode. The large hysteresis with Au electrodes was also observed in numerous other experiments.30 In general, several sources of hysteresis exist, as shown in Figure 2c: (i) interface trapped charges due to structural defects or impurities, (ii) fixed oxide charges near the electrode and oxide interface, (iii) oxide trapped charges due to holes or electrons trapped in the oxide, (iv) mobile oxide charges caused by ionic impurities, (v) surface dipoles formed between CNT channel and gate oxide surface, and (vi) environmental adsorbates.21,22 Among them, the interface trap charge is the only difference between the graphene electrode and the Au electrode used within our experiment. An Au electrode has many interface trap sites due to its defects, dangling bonds, and vacancies on the Au surface.23,24 On the other hand, the graphene gate electrode is ideally flat and defect-free and therefore does not form such interfacial trap states. In order to confirm the 1345

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Figure 2. (a) Hysteresis of the graphene gate electrode independent of the gate voltage sweeping range and (b) large hysteresis of Au gate electrode. (c) The possible origin of hysteresis of (i) interface trapped charge, (ii) fixed oxide charge, (iii) oxide trapped charge, (iv) mobile oxide charge, (v) oxideCNT interface charge, and (vi) water-molecule-induced charge. (d) Large hysteresis induced by an ozone-treated graphene gate electrode.

relationship between defects on graphene and hysteresis, the graphene surface was treated via ozone prior to deposition of the oxide layer. Vacancies, CdO, C—O—C, and C—OH functional groups were formed on the graphene surface during the ozone treatment.25,26 For this case, a large hysteresis was initially observed, and the threshold voltage was significantly shifted within the scanned gate bias range, as shown in Figure 2d. The consequence of the use of graphene electrodes was the reduction of contact resistance by 100 times as indicated in panels a and b of Figure 2. The improvement of contact resistance comes from the nearly Ohmic contact due to the smaller work function difference between graphene and the CNTs. This allows the mobility to increase by 20 times higher than those of an Au electrode, as will be discussed later. Our graphene-CNT device array showed both a high transmittance of 83.8%, due to highly transparent monolayer graphene for electrodes, and a negligible spectral variance, as shown in Figure 3a. The graphene electrode area is slightly darker, but the overall uniformity of transmittance was still manifested in the inset of Figure 3a. These characteristics are superb in comparison to the competing nonflexible ITO and CNT electrode.2,5,6 Source-drain currents (IDS) were well-modulated with the gate voltage. The switching behavior was well manifested at an operating voltage as low as 5 V and a small subthreshold swing of 220 mV decade-1, shown in Figure 3b,c, which is much smaller than the ITO electrode with CNTs, as supported by Table S-1 (Supporting Information). Despite the simple fabrication process for random network CNT transistors, reaching a desired practical level of device performance has been challenging technologically. The

optimization of individual devices is necessary in order to advance, particularly for a high yield of circuit integration. The random network CNT channels were optimized as a function of CNT density and channel width. The SWCNT density was controlled by catalyst density. The channel length was fixed at 50 μm. Both the on-current and off-current increased as the CNT density and channel width were incremented, as shown in Figure 3d and Figure S3 (Supporting Information), due to the additional availability of current channels. Reasonable device performance, such as an on/off ratio of approximately 103 and a mobility3,20 of approximately 81 cm2 V-1 s-1 were achieved at a density of 7.5 SWCNTs μm-1. The on/off ratio and mobility were then optimized for the channel width at a fixed density of 7.5 SWCNTs μm-1, as shown in Figure 3e. The channels consisted of several lines, and the mobility was calculated using the whole channel width. As the channel width decreased from 20 to 3 μm, the mobility was reduced by only 60%, but the on/off ratio increased enormously by approximately 300 times. All the transistors with channel widths of 3 and 5 μm were plotted via an on- and off-current within Figure 3f. The channel width of 3 μm samples had lower on-current and off-current distributions than that of the 5 μm samples but yielded a higher on/off ratio distribution. Small, on-current distribution was observed, in contrast to large, off-current distribution. For a wide channel width, the number of channels increases and, thus, mobility is expected to increase, while the chance of having metallic channels increases, yielding a low on/off ratio. A large off-current distribution and a small on/off ratio can be improved by removing metallic channels via electrical breakdown, as shown in Figure S4 (Supporting Information). 1346

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Figure 3. (a) Transmittance of graphene (electrode)-network CNTs (channel) transistor with reverences of an ITO-CNT transistor and a CNTCNT transistor. Inset shows an optical image for transparency of a graphene/CNT transistor array on PET substrate. (b) IDS-VDS characteristics in terms of VGS and (c) transfer characteristic in terms of VDS. (d) On/off ratio and mobility in terms of channel width and SWCNT density per channel width at 50 μm channel length. Bar color indicates channel width: red (3 μm), blue (5 μm), and black (10 μm). Mobility is indicated by the corresponding colored symbols. SEM images of the SWCNT density are shown in the inset. The scale bar in the inset is 300 nm. (e) On/off ratio and mobility as a function of channel width at a density of 7.5 SWCNTs μm-1 and 50 μm channel length. Each channel is separated by 10 μm, which is repeated within 50 μm. The scale bar in the inset is 20 μm. (f) On-current, off-current, and on/off ratio plot for a channel width of 3 μm (green) and 5 μm (red).

We fabricated a 9  16 logic circuit array using graphene/ SWCNT transistors, shown in Figure 4a,b, as follows: 48 inverters, 48 NOR gates, and 48 NAND gates. A yield of approximately 80% was obtained for logic circuits, although the yield was higher (i.e., approximately 87% in transistors). The failure of the devices was attributed to the leakage of the gate dielectric on polymer substrate, in good contrast with SiO2 substrate.29 Figure 4b again demonstrates the high device transmittance. Panels c-f of Figure 4 show the PMOS inverter consisting of two p-type transistors. The inverter gain was approximately 1.4, and a supply voltage of 0-5 V was enough to provide the switching functions. The PMOS NOR, as shown in panels g-j in Figure 4, and a NAND logic gate, as shown in

panels k-n in Figure 4, were constructed via three transistors. One on-state and three off-states for the NOR gate and three on-states and one off-state for the NAND gate were clearly observed. We now demonstrate the bending properties of the grapheneCNT transistors. Four different curvature radii were used, shown in Figure 5a, as follows: infinite, 20, 15, and 8 mm from the left. The on-current, off-current, and transconductance showed negligible changes during bending and releasing, independent of the radius of curvature, as shown in Figure 5b and Figure S5 (Supporting Information). The durability of the bending replication was tested for an 8 mm radius, as shown in Figure 5c and Figure S5 (Supporting Information). The stability was retained within 1347

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Figure 4. (a) Schematic of NOR and NAND gates and (b) optical image of graphene-SWCNT TFT based PMOS logic circuit array. The logic circuit array consists of 48 inverters (c-f), 48 NOR gates (g-j), and 48 NAND gates (k-n). There are four panels for each logic circuit, as follows: (c, g, k) circuit diagrams; (d, h, i), schematics; (e, i, m) optical images,; and (f, j, n, electrical logic gate functions. The scale bar represents 200 μm in (e), (i), and (m).

an on/off ratio error of 5%. In order to measure further mechanical properties of nanocarbon materials, the graphene electrode-CNT channel which was originally loaded on polyimide (PI) film was transferred onto a poly(dimethylsiloxane) (PDMS) substrate, as shown in Figure 5d and Figure S6 (Supporting Information). The resistance changes were then measured during stretching. The nanocarbon materials showed a 36% resistance change at a 50% strain, as shown in Figure 5e. The resistance change was remarkably smaller in comparison to that of an ITO electrode (i.e., 2000% at 5% strain) and a few layers of graphene (i.e., 200% at 30%

strain).15,16 This superb mechanical performance results from the use of graphene and SWCNT network. The graphene layer could cause cracks upon stretching, but a robust contact can be formed between the SWCNT network and graphene electrode. This superb stretching performance of nanocarbon materials could be combined with stable flexible organic dielectric to demonstrate a stretchable device in the future. The device performance was compared with the previous works, as shown in Table S-1 (Supporting Information). In addition to excellent device performance, invisibility and mechanical properties are superb merits due to the use of the graphene electrode 1348

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Figure 5. (a) Optical images of a bending test setup of graphene-SWCNT TFT on a 0.3 mm thick PET substrate with bending radii of ¥, 20 mm, 15 mm, or 8 mm. The scale bars are 1 cm. (b) On-current, off-current, and transconductance variation during bending and releasing and (c) bending reliability measured at 8 mm bending radius up to 1000 times. (d) Optical image of graphene-SWCNT TFT on 1.5 μm thick PI film and 1 mm thick PDMS. (e) Resistance variation of graphene-SWCNT TFT against a strain, as compared with an ITO electrode. Left inset shows stretched images of graphene-SWCNT TFT at the 0% and 50% strain. Right inset shows resistance variation, as compared with a few layer graphene. The scale bars in the inset are 0.7 mm.

and the CNT channels. These results suggest that the graphene electrode and the SWCNT network channel are the most desirable for use with invisible electronics, and this concept is expected to be used with next-generation displays and electronics.

’ ASSOCIATED CONTENT

bS

Description of the methods used, figures showing schematics of graphene transfer process and SWCNT network transfer process, and table for comparison of transistor performance between this and previous works. This material is available free of charge via the Internet at http://pubs.acs.org. Supporting Information.

’ AUTHOR INFORMATION Corresponding Author

*E-mail: [email protected].

’ ACKNOWLEDGMENT This work was supported by the MOE through the STAR faculty project, the WCU (World Class University) program

through the KOSEF funded by the MEST (R31-2008-00010029-0), Samsung Mobile Display Co., Ltd., the KICOS through a grant provided by MOST in 2007 (No. 2007-00202), and KOSEF through CNNC at SKKU.

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