Solution Processed Organic Field-Effect Transistors with High

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Solution Processed Organic Field-Effect Transistors with High Performance and Stability on Paper Substrate Vivek Raghuwanshi, Deepak Bharti, Ajay Kumar Mahato, Ishan Varun, and Shree Prakash Tiwari ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b21404 • Publication Date (Web): 31 Jan 2019 Downloaded from http://pubs.acs.org on February 2, 2019

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ACS Applied Materials & Interfaces

Solution Processed Organic Field-Effect Transistors with High Performance and Stability on Paper Substrate Vivek Raghuwanshi, Deepak Bharti, Ajay Kumar Mahato, Ishan Varun, and Shree Prakash Tiwari* Department of Electrical Engineering, Indian Institute of Technology Jodhpur, Jodhpur, Rajasthan 342037, India

KEYWORDS: Organic field-effect transistors (OFETs), paper substrate, TIPSPentacene:polymer blend , low voltage, operational stability.

ABSTRACT High performance operationally stable organic field-effect transistors were successfully fabricated on PowerCoat™ HD 230 paper substrate with TIPS-Pentacene:Polystyrene (PS) blend as active layer and Poly(4-vinylphenol)(PVP)/HfO2 as hybrid gate dielectric. The fabricated devices exhibited excellent p-channel characteristics with maximum and avg. field effect mobility of 0.44 and 0.22(±0.11) cm2 V-1 s-1 respectively, avg. threshold voltage of 0.021(±0.63) V and current on-off ratio of ~105 while operating at -10 V. These devices exhibited remarkable stability under effects of gate bias stress and large number of repeated transfer scans with negligible performance spread. In addition, these devices displayed very stable electrical characteristics after long exposure periods to 1 ACS Paragon Plus Environment

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humidity, and an excellent shelf life of more than 6 months in ambient environment. Thermal stress at high temperatures however deteriorates the device characteristics due to generation and propagation of cracks in the active semiconductor crystals. Furthermore, novel paper based phototransistors have been demonstrated with these devices.

I.

INTRODUCTION

Organic field effect transistors (OFETs), which are highly sought after for their applications in display circuitry1,2, RFIDs3-4 and sensors5-9 truly symbolize the advantages of organic electronics like low cost, light weight, convenient processing and vast material options over other technology domains. Besides these merits, due to unique advantage of inherent flexibility in organic materials, OFETs and other organic devices can be successfully realized not only on the conventional rigid substrates like Si and glass but also on unconventional flexible substrates like plastic10-13, paper14-15 and cloth16 unlike their inorganic counterparts, which are less preferable choices in flexible electronic applications. Incorporation of unconventional substrates like plastic (plastic electronics), paper (paper electronics) and cloth (textile electronics) in realization of organic devices is one among several novel research avenues in the area of flexible organic electronics. Plastic electronics has witnessed tremendous advancement in the previous decade with numerous studies conducted on several architectural and procedural aspects. Due to this wide scale exploration, plastic platforms, even after being costlier than other flexible substrates, remain quite popular globally among researchers for organic device fabrication. However, more economic flexible substrates like paper and cloth suffer from severe microscopic surface non-uniformity and mechanical fragility, which makes

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realization of highly stable device performance on these substrates a very challenging task17. Reports on paper and cloth based organic devices are rare until recently14, 16, 18-21. A few studies report viable device fabrication on paper substrates and analyze the device performance. High performance and stability have been reported with TIPSpentacene:PTAA blend OFETs with CYTOP/Al2O3 hybrid dielectric on nanocellulose/glycerol and HD 230 paper substrates14, 22. P3HT based OFETs with ion-gel dielectric have also been explored on biodegradable cellulose paper substrates18. In addition, DNTT based OFETs have shown steep sub-threshold slope with AlOx-SAM gate dielectric on commercial paper23. However, despite several reports on high performance paper based OFETs, the aspect of device stability under external stress conditions remain under-explored. Extensive investigation of this facet of device performance is imperative to address for productive fostering of the field and to cater the increasing demand of solutions to futuristic applications by the route of unconventional electronics. In this study, high performance operationally stable solution processed organic field effect transistors have been demonstrated on paper substrate. OFETs have been fabricated using TIPS-pentacene:PS blends on HfO2/PVP bi-layer dielectric layer. Even on a nonuniform paper substrate, OFETs exhibit average and maximum mobility values of 0.22(±0.11) and 0.44 cm2 V-1 s-1 respectively, avg. threshold voltage of 0.021(±0.63) V and current on-off ratio approaching 105. In addition to high performance, devices display remarkable stability under effects of electrical stress and prolonged exposure to high humidity. Excellent performance and stability arise from the contributing factors of



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uniform surface morphology, high molecular order and superior interfacial conditions. Moreover, a noticeably long shelf life (more than 6 months) in ambient environment is recorded for these devices. Thermal stress at high temperatures however deteriorates the device characteristics due to generation and propagation of cracks in the active semiconductor crystals. In addition, the realization of paper-based phototransistors is also accomplished with these devices.

II.

EXPERIMENTATION

Device Fabrication: OFETs were fabricated in top-contact bottom-gate architecture on PowerCoat™ HD 230 paper (thickness 220 µm, surface roughness < 20 nm as per manufacturers specifications) from Arjowiggins Creative Papers. All other materials used in the study, were purchased from Sigma-Aldrich and used directly without further purification. The substrates with 1 inch × 1 inch size were pasted on the glass slides using Kapton tape and cleaned with heavy blow of N2 to remove the dust particles from the surface. A solution of 8 wt. % polyvinyl alcohol (PVA) is prepared in deionized water and stirred at 80 °C for 3 h. For smoothing the paper surface and depositing a barrier layer, the PVA solution was deposited on top of the paper substrate by spin coating at 1000 rpm for 60 s followed by annealing at 60 °C for 10 minutes. A 100 nm thick sliver (Ag) layer is deposited using thermal evaporation to form the gate electrode. A solution of 3.4 wt. % Poly(4vinylphenol) (PVP, MW ~ 25,000) and 1.1 wt. % poly(melamine-co-formaldihyde) which is a cross-linking agent, was prepared in propylene glycol monomethyl ether acetate (PGMEA) and stirred at room temperature for 24 h. The PVP solution was


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deposited on the top of the gate electrode by spin coating at 1500 rpm for 60 s to achieve a dielectric layer with the thickness of ~160 nm. Samples were then placed on hot plate at 80 °C for few minutes to evaporate the residual solvent, followed by annealing at 100 °C for 3 h to promote crosslinking. A 40 nm thick HfO2 layer was deposited on PVP layer, by atomic layer deposition at 100 °C using using tetrakis(dimethylamido)hafnium (TDMAH) and H2O as precursors in a savannah S-200 ALD system from Cambridge nanotech. To make the active organic semiconductor layer, solutions of 0.5 wt. % each of TIPS-pentacene and PS (MW∼ 280,000), were stirred in toluene separately for 3 h. After 3 h, the blend solutions were prepared by mixing TIPS-pentacene and polymer stock solutions in 1:1 ratio by volume, followed by vigorous shaking. The blend solution was dispensed on top of HfO2 layer and the substrates were then covered with glass petri-dish to provide solvent rich environment to the drying film, and left overnight. Later a 200 nm thick Au layer was deposited by thermal evaporation under high vacuum of 10-6 Torr to form Source-Drain electrodes using shadow mask. Figure 1(a)-(c) show the digital image of the bare paper, the schematic of the fabricated device and the digital image of fabricated devices respectively. All solution preparation and sample processing steps were performed in dark and ambient conditions. The exact channel length (L) and width (W) of the devices were obtained from the length and width of semiconductor crystals joining source and drain regions. Surface morphologies were captured by atomic force microscopy (AFM) using SPM XE-70 from Park Systems. Electrical Characterization: Electrical measurements were performed using Keithley 4200 SCS analyzer in ambient conditions with relative humidity (RH) of ~20% and relatively constant environmental 5 ACS Paragon Plus Environment


conditions

were

maintained

around

characterization

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setup

during

the

entire

characterization span. sat and VTH were extracted from the highest slope of the linear fit of |IDS|1/2 vs. VGS plots using the saturation region drain current equation for standard transistors, 1

𝑊

2

𝐿

𝐼DS = 𝜇𝐶i

(𝑉GS − 𝑉TH )2

(1),

Where Ci is the capacitance density of the gate dielectric layer. Value of Ci for devices have been measured through metal-insulator-semiconductor (MIS) structure and found to have value of 9.00(±1.16) nF/cm2.

(a)

(b)

(c)

Figure 1. (a) Digital image of the paper substrate, (b) Device structure of the top contact bottom gate TIPS-pentacene paper OFET and (c) Digital image of the fabricated device on paper substrate.

Reliability Characterization To explore the operational stability 100 continuous transfer characteristics measurement cycles, DC bias stress measurement at VDS = VGS = -10 V for 3600 s, and transfer characteristics measurement with varying DC bias stress time were performed. To 6 ACS Paragon Plus Environment

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investigate the effect of humidity, the samples were placed inside a small chamber with constant humid condition (95% RH) for various time intervals and then the electrical measurements were performed immediately after taking the samples out of humidity chamber after each exposure. To study the effect of annealing temperatures, the devices were annealed at a particular temperature for 1800 s and then the devices were allowed to cool down in ambient and the electrical measurements were then carried out, the similar procedure was followed with increasing annealing temperature. UV irradiation study was performed by illuminating devices with a UV light source having peak wavelength of 365 nm. The UV source used in the study was a 2 terminal UV LED, which was allowed to be irradiated from the top of the device with the maximum intensity of 1.8 mW/cm2. To investigate the environmental stability of devices, samples were kept in a petri-dish under ambient conditions and electrical measurements were recorded at fixed intervals until 6 months. III.

RESULTS AND DISCUSSION

Surface morphologies and associated interfacial conditions of each layer involved in OFET fabrication are very crucial factors, which influence the electrical performance of the OFETs very critically. Previous studies have suggested that devices with layers having uniform morphologies and high quality interfaces tend to show ameliorated electrical performance mainly due to less-hindered charge transport in the improvedquality semiconducting film with fewer defect states24-27. Figure 2(a) and (b) show the AFM images of the bare HD 230 paper surface and PVA layer (thickness ~800 nm) deposited over the paper surfaces respectively. The bare paper surface was found to have an avg. surface roughness (Rq) of 11.9(±4.0) nm, which is quite uneven for OFET



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fabrication process. To make the substrate viable for further processing, thick film of PVA was deposited over the paper surface. The polymeric PVA layer was found to be amorphous hence suppressed the surface roughness to a value of 3.3 (±1.1) nm. Figure 2(c) and (d) show the AFM image of the PVP and HfO2 surface which are the major dielectrics used in the study and found to have the surface roughness of 0.88(±0.05) and 0.81(±0.06) nm respectively. Thus, the HfO2 surface over which the active layer is to be deposited was found suitable with smooth and uniform surface for viable OFET fabrication. Figure 2(e) shows the general terracing structure of TIPS-pentacene crystallite obtained above the bilayer dielectric. Figure 2 (f) shows the frequency dependent Ci curve for the PVP/HfO2 hybrid dielectric layer which demonstrate very low change in capacitance in a broad frequency range. In addition, the bilayer structure has demonstrated low leakage current density, which is shown in Figure 2 (g).

Figure 2. Surface morphology of (a) Bare paper substrate, (b) PVA coated paper substrate, (c) PVP dielectric surface and (d) HfO2 surface over which active layer was


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deposited. (e) Surface morphology of TIPS-Pentacene crystal (f) C-f and (g) J-V characteristics for PVP/HfO2 bilayer dielectric. Figure 3 shows the transfer and output characteristics for a representative device fabricated on PVA deposited paper substrates. The devices exhibited excellent p-channel characteristics with the maximum and average field-effect mobility of 0.44 and 0.22(±0.11) cm2 V-1 s-1 respectively, avg. threshold voltage (VTH) of 0.021(±0.63) V, and current on-off ratio (Ion/Ioff) approaching 105 with relatively lower operating voltage of 10 V. The summary of electrical parameters extracted from 23 devices is summarized in Table 1. The extracted parameters reveal that despite the uneven surface of paper substrate, the performance of these paper-based devices is comparable to the many recently reported TIPS-pentacene OFETs on glass and plastic substrates. The high performance of these devices can be attributed to many possible reasons, which include surfaces with smooth morphologies, crystalline behavior of the active layer and high quality of dielectric-semiconductor interface.



1.2 VDS= - 10 V

1E-6

1.0

1E-7

0.8

1E-8

0.6

1E-9  = sat

0.4 2

1E-10 0.44 cm /Vs 1E-11 1E-12

-5

VGS = 0 to -10 V Step = -2 V

0.8

0.4

0.2

W/L= 700m/94m

-10

(b) 1.2 -IDS(A)

1E-5

(-IDS)1/2(A)1/2

(a)

-IDS(A)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

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0.0

0.0

0

VGS(V)

-10 -8 -6 -4 -2

VDS(V)

0

Figure 3. (a) Transfer, and (b) Output characteristics of the representative device.

The initial PVA layer on the paper substrates acts as a planarization layer and provides a smoother surface morphology for deposition of subsequent layers. Further, the morphology is improved successively with deposition of PVP layer and HfO2 layer (avg. roughness 0.81 nm), which is well supported by AFM, as discussed earlier. Thus, an ideal surface with very smooth and even morphology is obtained for active layer deposition. Second reason can be the improved degree of crystallinity of the TIPS-pentacene crystal, which is achieved due to enhanced molecular order in the retarded process of solvent evaporation in the drop cast procedure. Another major factor resulting into high device performance is the formation of a uniform dielectric-semiconductor interface in blends of small molecule organic semiconductor such as TIPS-pentacane with polymer binder like PS through the process of vertical phase separation28-31. Vertical phase separation in TIPS-pentacene:PS blends results in to a tri layer structure of TIPS-pentacene:PS:TIPSpentacene, as reported earlier by our group32 and in many other studies33-36. A uniform 10 ACS Paragon Plus Environment

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quality dielectric-semiconductor interface thus evolved in OFETs supports charge transport with fewer obstructions along the conduction pathway leading to superior electrical characteristics in the corresponding devices. Table 1. Summary of the electrical parameters for the fabricated paper OFETs. Avg. for

23 Devices

Capacitance Density (nF/cm2)

μsat (cm2/Vs)

µmax (cm2/Vs)

VTH(V)

9.0(±1.16)

0.22(±0.11)

0.44

0.021(±0.63)

Ion/Ioff 104-105

To examine the bias stress stability, paper based OFETs were subjected to electrical stress (VDS = VGS = -10 V) for time duration varying from 0 to 3600 s and transfer measurements were performed after each stress time. The effect of varying the bias-stress duration on the transfer characteristics is depicted in Figure 4(a). Small changes were observed in device characteristics, when stress duration was gradually changed from 0 to 3600 s. This suggests that stress periods as large as 3600 s are also unable to effectively degrade the device characteristics. To investigate the bias stress stability of devices further, a particular device was subjected to electrical stress with the stress condition of VDS = VGS = -10 V for a period of 3600 s. Figure 4(b) shows the normalized drain current decay characteristics for this particular device. Under stress conditions, the ON current decays as a stretched exponential function of time due to charge trapping in various locations including bulk of the semiconductor, disordered areas of semiconductor, grain boundaries of semiconductor and dielectric-semiconductor interface37-40. The device demonstrated a small decay of 8.5 % in the ON current indicating a smaller number of charge trapping sites and an operationally stable device, also inferred from Figure 4(a).



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Reasons similar to that for high electrical performance can be ascribed to bias stability also. Superior surface morphology, molecular order and interfacial conditions causes less number of trapping sites at various locations, which eventually reduces the charge trapping. This phenomenon is reflected through small decay in IDS, indicating small magnitude of bias stress induced instabilities. Mathematically, the normalized decay in the drain current in the saturation regime can be expressed as the ratio of the IDS at time t and 0 s, and can be given as (2) 41 𝐼DS (t) 𝐼DS (0)

t 𝛽

= exp (−2 { } ) 𝜏

(2)

Where temperature dependent dispersion parameter β reflects the width of involved trap distribution and τ is the relaxation time, a measure of typical trapping time of charge carriers. These values were extracted by fitting the experimental data in equation (2) and were found to have values of 2.7 × 1011 and 0.165 for τ and β respectively. Such a high value of τ further reflects less charge trapping leading to an operationally stable device behavior.


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Figure 4. Test for operational stability. (a) Measured transfer characteristics with increasing bias stress (VDS = VGS = -10 V) duration up to 3600 s, (b) Bias stress induced decay in normalized drain current, (c) Threshold voltage shift as a function of stress duration, and (d) Continuous transfer cycle measurement up to 100 scans. The stress induced shift in threshold voltage can be represented mathematically as a stretched exponential function given as (3) 42 and is shown in Figure 4 (c), 13 ACS Paragon Plus Environment


𝑡 𝛽

|∆𝑉TH (𝑡)| = |𝑉GS − 𝑉TH0 | [1 − 𝑒𝑥𝑝 {− ( ) }] 𝜏

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(3)

It can be deduced from the Figure 4(c) that devices experienced only a small shift of 0.4 V in the threshold voltage after undergoing fixed bias stress for 3600 s, again confirming the high stability of devices under large stress durations quantitatively. The electrical stability of these devices was also explored by an alternative route, by subjecting devices to 100 continuous transfer characteristic measurement cycles as shown in Figure 4 (d). The devices exhibited very less performance spread with minuscule changes in ON current and threshold voltage. All these outcomes indicate minimal degree of charge trapping at various locations in the device due to aforementioned reasons of improved morphology, crystalline order and interfacial conditions, which is reflected through a high electrical stability in these devices. Further, to test the reliability of devices under extreme environmental conditions two types of investigations were performed, where the stability of device performance was analyzed in humid and environmental conditions respectively. In the first study, the devices were placed in a small chamber with highly humid environment, and electrical characterization of the devices was performed immediately after taking samples out in ambient environment. The successive exposure and characterization process is continued with increased humidity exposure time. Figure 5 (a) shows the effect of increasing humidity exposure time on the transfer characteristics of the representative device. The devices exhibited negligible variation in electrical performance even after long exposure periods of 3600 s to extreme humid conditions (95% RH), demonstrating outstanding electrical stability of OFETs on unconventional paper substrate. Plot of variation of µsat and VTH with humidity exposure time is presented in Figure 5 (b). For a set of 6 devices 14 ACS Paragon Plus Environment

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considered for investigation, very little deterioration was observed in µsat and VTH affirming high stability of performance parameters under humid conditions. This remarkable stability of OFETs under highly humid conditions can be associated with hydrophobic nature of polymeric binder PS, which forms uniform and high quality dielectric-semiconductor interface with TIPS-pentacene during the process of vertical phase separation. PS resists the dielectric-semiconductor interface degradation by repelling the moisture, which could have otherwise initiated severe charge trapping deteriorating the device performance7, 43.

Figure 5. Stability test under humid environment. (a) Transfer characteristics scans with varying device exposure time to humidity (Relative Humidity = 95%) and (b) Plot of variation in mobility and threshold voltage with varying humidity exposure time.



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Figure 6. Demonstration of shelf life time stability. Effect on transfer characteristics of the devices measured during storage in ambient environment for a period of 6 month 16 ACS Paragon Plus Environment

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in (a) logarithmic and (b) linear scale and (c) Plot of variation in mobility and threshold voltage as a function of time (months). Surface morphology of TIPS-Pentacene crystals for (d) pristine and (e) after 6-month environmental exposure. Second, to explore the long-term environmental stability, devices were exposed to ambient air with humidity values ranging from 20-30 % for a period as long as 180 days and electrical measurements were taken periodically under ambient conditions. Figure 6 (a) & (b) show the transfer characteristics of a representative device in logarithmic and linear scale, measured at different time intervals and the extracted mobility and threshold voltage values are shown in Figure 6 (c). The surface morphologies of active layer before and after 6-month of environmental exposure are shown in Figure 6 (d) and (e) respectively. Both obtained morphologies are the general terracing structure of TIPSpentacene crystallite and remain unaffected. The invariability in terracing structure before and after six months of environmental exposure suggests air stable nature of TIPSpentacene (further strengthened due to addition of PS). It can be observed that even after air-exposure for more than 6 months, there is little change in device performance (∆IDS = 18.5 %, |∆VTH|= 0.15 V, ∆µsat= 0.09 cm2 V-1 s-1), which indicates outstanding air-stability and long shelf life of the devices under ambient conditions. To the best of authors’ knowledge, this is one among the longest shelf life reported for OFETs on paper substrate. Such excellent air stability can be jointly attributed to the air stable and water repellant nature of the TIPS-pentacene and PS film respectively. The functional groups available at 6 and 13 positions protect the TIPSpentacene molecule from oxidation under ambient conditions, imparting the air-stable characteristics7, 43. In addition, water repellant nature of PS resists the moisture-induced



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degradation of TIPS-pentacene:PS interface. These factors lead to preserve the device characteristics for a long time making them suitable for reliable circuit and sensing applications. Next study involved analysis of effect of annealing temperature on the device performance. To investigate this effect, the paper based OFETs were annealed at different temperatures varying from 40 ˚C to 100 ˚C for duration of 1800 s. Annealing process was immediately followed by electrical characterization. All electrical measurements and annealing processes were carried out in ambient air. Figure 7 (a) shows the variation in transfer characteristics of a representative device, which were acquired after annealing the device at different temperatures. It can be observed from the figure that transfer curve is shifted a little towards right for initial annealing temperatures of 40 ˚C and 60 ˚C. In addition, the characteristics of device annealed initially at 40 ˚C exhibits a slight improvement in ON current and threshold voltage (VTH) in comparison to that recorded at room temperature. This initial improvement in the device performance can be attributed to evaporation of residual solvent and release of any strain present in the active layer because of the redistribution of grains at low-temperature annealing, which eventually leads to improved crystallization and ordered TIPS-pentacene molecules44. These events thus enhance the molecular ordering and granular arrangements, leading to improved device performance. However, with further increase in annealing temperature the ON current reduced monotonically with shift in the transfer curve towards the negative VGS direction that denotes the negative shift in VTH. Plot of variation in various extracted electrical parameters with increasing annealing temperature is shown in Figure 7 (b). For a set of 4 devices considered for the experiment, the mobility values were reduced from


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0.16(±0.09) cm2 V-1 s-1 for pristine case to 0.06(±0.02) after 80 ˚C annealing, which further reduced to 0.03(±0.02) after annealing at 100 ˚C, with a cumulative degradation of 81% in mobility values. The threshold voltage values were negatively shifted with the value of -0.65(±0.23) for pristine devices to -0.79(±0.03) after annealing the devices at 100 ˚C. The ON current, which was improved on initial low temperature annealing, further deteriorated by more than two folds after the 100 ˚C annealing. This performance degradation at high annealing temperature occurs mainly due to the physical degradation of the active layer crystals because of the thermally generated cracks and their propagation. One of the probable reasons for these crack generation may be the inelastic stress developed during the thermal annealing above 60 ˚C

44

. These cracks and defects

further function as charge trapping centers, leading to reduced device performance. Moreover, the device performance may also degrade due to permanent loss in the crystallinity of the active layer at higher annealing temperatures. To confirm the macroscopic deterioration of semiconducting crystals, optical micrographs of the crystals annealed at different temperatures were captured. It can be clearly observed from the Figure 7 (c, d & e) that no cracks were developed in crystals till initial annealing at 60 ˚C as the TIPS-pentacene crystals appear similar to that in the pristine case. However, with further increase in annealing temperature the cracks were gradually developed and propagated. After annealing at 100 ˚C (Figure 7 (e)), crystals appeared brittle and rough with evolution of large cracks on their top surface, indicating crystal rupture and concomitant degradation in electrical performance. The AFM images of active layer for pristine and annealed samples were also investigated and are shown in Figure 7 (f) and (g) respectively. It can be seen that pristine crystallite has a normal terrace structure,



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whereas in the annealed crystallite, terrace structure appears faded/flattened with presence of crack-like features. Figure 7 (h) shows the X-ray diffractogram of active layer for pristine and annealed samples. It can be observed that the peak intensities were increased a little when sample was annealed at 60 °C because of improved crystallization and ordering in TIPS-pentacene due to evaporation of residual solvent and release of any strain present. However, the peak intensity drastically decreased when the active layer is annealed at 100 °C, which is due to physical degradation of TIPS-pentacene crystals at higher temperature with generation of large cracks. Diffractogram results discussed above, are in very good agreement with those obtained from electrical characteristics and optical micrography.


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Figure 7. Effect of annealing temperature. Plot of variation in (a) Transfer characteristics, (b) Mobility, threshold voltage and IDON (maximum ON current at VGS = 21 ACS Paragon Plus Environment


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10 V) with annealing temperatures. Optical micrographs of semiconductor crystals for (c) Pristine, (d) 60 ˚C, and (e) 100 ˚C annealed devices. Surface morphology of (f) pristine and (g) 100 ˚C annealed active layer, showing crystal rupture at high temperature annealing leading to performance deterioration of devices. (h) X-ray diffractogram of active layer for pristine and annealed samples.

To check the utility of these paper OFETs in low cost sensors they were tested for photo sensing and was found that these paper-based OFETs can also function as phototransistors. To examine their photo-response, devices were exposed to UV irradiation. Figure 8 (a) and (b) show the variation in transfer and output characteristics of a representative device under dark and UV illuminated conditions. Upon UV exposure, there is significant change in the transfer curve, with a positive shift of 1.04(±0.53) V in VTH for the four devices under consideration. Their photo-response is a combination of photoconductive and photovoltaic effects (visualized as increase in the drain current and positive shift in VTH respectively) and is due to widely accepted phenomena of UV photons stimulated exciton-generation in the active layer, their eventual dissociation into free electrons and holes, subsequent collection of holes at drain electrode and trapping of electrons at interface45-46. Figure 8 (c) shows the effect of increasing illumination time on a representative device, where the characteristics were measured in dark after the illumination for a particular time. As the illumination time increases from 0 to 1000 s, the transfer curve shifts towards positive VGS direction, ultimately resulting in positive shift in VTH. The increased shift in VTH can be attributed to the increased degree of exciton generation and subsequent minority charge trapping as discussed before. Plot of variation in μsat , VTH and ON current (at VDS = -5 V & VGS = -10 V) with illumination time is 22 ACS Paragon Plus Environment

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shown in Figure 8 (d). The mobility values and ON current continues to degrade after a small initial increment, whereas the VTH increases and saturates with increasing illumination time.

Figure 8. Phototransistor. (a) Transfer and (b) Output characteristics of paper OFET under UV illumination. (c) Effect of UV illumination time on the transfer characteristics 23 ACS Paragon Plus Environment


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of the OFET. (d) Plot of variation of mobility, threshold voltage and IDON (maximum ON current at VGS = -10 V) with increasing UV illumination time.

On the initial illumination drain current increases due to prevalent photoconductive effect, whereas at higher values of illumination time, drain current is reduced due to UV induced permanent deterioration (bond rupture and defect generation) of the active layer. It should be noted that this photo-response has been obtained from the solution processed OFETs on unconventional paper substrate while operating at lower voltages (5-10 V range). To the best of authors’ knowledge, paper based phototransistors have been demonstrated for the first time in this study. Such reasonably well performance of paper based OFETs demonstrates that several other unconventional and highly biodegradable substrates like paper also have the potential to be viably used for various device applications like circuits and various kinds of sensors, despite of their rare usage currently.

IV.

CONCLUSION

In this paper, bottom gate top contact organic field-effect transistors with high performance and stability fabricated on PowerCoat™ HD 230 paper substrate have been reported. The solution processed paper based devices with TIPS-Pentacene:PS blend as active layer and HfO2/PVP as hybrid gate dielectric exhibited maximum field effect mobility of 0.44 cm2 V-1 s-1, near zero threshold voltage and current on-off ratio approaching 105, while operating at a comparatively lower voltage of -10 V. These paper based devices demonstrated highly stable behavior under gate bias stress, large number of


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repeated transfer measurement cycles and large duration exposure to high humidity, with negligible performance spread. In addition, a long ambient shelf life (more than 6 months) was observed. A slight improvement in the device performance was noticed when annealed at low temperatures, whereas high temperature annealing deteriorated the device characteristics due to crack generation and propagation in the active layer. Furthermore, these devices were successfully demonstrated as viable phototransistors on the paper substrate. AUTHOR INFORMATION Corresponding Author *Shree Prakash Tiwari. Email: [email protected]

Notes The authors declare no competing financial interest.

ACKNOWLEDGEMENTS Authors would like to acknowledge Visvesvaraya Ph.D. Scheme (Ministry of Electronics & IT) for providing financial support.

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Table of Content (TOC) Graphic

1E-5

VDS = -10 V

1E-6

-IDS(A)

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1E-7 W/L = 700m/94m

1E-8

Pristine 1 Month 2 Month 4 Month 6 Month

1E-9

1E-10 1E-11 1E-12

-10

-5

0

VGS(V)


Solution Processed Organic Field-Effect Transistors with High

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