Flexible Proton-Gated Oxide Synaptic Transistors ... - ACS Publications

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Flexible Proton Gated Oxide Synaptic Transistors on Si Membrane Li Qiang Zhu, Changjin Wan, Pingqi Gao, Yanghui Liu, Hui Xiao, Jichun Ye, and Qing Wan ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b05167 • Publication Date (Web): 29 Jul 2016 Downloaded from http://pubs.acs.org on August 2, 2016

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Flexible Proton Gated Oxide Synaptic Transistors on Si Membrane Li Qiang Zhu1, *, Chang Jin Wan1, Ping Qi Gao1, Yang Hui Liu1, Hui Xiao1, Ji Chun Ye1, Qing Wan2, * 1) Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201, People’s Republic of China 2) Nanjing University, School of Electronic Science & Engineering, Nanjing 210093, Jiangsu, Peoples Republic of China

ABSTRACT: Ion conducting materials have received considerable attentions for the applications in fuel cells, electrochemical devices and sensors. Here, flexible indium-zincoxide (InZnO) synaptic transistors with multiple pre-synaptic inputs gated by proton conducting phosphorosilicate glass based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multi-gates coupled flexible proton gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Keywords: Proton Gating, Electric-double-layer (EDL), Flexible Si membrane, Artificial synapses, Spiking logic.

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1. Introduction Conventionally, ionic contamination in Si-based integrated circuits would result in degraded electrical behaviors. While in recent advancements of condensed materials, ionic/electronic interaction offers rich physics and device functions, such as electrochemical devices 1, 2 and field-induced electronic phase transitions 3. In ion transistors, ions and charged molecules act as charge carriers.

4, 5

Due to the fact that such carriers carry specific chemical

information, ion transistors can be useful in delivering, regulating and establishing signaling patterns of ions and biomolecules.6 Ions also play an important role for biological responses in biological systems. Our brain consists of ~1011 neurons and each neuron is connected with other neurons through 103~104 synapses.7 Learning and memory functions of our brain are realized through ionic fluxes in neurons and synapses 8, 9, which involves physical alterations in neuronal substrates that modulate neuron activities and communications. Such ionic fluxes related information storages and retrievals occur by re-wiring the neuronal networks. With massive parallelism, structural plasticity and fault-tolerance of the neural activities, such architectures make our brain possess a significant computational ability. 10 As comparison, the energy consumption for brain computation is only ~20 W.

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Inspired by the high efficiency

of neural computation in biological systems, neuromorphic systems based on solid-state neural network have attracted much attention.12-14 Nanoscale ionic/electronic hybrid memristors were proposed for biologically-inspired neuromorphic circuits applications, such as memristors, atomic switch, etc. 15-18 Important synaptic responses have been demonstrated, such as spike-timing dependent plasticity (STDP) and short-term memory (STM) to long-term memory (LTM) transition. Transistors have also been proposed for emulating biological synaptic functions including hybrid nanoparticle organic memory field-effect transistors and electrolyte gated transistors (EGTs)

19, 20

21-23

. In EGTs, the migration of ions within the

electrolytes can modulate the carrier transport characteristics of solid-state materials greatly. 24

The ion-related electrostatic and electrochemical modulation processes in these devices 2 ACS Paragon Plus Environment


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make EGTs ideal candidates for synapse emulation. Several synaptic functions have been mimicked based on EGTs, such as short-term plasticity, signal processing, spatiotemporal dynamic logic, learning functions, dynamic filtering, etc. These achievements greatly enrich the intension of bionic electronic synapses, which provides new ways to realize neuromorphic systems. Flexible electronics are also attracting more and more attentions with the recent interests in smart biomimetics skin

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, brain/computer interface

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, wearable electronics

28, 29

substrate

27

, and electronic

. These devices require flexible substrates including plastic substrate 31

, and cellulose nanofibrillated fiber substrate

30

, paper

32

. Moreover, new fabrication

schemes and new device configurations need to be developed. Conventionally, complementary metal oxide semiconductor (CMOS) chips are fabricated on Si wafers with thickness of several hundred micrometers. But only the top part of the wafers acts as functional layer with a thickness of below ~1 micrometer. The rest of the Si substrate just acts as the mechanical support. With inherent limitations for the highly purified, expensive and rigid substrates, there are obstacles for Si wafers for low-cost flexible electronics applications. Recently, flexible devices have been fabricated using Si membrane including tactile sensor for artificial skin applications 33, high-performance giant magnetoresistive sensory 34, and CMOS inverters

35

. In the present work, proton gated oxide synaptic transistors with multiple pre-

synaptic inputs were self-assembled on flexible Si membranes. With field-configurable proton gating effects within proton conducting phosphorosilicate glass (PSG), short-term synaptic plasticities were mimicked on the proposed flexible synaptic transistors. The effects of tensile strain were investigated. With synaptic integration regulation, spiking logic modulations were realized based on the transition between superlinear and sublinear synaptic integration. The multi-gate coupled flexible oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.


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Figure 1. (a) Schematic diagram for obtaining flexible InZnO synaptic transistor with multi pre-synapses on Si membrane. (b) Optical image of the InZnO transistor. (c) Cross-sectional SEM image of the as obtained Si membrane. Top-right inset: the top-view SEM image. Lower-right inset: AFM image of the Si membrane. (d) Frequency-dependent specific capacitance of the PSG film under different tensile strain. Inset: an in-plane InZnO/PSG/InZnO sandwich structure.

2. EXPERIMENTAL PROCEDURE Ultrathin Si membrane was obtained by dipping (100)-oriented p-type Si wafers (13Ωcm) in a KOH solution with a concentration of 50 wt % at 80 °C.36 Then, flexible InZnO synaptic transistors were fabricated on the Si membrane at room temperature. First, nanogranular phosphorosilicate glass (PSG) electrolyte films with thickness of ~1.2 µm were 4 ACS Paragon Plus Environment


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deposited on Si membranes by plasma enhanced chemical vapor deposition (PECVD). The detailed deposition parameters could be found in Supplementary Information (SI). Proton conductivity (σ) of the PSG electrolyte was estimated to be in the order of 10-4 S/cm. Then, InZnO transistors with multi-gate configurations were obtained on the PSG electrolyte by sputtering in pure Ar ambient with a metal shadow mask, as schematically shown in figure 1a. The detailed sputtering parameters could be found in Supplementary Information (SI). Figure 1b shows optical image of the InZnO transistor with a single gate. The channel length (L) and the channel width (W) are 80 µm and 1 mm, respectively. When the InZnO in-plane gates and the InZnO channel are deemed as pre-synapses and post-synapse, respectively, flexible proton gated InZnO synaptic transistors with multiple pre-synapses are obtained. In our previous work, we observed that the distance between the pre-synapse and the post-synapse will affect synaptic responses.

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To avoid such effects, we have fixed the distances between

the pre-synapses and the post-synapse at ~300 µm in the present work. For electrical characterizations, we have put the Si membrane on a flat platform. Bending tests were performed by wrapping the Si membrane on an out cylindrical surface of a steel semi cylinder to introduce a tensile strain. Frequency dependent specific capacitance of the PSG electrolyte film was characterized by impedance analyzer. Electrical characteristics of the InZnO synaptic transistors were investigated by Keithley 4200 semiconductor parameter analyzer. All the electrical measurements were carried out at room temperature.

3. Results and discussions Figure 1c shows cross-sectional scanning electron microscope (SEM) image of ultrathin Si membrane. Thickness of the Si membrane (T) is estimated to be ~30 µm. Top-view SEM image is included in the top-right inset for comparison. There are no observable cracks and dislocations within the Si membrane, as is desirable for flexible electronics applications. The lower-right inset illustrates an atomic force microscopy (AFM) surface morphology image for 5 ACS Paragon Plus Environment

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the as obtained Si membrane with 1 µm×1 µm scanning. The root-mean-square (rms) roughness is estimated to be ~0.5 nm, indicating that the chemical thinned Si membrane has a very smooth surface. Frequency dependent specific capacitances of the PSG films were measured with an in-plane sandwich structure under different bending radius, as shown in the inset of figure 1d. The applied surface strain at top surface of the Si membranes could be estimated with a relation below 37:

ε = T /(2 R)

(1)

where R is bending radius. Thus, the surface strain is estimated to be ~0.075% and ~0.15% for R of 2 cm and 1 cm, respectively. It is observed that the capacitance increases with the decreased frequency from 0.1 MHz to 1 Hz. A maximum specific capacitance is obtained at 1 Hz, which is due to the formation of an electric-double-layer (EDL) at the PSG/InZnO interface originated from proton migration within PSG electrolyte. The maximum specific capacitance (C0) is estimated to be ~3.3 µF/cm2 at 1 Hz, not depending on the surface strain, indicating the similar EDL coupling behaviors for different surface tensile strain. Figure S1 shows typical output characteristic curves (Ids vs Vds) of the flexible proton gated IZO transistor on a flat platform. A typical n-channel field effect character with a good pinch-off and saturation behaviors was exhibited. Figure S2 shows transfer curves of the proton gated InZnO transistor upon eight repeating Vgs sweeps with a fixed Vds at 1.5 V. The eight subsequent traces exhibit good reproducibility, indicating good stabilities for the proton gated InZnO transistor. The transistor exhibits a high on/off ratio of above 1×106, a small threshold voltage (Vth) of -0.35 V, and a small subthreshold swing (SS) of ~116 mV/decade. Fieldeffect mobility (µ) is estimated to be ~4.8 cm2/Vs. Bending tests were performed to get an idea of mechanical robustness and its effects on electrical characteristics of the flexible proton gated InZnO transistor. Si membrane with InZnO transistors on it was received repeated bending cycles for bending radius of 2 cm. 6 ACS Paragon Plus Environment


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Upon bending, the tensile strain was loaded into the out surface of the devices, as shown in Figure 2a. Figure 2b shows the transfer curves of the InZnO transistors recorded after repeated bending cycles. The flexible transistor survives after 1000 flex/flat cycles with little changes in transfer characteristics. Figure 2c illustrates the extracted electrical parameters for the InZnO transistors received bending cycles. Though there are slight changes for parameters with the increased bending cycles to 300, the parameters are quite stable with bending cycles ranged between 400 and 1000. The effects of the tensile strain on device performances were also investigated after the bending cycle measurements. Figure 2d shows the transfer curves of the InZnO transistors measured at different bending radius (R) of infinity (flat), 2 cm and 1 cm, respectively. There are no significant changes in transfer curves. Table I compares electrical parameters of the proton gated InZnO transistor obtained at different R values. With the decreased R values, threshold voltage (Vth), subthreshold swing (SS), Ion/Ioff ratios and µ are quite stable. The shifts in Vth, Ion/Ioff ratio, SS and µ are only ~30 mV, ~2 mV/dec, ~1.6×105 and ~0.1 cm2/Vs, respectively. The results observed here indicate that the flexible transistors have good mechanical reproducibility and durability.


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Figure 2. (a) Schematic diagrams for the proton gated InZnO transistor under tensile strain with a bending radius (R). (b) Transfer curves of the InZnO transistors recorded after repeated bending cycles. (c) Extracted electrical parameters of the transistors as a function of bending cycles. (d) Transfer curves of the transistors measured under tensile strain with different R values.

Table I Electrical parameters for the proton gated flexible InZnO transistor obtained at different bending radius of 1 cm, 2 cm and ∞. Bending radius

Vth (V)

Ion/Ioff ratio

SS (mV/dec)

µ (cm2/Vs)

1cm

-0.22

8.1×106

115

3.51

2cm

-0.22

6.5×106

116

3.49

∞

-0.25

7.3×106

114

3.61



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Figure 3. (a) Transient Ids of the proton gated InZnO transistor measured under a constant Vds of 0.5 V with pulsed Vgs. The amplitude is ranged from 0.2 V to 1.4 V with a step of 0.2 V. The pulse duration time is 10 ms. (b) A typical stretched exponential function (SEF) fitting for a transient Ids triggered by a pulsed Vgs (1 V, 10 ms) under a constant Vds of 0.5 V. (c) Retention time for transient Ids in (a). (d) Retention time for transient Ids under different bending radius with pulsed Vgs of (1 V, 10 ms).

Transient characteristics of the flexible proton gated InZnO transistor are also studied. Transient channel current induced by gate pulses through proton gating are recorded with a constant Vds of 0.5 V. The amplitudes of the gate pulses were altered from 0.2 V to 1.4 V with pulse duration time of 10 ms. Figure 3a shows the transient Ids for InZnO transistor on a flat platform. The peak transient Ids increases from ~3.0 µA to ~4.7 µA linearly. When the gate pulse is finished, Ids gradually decays back to a resting current of ~2.8 µA in ~300 ms. The migration of protons within the PSG electrolyte plays an important role for the transient Ids. With the increased magnitude of the gate pulses, more protons will be dissociated, which results in the increased number of protons at the interface. Thus, the InZnO channel will get more conductive with the increased number of electrons due to the EDL effects at the PSG/channel interface, which results in the increased peak Ids values. When the gate pulse stops, protons will gradually drift back to their equilibrium positions. Thus, Ids will decrease 9 ACS Paragon Plus Environment

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gradually back to the resting current. It should be noted here that the Ids decay curves could be fitted by a stretched exponential function (SEF) shown below 17, 38: I ds = ( I 0 − I ∞ ) exp[−(

t − t0

τ

)β ] + I∞

( 2)

where τ is the retention time, t0 is the time when the pulse stops, I0 is the triggered current at the end of the pulse, I∞ is the resting current and β is the stretch index ranging between 0 and 1. Figure 3b shows the transient Ids triggered by a gate pulse of (1.0 V, 10 ms). It is observed that the SEF fitting curve approaches the measured data very well, indicating the validity of the SEF for the proton gated InZnO transistor. The retention time (τ) is estimated to be ~26.6 ms. Figure 3c illustrates the obtained τ values for each transient Ids illustrated in Figure 3a. It is observed that the τ values are quite stable, scattered at ~27 ms. The stable τ values rule out the electrochemical reaction at the interface. Transient characteristics for the flexible proton gated InZnO transistor are also studied under different bending radius. Again, the τ values are still quite stable with the values of ~27.2, ~26.1 and ~26.6 ms for bending radius (R) of 1 cm, 2 cm and ∞, respectively. The results here indicate that the tensile strain has little effects on the proton gating behaviors, consistent with the obtained EDL capacitances at different bending radius (R). It is interesting to note here that the transient Ids behavior is similar to an excitatory post-synaptic current (EPSC) process in a biological excitatory synapse.

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In

biological systems, the characteristic time for neural activity is several tens of milliseconds or hundreds of milliseconds 40. Moreover, the biological activities always occur with ion signals in spike mode.

41, 42

Thus, the flexible proton gated InZnO transistors with transient

characteristics are interesting for neuromorphic system applications.



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Figure 4. (a) Schematic diagram of the EPSC triggered by a pair of temporally correlated presynaptic spikes in an InZnO synaptic transistor under tensile strain. (b) PPF Index as a function of the interval time (∆tpre) between the paired pre-synaptic spikes.

In biological neural circuits, short-term synaptic plasticity (STP) is an important form of temporal dynamics and is believed to function as a key neural mechanism for information analysis. Paired-pulse facilitation (PPF) is a phenomenon in which EPSC evoked by the spike increases when the second spike closely follows a prior one.

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With a pair of stimuli, the

second post-synaptic current (or post-synaptic potential) can be larger than the magnitude of the first one. PPF is thus a form of short-term synaptic plasticity and was reported to be important for decode temporal information in biological system.

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The flexible proton gated

InZnO transistor could emulate the PPF behavior in a biological synapse. Two pre-synaptic spikes (0.5 V, 10 ms) are applied on pre-synapse in close succession with a constant Vds of 0.3 V. The inter-spike interval (∆tpre) ranges between 20 ms and 1500 ms. The bending radius is set to 2 cm. Figure 4a shows a schematic diagram of the EPSC triggered by a pair of temporally correlated pre-synaptic spikes in an InZnO synaptic transistor under tensile strain. PPF Index, defined as 100%×A2/A1, is illustrated in Figure 4b as a function of interval time (∆tpre) between the paired pulses. A maximum PPF Index value of ~170% is obtained at ∆tpre=20 ms. When ∆tpre increases, PPF Index value decreases gradually. In biological 11 ACS Paragon Plus Environment

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synapses, PPF Index decreases as the inter spike interval increases. Such decay is reported to be divided into a rapid phase lasting tens of milliseconds and a slower phase lasting hundreds of milliseconds based on a double exponential decay relation 42:

PPF Index = 1 + C1 ⋅ exp(-

∆t pre

τ 1 ) + C 2 ⋅ exp(-

∆t pre

τ2)

(3)

where C1 and C2 are the initial facilitation magnitudes of the respective phases, and τ1 and τ2 are the characteristic relaxation times of the respective phases. Thus, relaxation time τ1 and τ2 are determined to be 26 ms and 148 ms, respectively. It is interesting to note here that the time scales of the rapid phase and slower phase of the InZnO synaptic transistor are similar to those observed in biological synapses.

Figure 5. (a) Schematic image of the spatial summation in a dendrite, i.e., the addition of unitary events occurred synchronously in separate regions of a dendrite. (b) Schematic illustration of the method to realize the synaptic integration on InZnO synaptic networks. (c) 12 ACS Paragon Plus Environment


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Measured EPSC sum (Psum) and arithmetic EPSC sum (P1+P2) as a function of modulatory spike (Vm). (d) “OR” logic operation and “AND” logic operation regulated by a modulatory spike (Vm) of (0.6 V, 20 ms) and (-0.6 V, 20 ms), respectively.

A neuron receives thousands of synaptic inputs from its dendrite and integrates them to process information.45 Synaptic integration plays an important role in nervous system for information transformation, which have important implications for neural computation and memory-related functions.

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Figure 5a schematically illustrates the synaptic integration

with the form of addition of unitary events occurred synchronously in separate regions of a dendrite, i.e., the spatial summation. Pre-synaptic spike arrived at pre-synapse 1 will trigger a synaptic response with an amplitude of P1 on post-synapse, while that arrived at pre-synapse 2 will trigger a synaptic response with an amplitude of P2. When the two pre-synaptic spikes arrived at pre-synapse 1 and pre-synapse 2 synchronously, the triggered synaptic response on post-synapse will have the amplitude of Psum. If Psum>P1+P2, superlinear synaptic integration is obtained. While if Psum

Flexible Proton-Gated Oxide Synaptic Transistors ... - ACS Publications

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