Letter pubs.acs.org/NanoLett
Logic Circuit Function Realization by One Transistor Mingzhi Dai and Ning Dai* Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201, P. R. China ABSTRACT: Bottom-up nanowires are very attractive building blocks for functional devices due to their controllable properties. Meanwhile, assembling nanowires into large-scale integrated circuits is a daunting challenge because for the present circuits diverse nanowires are needed to grow simultaneously together closely. Here, a nanowire trigate transistor structure is proposed which can accomplish the functions of the logic gate circuits. By adding one channel-electrode junction as the output, this interesting one-channel structure is used to realize inverter and OR logic gates. In this way, logic circuits could shrink into a single transistor. KEYWORDS: nanowire transistors, logic gates, trigate, one-channel
T
ransistors are one of the most fundamental state-of-the-art electronic devices.1−4 Here, with an additional gate deposited on the channel, a trigate structure is proposed to realize the logic circuit functions in one single channel transistor. Recently, nanowire (NW) transistors have attracted tremendous attention. Therefore, the trigate structure takes a NW transistor for example in this Letter. Meanwhile, oxide-based electric-double-layer (EDL) transistors have been studied.2−4 It is reported that, by carefully adding NW, the NW EDL transistors can be fabricated.4 Initially, the solid electrolyte films are developed by plasmaenhanced chemical vapor deposition (PECVD) on the conductive ITO glass substrates. Using SiH4 and O2 as the reactive gases, the SiO2 film with a thickness of about 2 μm is deposited on the bottom gate G1 on the top of ITO substrates. The NW channel could either be transferred onto the surface of the oxide dielectrics with the rest of the electrodes being deposited afterward or grown epitaxially from the drain and source electrodes by the Au-catalyzed vapor−liquid−solid growth mechanism. The drain and source are deposited simultaneously with the input gate G2 using radio frequency magnetron sputtering. The output gate G3 is then deposited across the middle region of the NW. There are quite a few NW fabrication routes, and detailed processes can be found in other publications.4−12 The schematic of the EDL transistor is illustrated in Figure 1a. The channel length of NW as semiconductor in green is 15 μm, and the gate capacitance is equivalent to ∼1 nm EDL thermally grown SiO2 capacitance. The technology computeraided design (TCAD) simulations based on semiconductor models and theories are performed.2,3,13,14 These semiconductor models include basic semiconductor equations, together with the basic theory of carrier statistics, effective density of states model, intrinsic carrier concentration, and energy bandgap model. The procedure in more detail can be found in other publications.2,3 The key fitting parameters for our simulation are shown in Table 1, which are in a reasonable range with the previous data shown in a single gate EDL device.3,4 The EDL transistor is a transistor with a 2% Sb-doped © 2012 American Chemical Society
Figure 1. Schematic of the oxide-based electric-double-layer (EDL) transistors with a SnO2 NW channel in green. The channel length is 15 μm, and oxide thickness is equivalent to 1 nm EDL: (a) with bottom gate G1 and top gate G2; (b) with an additional gate G3 across SnO2. l represents the channel length from the source end to G3.
Table 1. Key Parameters in Simulation SnO2 Eg (eV) dopant (cm−3) μEFF (cm2·V−1·s−1) Nc (cm−3·eV−1) Nc (cm−3·eV−1)
5.02 1.6 × 1018 106 1 × 1020 1 × 1020
SnO2 NW channel. The scanning electron microscopy (SEM) image of the SnO2 NW transistor for simulation reference is shown in Figure 2a and b.4 Here, the simulated results are similar with the results reported,4 as shown in Figure 2c, which suggests the simulation models might be available to describe the electrical properties of NW EDL transistors well. With these simulation results, a third gate G3 is added across the channel to become a trigate structure. A schematic of the trigate NW transistor is shown in Figure 1b. The bottom gate Received: September 11, 2012 Revised: October 6, 2012 Published: October 17, 2012 5954
dx.doi.org/10.1021/nl303386b | Nano Lett. 2012, 12, 5954−5956
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Figure 2. (a) SEM image of the 2% Sb-doped SnO2 NWs. (Inset) High-resolution SEM image of an individual 2% Sb-doped SnO2 NW.4 (b) SEM image of the basic structure of a transistor with an individual SnO2 NW channel.4 The additional straight line in white across the NW channel is used to represent the third gate G3. (c) Simulated transfer curve based on the simulation models, which have the key characteristics comparable to the published data as shown Table 1.
Hence, we can obtain the OR gate function as Table 2 suggests, when both VG1 and VG2 are 0 and no channel current exists (IDS
G1 and the top gate G2 are used as the input gate. G3 is the output gate. Here, the voltages applied on G1, G2, and G3 are defined as VG1, VG2, and VG3, respectively. In Figure 3, the simulation
Table 2. Truth Table for OR Gates Realized by the Structure in Figure 1b input VG1 0 0 1 1
(0 V) (0 V) (0.7 V) (0.7 V)
output VG2 0 (0 V) 1 (0.7 V) 0 1 (0.7 V)
VG3 0 1 1 1
(0 V) (0.7 V) (0.7 V) (0.7 V)
= 0), VG3 = 0. When either of the two gates G1 and G2 is 0.7 V, the channel is turned on and thus VG3 = 0.7 V. In this case, the voltage gain can be 0.7 V/0.7 V = 1. However, given l is fixed, once the channel is turned on, VG3 is l/L·VDS. Therefore, if VDS = 3 V, the voltage gain can be 2.1 V/0.7 V = 3. If the transistor is turned on with VDS = 1 V and l is equal to 10.5 μm, we can obtain the output voltage VG3 = 0.7 V. As shown in Figure 4, VG2 can effectively tune IDS at the same VG1.
Figure 3. Output curves for different conditions of the two input gate voltage: VG1 = 1 V, VG2 = 1 V (dotted line with square data points); VG1 = 1 V, VG2 = 0 V (red dashed line with square data points); and VG1 = 0 V, VG2 = 1 V (green line with square data points). The current for the second condition is greater than that for the third condition, because the bottom gate G1 has a higher capacitance than the top gate G2.
results of output curves IDS−VDS are shown for different conditions of the two input gate voltages, including: VG1 = 1 V, VG2 = 1 V (the first condition, dotted line with square data points in Figure 3); VG1 = 1 V, VG2 = 0 V (the second condition, red dashed line with square data points); and VG1 = 0 V, VG2 = 1 V (the third condition, green line with square data points). IDS for the second condition is larger than that for the third condition. This is because the bottom gate G1 has a higher capacitance for the channel than the top gate G2 does. It is consistent with the model proposed previously: there is a gate capacitance equivalent to 1 nm EDL capacitance between G1 and the channel, while there is a gate capacitance equivalent to 2 nm EDL capacitance between G2 and the channel.3 Therefore, VG1 has a greater impact on the drain current IDS than VG2. This is because, with a higher gate capacitance, G1 can change and control the current more obviously than G2 does. Now let us fix VDS = 1 V and VSS = 0 V. If we set VG3 ≥ 0.7 V to be 1 and VG3 < 0.7 V to be 0, we can define the value of VG3 by selecting the distance of G3 from the source end l. Because we know the channel length L = 15 μm, and VDS = 1 V, based on l/L = 0.7/1, we can obtain l = 10.5 μm. So if we set l = 10.5 μm, once the transistor is turned on, we can get VG3 = 0.7 V.
Figure 4. Transfer curves for different VG2, suggesting the channel can be turned on (IDS > 1 μA) by different VG1.
So we can obtain the inverter function (as shown in Table 3): when the input gate voltage (VIN) VG1 = 0, the output gate Table 3. Truth Table for a Trigate Inverter Realized by the Structure in Figure 1b
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input
output
VG1
VG3
N/A VG2
0 1 (0.7 V)
1 (0.7 V) 0 (0 V)
1 (1 V) 0 (−1 V)
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voltage (VOUT) VG3 = 1 (with VG2 = 1 V); when VG1 (VIN) = 1, VG3 (VOUT) = 0 (with VG2 = −1 V). From the data in Figure 5, we can find VOUT and VIN as in Table 3. As shown in Figure 4, when VIN = VG1 = 0 (0.69 V), IDS can be higher than 1 μA with VG2 = 1 V; that is, the channel is turned on and VOUT (VG3) = 0.7 V. When we adjust VG2 properly, we can obtain VOUT = 1 (0.7 V) at VIN = 0 (0.69 V), and VOUT = 0 at VIN = 1 (0.7 V), leading to a voltage gain ΔVOUT/ΔVIN ∼ 70. It is higher than the previous reported highest voltage gain ΔVOUT/ΔVIN ∼ 60 obtained with any molecular materials including single wall nanotube and conjugated organic materials.5
the Ningbo Natural Science Foundation of China (Grant No. Y10814VA08).
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(1) Nomura, K.; Ohta, H.; Takagi, A.; Kamiya, T.; Hirano, M.; Hosono, H. Room-Temperature Fabrication of Transparent Flexible Thin-film Transistors Using Amorphous Oxide Semiconductors. Nature 2004, 432, 488−491. (2) Dai, M.; Wu, G.; Yang, Y.; Jiang, J.; Li, L.; Wan, Q. Modeling of Low-voltage Oxide-based Electric-double-layer Thin-film Transistors Fabricated at Room Temperature. Appl. Phys. Lett. 2011, 98, 093506. (3) Dai, M.; Wan, Q. Modeling Novel Double-in-plane Gate Electricdouble-layer Thin-film and Nanoscale Transistors. Nano Lett. 2011, 11, 3987−3990. (4) Sun, J.; Liu, H.; Jiang, J.; Lu, A.; Wan, Q. Transparent SnO2 Nanowire Electric-Double-Layer Transistors with Different Antimony Doping Levels. J. Mater. Chem. 2010, 20, 8010−8015. (5) Javey, A.; Kim, H.; Brink, M.; Wang, Q.; Ural, A.; Guo, J.; McIntyre, P.; McEuen, P.; Lundstrom, M.; Dai, H. High-k Dielectrics for Advanced Carbon-nanotube Transistors and Logic Gates. Nat. Mater. 2002, 1, 241−246. (6) Kim, D. R.; Lee, C. H.; Zheng, X.-L. Direct Growth of Nanowire Logic Gates and Photovoltaic Devices. Nano Lett. 2010, 10, 1050− 1054. (7) Yan, H.; Choe, H. S.; Nam, S.; Hu, Y.; Das, S.; Klemic, J. F.; Ellenbogen, J. C.; Lieber, C. M. Programmable Nanowire Circuits for Nanoprocessors. Nature 2011, 470, 240−244. (8) Lu, W.; Lieber, C. M. Nanoelectronics from the Bottom Up. Nat. Mater. 2007, 6, 841−850. (9) Zhong, Z. H.; Wang, D. L.; Cui, Y.; Bockrath, M. W.; Lieber, C. M. Nanowire Crossbar Arrays as Address Decoders for Integrated Nanosystems. Science 2003, 302, 1377−1379. (10) Huang, Y.; Duan, X.; Cui, Y.; Lauhon, L. J.; Kim, K.-H.; Lieber, C. M. Logic Gates and Computation from Assembled Nanowire Building Blocks. Science 2001, 294, 1313−1317. (11) Bachtold, A.; Hadley, P.; Nakanishi, T.; Dekker, C. Logic Circuits with Carbon Nanotube Transistors. Science 2001, 294, 1317− 1320. (12) Cui, Y.; Lieber, C. M. Functional Nanoscale Electronic Devices Assembled Using Silicon Nanowire Building Blocks. Science 2001, 291, 851−853. (13) Hsieh, H.-H.; Kamiya, T.; Nomura, K.; Hosono, H.; Wu, S.-C. Modeling of Amorphous InGaZnO4 Thin Film Transistors and Their Subgap Density of States. Appl. Phys. Lett. 2008, 92, 133503. (14) Fung, T.-C.; Chuang, C.-S.; Chen, C.; Abe, K.; Cottle, R.; Townsend, M.; Kumomi, H.; Kanicki, J. Two-dimensional numerical simulation of radio frequency sputter amorphous In−Ga−Zn−O thinfilm transistors. J. Appl. Phys. 2009, 106, 084511.
Figure 5. Output voltage VOUT as a function of the input voltage VIN of a trigate inverter.
Compared to the previous published NW transistors and nanotube devices,5−12 here, the trigate transistor has some notable characteristics: (1) It has one transistor with one single channel and one NW−electrode junction to realize the logic gate functions, compared to the other logic gates with more than one transistor,14 multiple NWs, or one NW with multiple nanotube−electrode junctions.10,12 (2) It has a voltage gain higher than the previous known inverter.5 (3) It has a low turnon voltage, and its fabrication is simple and correlated with the conventional silicon semiconductor foundry process. A trigate transistor structure as shown in Figure 1b is proposed to realize the circuit functions. With an additional gate G3 across the channel, the logic functions used to be accomplished by transistors now could be realized in a single channel transistor with one nanotube-electrode junction. Here, we could obtain the logic functions, such as OR gate function and inverter function, using a simple single channel transistor with one NW-electrode junction. This transistor easily obtains a high gain, and it might be useful in portable electronics because the structure is simple. It may also find many useful applications in some electronics including sensors or in electrochemistry and energy storage.
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REFERENCES
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NOTE ADDED AFTER ASAP PUBLICATION This paper was published ASAP on October 19, 2012. Additional changes have been made to the manuscript. The revised version was posted on October 30, 2012.
AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected],
[email protected]. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS This work was supported by the National Natural Science Foundation of China (Grant No. 61106090), the National Basic Research Program of China (973 Program) Special Project (Grant No.2010CB933700), the Spring Project in Ningbo Institute of Material Technology and Engineering, and 5956
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